mirror of
https://github.com/apache/nuttx.git
synced 2026-06-08 01:42:58 +08:00
arch/arm/src/samv7: Add SAME70 memory map
This commit is contained in:
Gregory Nutt
@@ -44,6 +44,8 @@
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#if defined(CONFIG_ARCH_CHIP_SAMV71)
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# include "chip/samv71_memorymap.h"
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#elif defined(CONFIG_ARCH_CHIP_SAME70)
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# include "chip/same70_memorymap.h"
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#else
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# error Unrecognized SAMV7 architecture
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#endif
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@@ -0,0 +1,201 @@
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/************************************************************************************************
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* arch/arm/src/samv7/chip/same70_memorymap.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
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||||
*
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************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAME70_MEMORYMAP_H
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#define __ARCH_ARM_SRC_SAMV7_CHIP_SAME70_MEMORYMAP_H
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/************************************************************************************************
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* Included Files
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************************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/samv7/chip.h>
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/************************************************************************************************
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* Pre-processor Definitions
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************************************************************************************************/
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/* Address regions */
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#define SAM_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */
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#define SAM_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */
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#define SAM_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */
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#define SAM_MEMORY_BASE 0x60000000 /* 0x60000000-0x7fffffff: Memories */
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#define SAM_QSPIMEM_BASE 0x80000000 /* 0x80000000-0x9fffffff: QSPI memory */
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#define SAM_AXIMX_BASE 0xa0000000 /* 0xa0000000-0x9fffffff: AXIMX */
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#define SAM_USBHSRAM_BASE 0xa0100000 /* 0xa0100000-0xa01fffff: USBHS RAM */
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/* 0xa0200000-0xdfffffff: Reserved */
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#define SAM_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */
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/* Code memory region */
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#define SAM_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x00ffffff: ITCM or Boot Memory */
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#define SAM_INTFLASH_BASE 0x00400000 /* 0x00400000-0x007fffff: Internal FLASH */
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#define SAM_INTROM_BASE 0x00800000 /* 0x00800000-0x00bfffff: Internal ROM */
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/* 0x00c00000-0x1fffffff: Reserved */
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/* Internal SRAM memory region */
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#define SAM_DTCM_BASE 0x20000000 /* 0x20000000-0x203fffff: DTCM */
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#define SAM_SRAM_BASE 0x20400000 /* 0x20400000-0x20bfffff: SRAM */
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/* 0x20c00000-0x3fffffff: Reserved */
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/* Peripherals address region */
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#define SAM_HSMCI0_BASE 0x40000000 /* 0x40000000-0x40003fff: High Speed Multimedia Card Interface */
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#define SAM_SSC0_BASE 0x40004000 /* 0x40004000-0x40007fff: Serial Synchronous Controller */
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#define SAM_SPI0_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface 0 */
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#define SAM_TC012_BASE 0x4000c000 /* 0x4000c000-0x4000ffff: Timer Counters 0-2 */
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# define SAM_TC0_BASE 0x4000c000 /* 0x4000c000-0x4000c03f: Timer Counter 0 */
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# define SAM_TC1_BASE 0x4000c040 /* 0x4000c040-0x4000c07f: Timer Counter 1 */
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# define SAM_TC2_BASE 0x4000c080 /* 0x4000c080-0x4000c0bf: Timer Counter 2 */
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/* 0x4000c0c0-0x4000ffff Reserved */
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#define SAM_TC345_BASE 0x40010000 /* 0x40010000-0x40013fff: Timer Counters 3-5 */
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# define SAM_TC3_BASE 0x40010000 /* 0x40010000-0x4001003f: Timer Counter 3 */
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# define SAM_TC4_BASE 0x40010040 /* 0x40010040-0x4001007f: Timer Counter 4 */
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# define SAM_TC5_BASE 0x40010080 /* 0x40010080-0x400100bf: Timer Counter 5 */
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/* 0x400100c0-0x40013fff Reserved */
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#define SAM_TC678_BASE 0x40014000 /* 0x40014000-0x40017fff: Timer Counters 6-8 */
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# define SAM_TC6_BASE 0x40014000 /* 0x40014000-0x4001403f: Timer Counter 6 */
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# define SAM_TC7_BASE 0x40014040 /* 0x40014040-0x4001407f: Timer Counter 7 */
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# define SAM_TC8_BASE 0x40014080 /* 0x40014080-0x400140bf: Timer Counter 8 */
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/* 0x400140c0-0x40017fff: Reserved */
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#define SAM_TWIHS0_BASE 0x40018000 /* 0x40018000-0x4001bfff: Two-Wire Interface 0 (TWIHS0) */
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#define SAM_TWIHS1_BASE 0x4001c000 /* 0x4001c000-0x4001ffff: Two-Wire Interface 1 (TWIHS1) */
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#define SAM_PWM0_BASE 0x40020000 /* 0x40020000-0x40023fff: Pulse Width Modulation 0 */
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#define SAM_USART0_BASE 0x40024000 /* 0x40024000-0x40023fff: USART0 */
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#define SAM_USART1_BASE 0x40028000 /* 0x40028000-0x4002bfff: USART1 */
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#define SAM_USART2_BASE 0x4002c000 /* 0x4002c000-0x4002ffff: USART12*/
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#define SAM_MCAN0_BASE 0x40030000 /* 0x40030000-0x40033fff: Controller Area Network 0 (MCAN0) */
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#define SAM_MCAN1_BASE 0x40034000 /* 0x40034000-0x40037fff: Controller Area Network 1 (MCAN1) */
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#define SAM_USBHS_BASE 0x40038000 /* 0x40038000-0x4003bfff: USB High-Speed (USBHS) */
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#define SAM_AFEC0_BASE 0x400b0000 /* 0x4003c000-0x4003ffff: Analog Front End 0 (AFEC0) */
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#define SAM_DACC_BASE 0x40040000 /* 0x40040000-0x40043fff: Digital To Analog Converter (DACC) */
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#define SAM_ACC_BASE 0x40044000 /* 0x40044000-0x40047fff: Analog Comparator (ACC) */
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#define SAM_ICM_BASE 0x40048000 /* 0x40048000-0x4004bfff: Integrity Check Monitor (ICM) */
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#define SAM_ISI_BASE 0x4004c000 /* 0x4004c000-0x4004ffff: Image Sensor Interface (ISI) */
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#define SAM_EMAC0_BASE 0x40050000 /* 0x40050000-0x40053fff: EMAC0 (aka GMAC) */
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#define SAM_TC901_BASE 0x40054000 /* 0x40054000-0x40054fff: Timer Counters 9-11 */
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# define SAM_TC9_BASE 0x40054000 /* 0x40054000-0x4005403f: Timer Counter 9 */
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# define SAM_TC10_BASE 0x40054040 /* 0x40054040-0x4005407f: Timer Counter 10 */
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# define SAM_TC11_BASE 0x40054080 /* 0x40054080-0x400540bf: Timer Counter 11 */
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/* 0x400540c0-0x40057fff: Reserved */
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#define SAM_SPI1_BASE 0x40058000 /* 0x40058000-0x4005bfff: Serial Peripheral Interface 1 */
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#define SAM_PWM1_BASE 0x4005c000 /* 0x4005c000-0x4005ffff: Pulse Width Modulation 1 */
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#define SAM_TWIHS2_BASE 0x40060000 /* 0x40060000-0x40063fff: Two-Wire Interface 2 (TWIHS2) */
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#define SAM_AFEC1_BASE 0x40064000 /* 0x40064000-0x40067fff: Analog Front End 1 (AFEC1) */
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/* 0x40068000-0x4006bfff: Reserved */
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#define SAM_AES_BASE 0x4006c000 /* 0x4006c000-0x4006ffff: AES */
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#define SAM_TRNG_BASE 0x40070000 /* 0x40070000-0x40073fff: True Random Number Generator (TRNG) */
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#define SAM_BRAM_BASE 0x40074000 /* 0x40074000-0x40077fff: Backup SRAM (BRAM) */
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#define SAM_XDMAC_BASE 0x40078000 /* 0x40078000-0x4007bfff: Central DMA controller (XDMAC) */
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#define SAM_QSPI_BASE 0x4007c000 /* 0x4007c000-0x4007ffff: Quad SPI (QSPI) */
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#define SAM_SMC_BASE 0x40080000 /* 0x40080000-0x40083fff: Static Memory Controller (SMC) */
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#define SAM_SDRAMC_BASE 0x40084000 /* 0x40084000-0x40087fff: SDRAM Controller (SDRAMC) */
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#define SAM_MATRIX_BASE 0x40088000 /* 0x40088000-0x400e03ff: MATRIX */
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#define SAM_UTMI_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: USB Transmitter Macrocell Interface (UTMI) */
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#define SAM_PMC_BASE 0x400e0600 /* 0x400e0600-0x400e07ff: Power Management Controller (PMC) */
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#define SAM_UART0_BASE 0x400e0800 /* 0x400e0800-0x400e093f: UART 0 */
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#define SAM_CHIPID_BASE 0x400e0940 /* 0x400e0940-0x400e09ff: CHIP ID */
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#define SAM_UART1_BASE 0x400e0a00 /* 0x400e0a00-0x400e0bff: UART 1 */
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#define SAM_EEFC_BASE 0x400e0c00 /* 0x400e0c00-0x400e0dff: Embedded Flash Controller (EEFC) */
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#define SAM_PIO_BASE 0x400e0e00 /* 0x400e0e00-0x400e13ff: Parallel I/O Controllers */
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# define SAM_PION_BASE(n) (0x400e0e00 + ((n) << 9))
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# define SAM_PIOA_BASE 0x400e0e00 /* 0x400e0e00-0x400e0fff: Parallel I/O Controller A */
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# define SAM_PIOB_BASE 0x400e1000 /* 0x400e1000-0x400e11ff: Parallel I/O Controller B */
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# define SAM_PIOC_BASE 0x400e1200 /* 0x400e1200-0x400e13ff: Parallel I/O Controller C */
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# define SAM_PIOD_BASE 0x400e1400 /* 0x400e1400-0x400e15ff: Parallel I/O Controller D */
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# define SAM_PIOE_BASE 0x400e1600 /* 0x400e1600-0x400e17ff: Parallel I/O Controller E */
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#define SAM_SYSCTRLR_BASE 0x400e0000 /* 0x400e0000-0x400e1bff: System Controller */
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# define SAM_RSTC_BASE 0x400e1800 /* 0x400e1800-0x400e180f: Reset Controller (RSTC) */
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# define SAM_SUPC_BASE 0x400e1810 /* 0x400e1810-0x400e182f: Supply Controller (SUPC) */
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# define SAM_RTT_BASE 0x400e1830 /* 0x400e1830-0x400e184f: Real Time Timer (RTT) */
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# define SAM_WDT0_BASE 0x400e1850 /* 0x400e1850-0x400e185f: Watchdog Timer 0 (WDT0) */
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# define SAM_RTC_BASE 0x400e1860 /* 0x400e1860-0x400e188f: Real Time Clock (RTC) */
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# define SAM_GPBR_BASE 0x400e1890 /* 0x400e1890-0x400e18ff: GPBR */
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# define SAM_SYSC_BASE 0x400e18e0 /* 0x400e1890-0x400e18ff: System Controller Common */
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# define SAM_WDT1_BASE 0x400e1900 /* 0x400e1900-0x400e19ff: Watchdog Timer 1 (WDT1) */
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#define SAM_UART2_BASE 0x400e1a00 /* 0x400e1a00-0x400e1bff: UART 2 */
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#define SAM_UART3_BASE 0x400e1c00 /* 0x400e1c00-0x400e1dff: UART 3 */
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#define SAM_UART4_BASE 0x400e1e00 /* 0x400e1e00-0x400e1fff: UART 4 */
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/* 0x400e2000-0x5fffffff: Reserved */
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/* External RAM memory region */
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#define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x7fffffff: EBI Chip selects */
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# define SAM_EXTCSn_BASE(n) (0x60000000 + ((n) << 24))
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# define SAM_EXTCS0_BASE 0x60000000 /* 0x60000000-0x60ffffff: EBI Chip select 0 */
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# define SAM_EXTCS1_BASE 0x61000000 /* 0x61000000-0x601fffff: EBI Chip select 1 */
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# define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: EBI Chip select 2 */
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# define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x6fffffff: EBI Chip select 3 */
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#define SAM_SDRAMCS_BASE 0x70000000 /* 0x70000000-0x7fffffff: SDRAM chip select */
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/* QSPI memory region */
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#define SAM_QSPIMEM_SIZE 0x20000000 /* 0x80000000-0x9fffffff: QSPI memory */
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/* System memory region */
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#define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */
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#define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */
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/************************************************************************************************
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* Public Types
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************************************************************************************************/
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#ifndef __ASSEMBLY__
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM4S_MEMORYMAP_H */
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@@ -83,7 +83,7 @@
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/* System Bus Interfaces */
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#ifdef CONFIG_ARCH_CHIP_SAMV71
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#if defined(CONFIG_ARCH_CHIP_SAMV71) || defined(CONFIG_ARCH_CHIP_SAME70)
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# define HSMCI_SYSBUS_IF DMACH_FLAG_PERIPHAHB_AHB_IF1
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# define MEMORY_SYSBUS_IF DMACH_FLAG_MEMAHB_AHB_IF0
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#else
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@@ -44,7 +44,7 @@
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#if defined(CONFIG_ARCH_CHIP_SAMV71)
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# include "samv71_periphclks.h"
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#if defined(CONFIG_ARCH_CHIP_SAME70)
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#elif defined(CONFIG_ARCH_CHIP_SAME70)
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# include "same70_periphclks.h"
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#else
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# error Unrecognized SAMV7 architecture
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@@ -63,7 +63,7 @@
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/* Chip dependencies */
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#if defined(CONFIG_ARCH_CHIP_SAMV71)
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#if defined(CONFIG_ARCH_CHIP_SAMV71) || defined(CONFIG_ARCH_CHIP_SAME70)
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/* All sectors are 128KB and are uniform in size.
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* The only execption is sector 0 which is subdivided into two small sectors
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* of 8KB and one larger sector of 112KB.
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@@ -0,0 +1,223 @@
|
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/************************************************************************************
|
||||
* arch/arm/src/samv7/same70_periphclks.h
|
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*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMV7_SAME70_PERIPHCLKS_H
|
||||
#define __ARCH_ARM_SRC_SAMV7_SAME70_PERIPHCLKS_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <stdint.h>
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||||
#include <arch/irq.h>
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#include "chip/sam_pmc.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Helper macros */
|
||||
|
||||
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
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#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
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#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0)
|
||||
#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1)
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|
||||
#define sam_supc_enableclk()
|
||||
#define sam_rstc_enableclk()
|
||||
#define sam_rtc_enableclk()
|
||||
#define sam_rtt_enableclk()
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||||
#define sam_wdt0_enableclk()
|
||||
#define sam_pmc_enableclk()
|
||||
#define sam_efc_enableclk()
|
||||
|
||||
#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
|
||||
#define sam_uart1_enableclk() sam_enableperiph0(SAM_PID_UART1)
|
||||
#define sam_smc_enableclk() sam_enableperiph0(SAM_PID_SMC)
|
||||
#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
|
||||
#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB)
|
||||
#define sam_pioc_enableclk() sam_enableperiph0(SAM_PID_PIOC)
|
||||
#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0)
|
||||
#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1)
|
||||
#define sam_usart2_enableclk() sam_enableperiph0(SAM_PID_USART2)
|
||||
#define sam_piod_enableclk() sam_enableperiph0(SAM_PID_PIOD)
|
||||
#define sam_pioe_enableclk() sam_enableperiph0(SAM_PID_PIOE)
|
||||
#define sam_hsmci0_enableclk() sam_enableperiph0(SAM_PID_HSMCI0)
|
||||
#define sam_twihs0_enableclk() sam_enableperiph0(SAM_PID_TWIHS0)
|
||||
#define sam_twihs1_enableclk() sam_enableperiph0(SAM_PID_TWIHS1)
|
||||
#define sam_spi0_enableclk() sam_enableperiph0(SAM_PID_SPI0)
|
||||
#define sam_ssc_enableclk() sam_enableperiph0(SAM_PID_SSC0)
|
||||
#define sam_tc0_enableclk() sam_enableperiph0(SAM_PID_TC0)
|
||||
#define sam_tc1_enableclk() sam_enableperiph0(SAM_PID_TC1)
|
||||
#define sam_tc2_enableclk() sam_enableperiph0(SAM_PID_TC2)
|
||||
#define sam_tc3_enableclk() sam_enableperiph0(SAM_PID_TC3)
|
||||
#define sam_tc4_enableclk() sam_enableperiph0(SAM_PID_TC4)
|
||||
#define sam_tc5_enableclk() sam_enableperiph0(SAM_PID_TC5)
|
||||
#define sam_afec0_enableclk() sam_enableperiph0(SAM_PID_AFEC0)
|
||||
#define sam_dacc_enableclk() sam_enableperiph0(SAM_PID_DACC)
|
||||
#define sam_pwm0_enableclk() sam_enableperiph0(SAM_PID_PWM0)
|
||||
|
||||
#define sam_icm_enableclk() sam_enableperiph1(SAM_PID_ICM)
|
||||
#define sam_acc_enableclk() sam_enableperiph1(SAM_PID_ACC)
|
||||
#define sam_usbhs_enableclk() sam_enableperiph1(SAM_PID_USBHS)
|
||||
#define sam_mcan00_enableclk() sam_enableperiph1(SAM_PID_MCAN00)
|
||||
#define sam_mcan01_enableclk()
|
||||
#define sam_mcan10_enableclk() sam_enableperiph1(SAM_PID_MCAN10)
|
||||
#define sam_mcan11_enableclk()
|
||||
#define sam_emac0_enableclk() sam_enableperiph1(SAM_PID_EMAC0)
|
||||
#define sam_afec1_enableclk() sam_enableperiph1(SAM_PID_AFEC1)
|
||||
#define sam_twihs2_enableclk() sam_enableperiph1(SAM_PID_TWIHS2)
|
||||
#define sam_spi1_enableclk() sam_enableperiph1(SAM_PID_SPI1)
|
||||
#define sam_qspi_enableclk() sam_enableperiph1(SAM_PID_QSPI)
|
||||
#define sam_uart2_enableclk() sam_enableperiph1(SAM_PID_UART2)
|
||||
#define sam_uart3_enableclk() sam_enableperiph1(SAM_PID_UART3)
|
||||
#define sam_uart4_enableclk() sam_enableperiph1(SAM_PID_UART4)
|
||||
#define sam_tc6_enableclk() sam_enableperiph1(SAM_PID_TC6)
|
||||
#define sam_tc7_enableclk() sam_enableperiph1(SAM_PID_TC7)
|
||||
#define sam_tc8_enableclk() sam_enableperiph1(SAM_PID_TC8)
|
||||
#define sam_tc9_enableclk() sam_enableperiph1(SAM_PID_TC9)
|
||||
#define sam_tc10_enableclk() sam_enableperiph1(SAM_PID_TC10)
|
||||
#define sam_tc11_enableclk() sam_enableperiph1(SAM_PID_TC11)
|
||||
#define sam_aes_enableclk() sam_enableperiph1(SAM_PID_AES)
|
||||
#define sam_trng_enableclk() sam_enableperiph1(SAM_PID_TRNG)
|
||||
#define sam_xdmac_enableclk() sam_enableperiph1(SAM_PID_XDMAC)
|
||||
#define sam_isi_enableclk() sam_enableperiph1(SAM_PID_ISI)
|
||||
#define sam_pwm1_enableclk() sam_enableperiph1(SAM_PID_PWM1)
|
||||
#define sam_fpu_enableclk()
|
||||
#define sam_sdramc_enableclk() sam_enableperiph1(SAM_PID_SDRAMC) /* REVISIT: Does this exist? */
|
||||
#define sam_wdt1_enableclk()
|
||||
|
||||
#define sam_ccw_enableclk()
|
||||
|
||||
#define sam_supc_disableclk()
|
||||
#define sam_rstc_disableclk()
|
||||
#define sam_rtc_disableclk()
|
||||
#define sam_rtt_disableclk()
|
||||
#define sam_wdt0_disableclk()
|
||||
#define sam_pmc_disableclk()
|
||||
#define sam_efc_disableclk()
|
||||
|
||||
#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
|
||||
#define sam_uart1_disableclk() sam_disableperiph0(SAM_PID_UART1)
|
||||
#define sam_smc_disableclk() sam_disableperiph0(SAM_PID_SMC)
|
||||
#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
|
||||
#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB)
|
||||
#define sam_pioc_disableclk() sam_disableperiph0(SAM_PID_PIOC)
|
||||
#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0)
|
||||
#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1)
|
||||
#define sam_usart2_disableclk() sam_disableperiph0(SAM_PID_USART2)
|
||||
#define sam_piod_disableclk() sam_disableperiph0(SAM_PID_PIOD)
|
||||
#define sam_pioe_disableclk() sam_disableperiph0(SAM_PID_PIOE)
|
||||
#define sam_hsmci0_disableclk() sam_disableperiph0(SAM_PID_HSMCI0)
|
||||
#define sam_twihs0_disableclk() sam_disableperiph0(SAM_PID_TWIHS0)
|
||||
#define sam_twihs1_disableclk() sam_disableperiph0(SAM_PID_TWIHS1)
|
||||
#define sam_spi0_disableclk() sam_disableperiph0(SAM_PID_SPI0)
|
||||
#define sam_ssc_disableclk() sam_disableperiph0(SAM_PID_SSC0)
|
||||
#define sam_tc0_disableclk() sam_disableperiph0(SAM_PID_TC0)
|
||||
#define sam_tc1_disableclk() sam_disableperiph0(SAM_PID_TC1)
|
||||
#define sam_tc2_disableclk() sam_disableperiph0(SAM_PID_TC2)
|
||||
#define sam_tc3_disableclk() sam_disableperiph0(SAM_PID_TC3)
|
||||
#define sam_tc4_disableclk() sam_disableperiph0(SAM_PID_TC4)
|
||||
#define sam_tc5_disableclk() sam_disableperiph0(SAM_PID_TC5)
|
||||
#define sam_afec0_disableclk() sam_disableperiph0(SAM_PID_AFEC0)
|
||||
#define sam_dacc_disableclk() sam_disableperiph0(SAM_PID_DACC)
|
||||
#define sam_pwm0_disableclk() sam_disableperiph0(SAM_PID_PWM0)
|
||||
|
||||
#define sam_icm_disableclk() sam_disableperiph1(SAM_PID_ICM)
|
||||
#define sam_acc_disableclk() sam_disableperiph1(SAM_PID_ACC)
|
||||
#define sam_usbhs_disableclk() sam_disableperiph1(SAM_PID_USBHS)
|
||||
#define sam_mcan00_disableclk() sam_disableperiph1(SAM_PID_MCAN00)
|
||||
#define sam_mcan01_disableclk()
|
||||
#define sam_mcan10_disableclk() sam_disableperiph1(SAM_PID_MCAN10)
|
||||
#define sam_mcan11_disableclk()
|
||||
#define sam_emac0_disableclk() sam_disableperiph1(SAM_PID_EMAC0)
|
||||
#define sam_afec1_disableclk() sam_disableperiph1(SAM_PID_AFEC1)
|
||||
#define sam_twihs2_disableclk() sam_disableperiph1(SAM_PID_TWIHS2)
|
||||
#define sam_spi1_disableclk() sam_disableperiph1(SAM_PID_SPI1)
|
||||
#define sam_qspi_disableclk() sam_disableperiph1(SAM_PID_QSPI)
|
||||
#define sam_uart2_disableclk() sam_disableperiph1(SAM_PID_UART2)
|
||||
#define sam_uart3_disableclk() sam_disableperiph1(SAM_PID_UART3)
|
||||
#define sam_uart4_disableclk() sam_disableperiph1(SAM_PID_UART4)
|
||||
#define sam_tc6_disableclk() sam_disableperiph1(SAM_PID_TC6)
|
||||
#define sam_tc7_disableclk() sam_disableperiph1(SAM_PID_TC7)
|
||||
#define sam_tc8_disableclk() sam_disableperiph1(SAM_PID_TC8)
|
||||
#define sam_tc9_disableclk() sam_disableperiph1(SAM_PID_TC9)
|
||||
#define sam_tc10_disableclk() sam_disableperiph1(SAM_PID_TC10)
|
||||
#define sam_tc11_disableclk() sam_disableperiph1(SAM_PID_TC11)
|
||||
#define sam_aes_disableclk() sam_disableperiph1(SAM_PID_AES)
|
||||
#define sam_trng_disableclk() sam_disableperiph1(SAM_PID_TRNG)
|
||||
#define sam_xdmac_disableclk() sam_disableperiph1(SAM_PID_XDMAC)
|
||||
#define sam_isi_disableclk() sam_disableperiph1(SAM_PID_ISI)
|
||||
#define sam_pwm1_disableclk() sam_disableperiph1(SAM_PID_PWM1)
|
||||
#define sam_fpu_disableclk()
|
||||
#define sam_sdramc_disableclk() sam_disableperiph1(SAM_PID_SDRAMC) /* REVISIT: Does this exist? */
|
||||
#define sam_wdt1_disableclk()
|
||||
|
||||
#define sam_ccw_disableclk()
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAMV7_SAME70_PERIPHCLKS_H */
|
||||
Reference in New Issue
Block a user