ARMv7-A: Exception register save/restore needs to work a little differently if we support user mode processes

2026-09-22 06:04:28 +08:00 · 2014-09-11 14:34:10 -06:00
parent 17e798993d
commit 57d78ddd93
2 changed files with 363 additions and 33 deletions
@@ -1439,7 +1439,7 @@ o ARM (arch/arm/)
  Priority:    Low

  Title:       CORTEX-M3 STACK OVERFLOW
-  Description: There is bit bit logic inf up_fullcontextrestore() that executes on
+  Description: There is bit bit logic in up_fullcontextrestore() that executes on
               return from interrupts (and other context switches) that looks like:

                 ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the stored CPSR value */