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Merge remote-tracking branch 'origin/master' into clicker2

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This commit is contained in:
Gregory Nutt
2017-03-22 09:56:59 -06:00
parent 5861d9610c 5fb85451cb
commit 571aad3cf1
14 changed files with 409 additions and 59 deletions
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arch/arm/src/stm32/Kconfig
+10
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@@ -6190,6 +6190,16 @@ config STM32_I2C_DUTY16_9
default n
depends on STM32_I2C
config STM32_I2C_DMA
bool "I2C DMA Support"
default n
depends on STM32_I2C && STM32_STM32F40XX && STM32_DMA1
---help---
This option enables the DMA for I2C transfers.
Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the
I2C dma streams, else the default priority level is set to medium.
Note: This option is compatible with CONFIG_I2C_POLLED.
endmenu
menu "SDIO Configuration"
arch/arm/src/stm32/stm32f40xxx_i2c.c
+322 -25
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File diff suppressed because it is too large Load Diff
arch/arm/src/xmc4/chip/xmc4_scu.h
+1 -1
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@@ -889,7 +889,7 @@
#define SCU_PBCLKCR_PBDIV (1 << 0) /* Bit 0: PB Clock Divider Enable */
# define SCU_PBCLKCR_PBDIV_FCPU (0) /* 0=fCPU */
# define SCU_PBCLKCR_PBDIV_DIV2 ((1 << 0) /* 1=fCPU/2 */
# define SCU_PBCLKCR_PBDIV_DIV2 (1 << 0) /* 1=fCPU/2 */
/* USB Clock Control */
arch/arm/src/xmc4/chip/xmc4_usic.h
+1 -1
View File
@@ -563,7 +563,7 @@
# define USIC_SCTR_TRM_ACTIVE (3 << USIC_SCTR_TRM_SHIFT) /* Active without regard to signal level */
#define USIC_SCTR_FLE_SHIFT (16) /* Bits 16-21: Frame Length */
#define USIC_SCTR_FLE_MASK (0x3f << USIC_SCTR_FLE_SHIFT)
# define USIC_SCTR_FLE(n) ((uint32_t)(n) << USIC_SCTR_FLE_SHIFT)
# define USIC_SCTR_FLE(n) ((uint32_t)((n)-1) << USIC_SCTR_FLE_SHIFT)
#define USIC_SCTR_WLE_SHIFT (24) /* Bits 24-27: Word Length */
#define USIC_SCTR_WLE_MASK (15 << USIC_SCTR_WLE_SHIFT)
# define USIC_SCTR_WLE(n) ((uint32_t)((n)-1) << USIC_SCTR_WLE_SHIFT)
arch/arm/src/xmc4/xmc4_clockconfig.c
+7 -2
View File
@@ -105,13 +105,18 @@
#define CLKSET_VALUE (0x00000000)
#define SYSCLKCR_VALUE (0x00010001)
#define CPUCLKCR_VALUE (0x00000000)
#define PBCLKCR_VALUE (0x00000000)
#define CCUCLKCR_VALUE (0x00000000)
#define WDTCLKCR_VALUE (0x00000000)
#define EBUCLKCR_VALUE (0x00000003)
#define USBCLKCR_VALUE (0x00010000)
#define EXTCLKCR_VALUE (0x01200003)
#if BOARD_PBDIV == 1
# define PBCLKCR_VALUE SCU_PBCLKCR_PBDIV_FCPU
#else /* BOARD_PBDIV == 2 */
# define PBCLKCR_VALUE SCU_PBCLKCR_PBDIV_DIV2
#endif
#if ((USBCLKCR_VALUE & SCU_USBCLKCR_USBSEL) == SCU_USBCLKCR_USBSEL_USBPLL)
# define USB_DIV 3
#else
@@ -387,7 +392,7 @@ void xmc4_clock_configure(void)
/* Before scaling to final frequency we need to setup the clock dividers */
putreg32(SYSCLKCR_VALUE, XMC4_SCU_SYSCLKCR);
putreg32(PBCLKCR_VALUE, XMC4_SCU_PBCLKCR);
putreg32(PBCLKCR_VALUE, XMC4_SCU_PBCLKCR);
putreg32(CPUCLKCR_VALUE, XMC4_SCU_CPUCLKCR);
putreg32(CCUCLKCR_VALUE, XMC4_SCU_CCUCLKCR);
putreg32(WDTCLKCR_VALUE, XMC4_SCU_WDTCLKCR);
arch/arm/src/xmc4/xmc4_usic.c
+2 -2
View File
@@ -448,14 +448,14 @@ int xmc4_usic_baudrate(enum usic_channel_e channel, uint32_t baud,
/* Select and setup the fractional divider */
regval = USIC_FDR_DM_FRACTIONAL | (clkdiv_min << USIC_FDR_STEP_SHIFT);
regval = USIC_FDR_DM_FRACTIONAL | USIC_FDR_STEP(clkdiv_min);
putreg32(regval, base + XMC4_USIC_FDR_OFFSET);
/* Setup and enable the baud rate generator */
regval = getreg32(base + XMC4_USIC_BRG_OFFSET);
regval &= ~(USIC_BRG_DCTQ_MASK | USIC_BRG_PDIV_MASK | USIC_BRG_PCTQ_MASK | USIC_BRG_PPPEN);
regval |= (USIC_BRG_DCTQ(oversampling - 1) | USIC_BRG_PDIV(pdiv_int_min - 1));
regval |= (USIC_BRG_DCTQ(oversampling - 1) | USIC_BRG_PDIV(pdiv_int_min - 1));
putreg32(regval, base + XMC4_USIC_BRG_OFFSET);
ret = OK;
configs/xmc4500-relax/README.txt
+10
View File
@@ -7,6 +7,13 @@ README for the XMC4500 Relax
The current configurations support only the Lite version of the board.
Status
======
2017-03-21: The XMC4500 Relax boots into NSH, provides the NSH prompt,
and the LEDs are working. But there is a problem with sserial input.
The most likely reason for this is there are no serial RX interripts.
Serial Console
==============
@@ -20,6 +27,9 @@ Serial Console
VDD5 - Available on pins 39-40 of either connector X1 or X2
A TTL to RS-232 convertor or a USB TTL-to-USB serial adaptor is required.
The notion of what is TX and what is RX depends on your point of view.
With the TTL to RS-232 converter, I connect pin 17 to the pin labeled
TX on the converter and pin 16 to the RX pin on the converter.
LEDs
====
configs/xmc4500-relax/include/board.h
+21 -11
View File
@@ -53,16 +53,21 @@
/* Clocking *************************************************************************/
/* Default clock initialization
* fPLL = 288MHz => fSYS = 288MHz => fCPU = 144MHz
* => fPB = 144MHz
* => fCCU = 144MHz
* => fETH = 72MHz
* => fUSB = 48MHz
* => fEBU = 72MHz
*
* fXTAL = 12Mhz
* -> fPLL = (fXTAL / (2 * 1) * 48) = 288MHz
* -> fSYS = (fPLL / 1) = 288MHz
* -> fCPU = (fSYS / 2) = 144MHz
* -> fPERIPH = (fCPU / 1) = 144MHz
* -> fCCU = (fSYS / 2) = 144MHz
* -> fETH = 72MHz (REVISIT)
* -> fUSB = 48MHz (REVISIT)
* -> fEBU = 72MHz (REVISIT)
*
* fUSBPLL Disabled, only enabled if SCU_CLK_USBCLKCR_USBSEL_USBPLL is selected
*
* fOFI = 24MHz => fWDT = 24MHz
* fOFI = 24MHz
* -> fWDT = 24MHz (REVISIT)
*/
#undef BOARD_FOFI_CALIBRATION /* Enable factory calibration */
@@ -79,7 +84,7 @@
/* Select the external crystal as the PLL clock source */
#define BOARD_PLL_CLOCKSRC_XTAL 1 /* PLL Clock source == extnernal crystal */
#undef BOARD_PLL_CLOCKSRC_OFI /* PLL Clock source != internal fast oscillator */
#undef BOARD_PLL_CLOCKSRC_OFI /* PLL Clock source != internal fast oscillator */
/* PLL Configuration:
*
@@ -95,16 +100,21 @@
#define BOARD_PLL_K2DIV 1
#define BOARD_PLL_FREQUENCY 288000000
/* System frequency is divided down from PLL output */
/* System frequency, fSYS, is divided down from PLL output */
#define BOARD_SYSDIV 1 /* PLL Output divider to get fSYS */
#define BOARD_SYS_FREQUENCY 288000000
/* CPU frequency may be divided down from system frequency */
/* CPU frequency, fCPU, may be divided down from system frequency */
#define BOARD_CPUDIV_ENABLE 1 /* Enable PLL dive by 2 for fCPU */
#define BOARD_CPU_FREQUENCY 144000000
/* The peripheral clock, fPERIPH, derives from fCPU with no division */
#define BOARD_PBDIV 1 /* No division */
#define BOARD_PERIPH_FREQUENCY 144000000
/* Standby clock source selection
*
* BOARD_STDBY_CLOCKSRC_OSI - Internal 32.768KHz slow oscillator
@@ -112,7 +122,7 @@
*/
#define BOARD_STDBY_CLOCKSRC_OSI 1
#undef BOARD_STDBY_CLOCKSRC_OSCULP
#undef BOARD_STDBY_CLOCKSRC_OSCULP
#define BOARD_STDBY_FREQUENCY 32768
/* USB PLL settings.
drivers/lcd/st7565.c
+1 -1
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@@ -1041,7 +1041,7 @@ FAR struct lcd_dev_s *st7565_initialize(FAR struct st7565_lcd_s *lcd,
up_mdelay(2);
(void)st7565_send_one_data(priv, ST7565_POWERCTRL_BR);
up_mdelay(2);
(void)st7565_send_one_data(priv, ST7565_POWERCTRL_BRF);
(void)st7565_send_one_data(priv, ST7565_POWERCTRL_INT);
(void)st7565_send_one_data(priv, ST7565_REG_RES_4_5);
(void)st7565_send_one_data(priv, ST7565_SETEVMODE);
drivers/lcd/st7565.h
-2
View File
@@ -102,8 +102,6 @@
*/
#define ST7565_POWERCTRL_B 0x2c /* 0x2c: Booster=ON */
#define ST7565_POWERCTRL_BR 0x2e /* 0x2e: Booster=ON V/R=ON */
#define ST7565_POWERCTRL_BRF 0x2f /* 0x23: Booster=ON V/R=ON V/F=ON */
#define ST7565_POWERCTRL_INT 0x2f /* 0x2f: Only the internal power supply is used */
/* Regulation Resistior ratio V0 = (1+Rb/Ra)*Vev */
sched/Kconfig
+7 -1
View File
@@ -263,11 +263,17 @@ if SMP
config SMP_NCPUS
int "Number of CPUs"
default 4
range 2 32
range 1 32 if DEBUG_FEATURES
range 2 32 if !DEBUG_FEATURES
---help---
This value identifies the number of CPUs supported by the processor
that will be used for SMP.
If CONFIG_DEBUG_FEATURES is enbled, then the value one is permitted
for CONFIG_SMP_NCPUS. This is not normally a valid setting for an
SMP configuration. However, running the SMP logic in a single CPU
configuration is useful during certain testing.
config SMP_IDLETHREAD_STACKSIZE
int "CPU IDLE stack size"
default 2048
sched/pthread/pthread_mutexlock.c
+7 -3
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@@ -136,8 +136,13 @@ int pthread_mutex_lock(FAR pthread_mutex_t *mutex)
else
#endif
{
/* No, then we would deadlock... return an error (default behavior
* is like PTHREAD_MUTEX_ERRORCHECK)
/* No, then we would deadlock... return an error (default
* behavior is like PTHREAD_MUTEX_ERRORCHECK)
*
* NOTE: This is non-compliant behavior for the case of a
* NORMAL mutex. In that case, it the deadlock condition should
* not be detected and the thread should be permitted to
* deadlock.
*/
serr("ERROR: Returning EDEADLK\n");
@@ -169,4 +174,3 @@ int pthread_mutex_lock(FAR pthread_mutex_t *mutex)
sinfo("Returning %d\n", ret);
return ret;
}
sched/pthread/pthread_mutexunlock.c
+13 -2
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@@ -100,13 +100,22 @@ int pthread_mutex_unlock(FAR pthread_mutex_t *mutex)
if (mutex->pid != (int)getpid())
{
/* No... return an error (default behavior is like PTHREAD_MUTEX_ERRORCHECK) */
/* No... return an EPERM error.
*
* Per POSIX: "EPERM should be returned if the mutex type is
* PTHREAD_MUTEX_ERRORCHECK or PTHREAD_MUTEX_RECURSIVE, or the
* mutex is a robust mutex, and the current thread does not own
* the mutex."
*
* For the case of the non-robust PTHREAD_MUTEX_NORMAL mutex,
* the behavior is undefined. Here we treat that type as though
* it were PTHREAD_MUTEX_ERRORCHECK type and just return an error.
*/
serr("ERROR: Holder=%d returning EPERM\n", mutex->pid);
ret = EPERM;
}
/* Yes, the caller owns the semaphore.. Is this a recursive mutex? */
#ifdef CONFIG_MUTEX_TYPES
@@ -116,6 +125,7 @@ int pthread_mutex_unlock(FAR pthread_mutex_t *mutex)
* the mutex lock, just decrement the count of locks held, and return
* success.
*/
mutex->nlocks--;
}
#endif
@@ -134,6 +144,7 @@ int pthread_mutex_unlock(FAR pthread_mutex_t *mutex)
#endif
ret = pthread_givesemaphore((FAR sem_t *)&mutex->sem);
}
sched_unlock();
}
sched/semaphore/sem_holder.c
+7 -8
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@@ -156,7 +156,7 @@ static FAR struct semholder_s *sem_findholder(sem_t *sem,
int i;
pholder = NULL;
/* We have two hard-allocated holder structuse in sem_t */
/* We have two hard-allocated holder structures in sem_t */
for (i = 0; i < 2; i++)
{
@@ -338,7 +338,7 @@ static int sem_boostholderprio(FAR struct semholder_s *pholder,
if (!sched_verifytcb(htcb))
{
serr("ERROR: TCB 0x%08x is a stale handle, counts lost\n", htcb);
DEBUGASSERT(!sched_verifytcb(htcb));
DEBUGPANIC();
sem_freeholder(sem, pholder);
}
@@ -498,7 +498,7 @@ static int sem_restoreholderprio(FAR struct tcb_s *htcb,
if (!sched_verifytcb(htcb))
{
serr("ERROR: TCB 0x%08x is a stale handle, counts lost\n", htcb);
DEBUGASSERT(!sched_verifytcb(htcb));
DEBUGPANIC();
pholder = sem_findholder(sem, htcb);
if (pholder != NULL)
{
@@ -787,7 +787,6 @@ static inline void sem_restorebaseprio_task(FAR struct tcb_s *stcb,
FAR sem_t *sem)
{
FAR struct tcb_s *rtcb = this_task();
FAR struct semholder_s *pholder;
/* Perform the following actions only if a new thread was given a count.
* The thread that received the count should be the highest priority
@@ -831,7 +830,6 @@ static inline void sem_restorebaseprio_task(FAR struct tcb_s *stcb,
*/
sem_findandfreeholder(sem, rtcb);
}
/****************************************************************************
@@ -905,14 +903,15 @@ void sem_destroyholder(FAR sem_t *sem)
if (sem->hhead != NULL)
{
serr("ERROR: Semaphore destroyed with holders\n");
DEBUGASSERT(sem->hhead != NULL);
DEBUGPANIC();
(void)sem_foreachholder(sem, sem_recoverholders, NULL);
}
#else
if (sem->holder[0].htcb != NULL || sem->holder[0].htcb != NULL)
if (sem->holder[0].htcb != NULL || sem->holder[1].htcb != NULL)
{
DEBUGASSERT(sem->holder[0].htcb != NULL || sem->holder[0].htcb != NULL);
serr("ERROR: Semaphore destroyed with holder\n");
DEBUGPANIC();
}
sem->holder[0].htcb = NULL;