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espressif: Update internal libraries reference

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Update internal reference to get the most updated Espressif's
libraries. Those libraries are based on branch `release/v5.1` of
the ESP-IDF and include `v5.1.4` version of it.
This commit is contained in:
Tiago Medicci Serrano
2024-07-23 17:57:14 -03:00
committed by Xiang Xiao
parent c40358ff0d
commit 5680e9d5a4
80 changed files with 1925 additions and 6238 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/risc-v/src/common/espressif/Make.defs
+2 -2
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@@ -130,7 +130,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = 8e8e62cf6a7ae8a9659b91706024cab38af29118
ESP_HAL_3RDPARTY_VERSION = 51afbfd1a17e806fa6fd8227a18395c1bbecbad3
endif
ifndef ESP_HAL_3RDPARTY_URL
@@ -161,7 +161,7 @@ include common$(DELIM)espressif$(DELIM)Bootloader.mk
# Silent preprocessor warnings
CFLAGS += -Wno-undef -Wno-unused-variable
CFLAGS += -Wno-undef -Wno-unused-variable -fno-jump-tables -fno-tree-switch-conversion
# Remove quotes from CONFIG_ESPRESSIF_CHIP_SERIES configuration
arch/risc-v/src/common/espressif/Wireless.mk
+4 -2
View File
@@ -68,6 +68,7 @@ CHIP_CSRCS += pkcs5.c
CHIP_CSRCS += platform_util.c
CHIP_CSRCS += platform.c
CHIP_CSRCS += sha1.c
CHIP_CSRCS += sha3.c
CHIP_CSRCS += sha256.c
CHIP_CSRCS += sha512.c
CHIP_CSRCS += pk.c
@@ -81,9 +82,9 @@ CHIP_CSRCS += md5.c
CHIP_CSRCS += oid.c
CHIP_CSRCS += pem.c
CHIP_CSRCS += hmac_drbg.c
CHIP_CSRCS += hash_info.c
CHIP_CSRCS += rsa_alt_helpers.c
CHIP_CSRCS += ecdh.c
CHIP_CSRCS += pk_ecc.c
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port
@@ -112,6 +113,7 @@ CFLAGS += $(DEFINE_PREFIX)IEEE8021X_EAPOL
CFLAGS += $(DEFINE_PREFIX)USE_WPA2_TASK
CFLAGS += $(DEFINE_PREFIX)CONFIG_SHA256
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE
CFLAGS += $(DEFINE_PREFIX)USE_WPS_TASK
ifeq ($(CONFIG_ESPRESSIF_WIFI_ENABLE_SAE_PK),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE_PK
@@ -222,11 +224,11 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)
CHIP_CSRCS += esp_common.c
CHIP_CSRCS += esp_hostap.c
CHIP_CSRCS += esp_wpa_main.c
CHIP_CSRCS += esp_wpa2.c
CHIP_CSRCS += esp_wpa3.c
CHIP_CSRCS += esp_wpas_glue.c
CHIP_CSRCS += esp_owe.c
CHIP_CSRCS += esp_scan.c
CHIP_CSRCS += esp_wps.c
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src$(DELIM)crypto
arch/risc-v/src/common/espressif/esp_hr_timer.c
+41
View File
@@ -424,6 +424,47 @@ void IRAM_ATTR esp_hr_timer_start(struct esp_hr_timer_s *timer,
spin_unlock_irqrestore(&priv->lock, flags);
}
/****************************************************************************
* Name: esp_hr_timer_start_once
*
* Description:
* Start the High Resolution Timer with one shot mode.
*
* Input Parameters:
* timer - HR Timer pointer.
* timeout - Timeout value.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_hr_timer_start_once(struct esp_hr_timer_s *timer, uint64_t timeout)
{
esp_hr_timer_start(timer, timeout, false);
}
/****************************************************************************
* Name: esp_hr_timer_start_periodic
*
* Description:
* Start the High Resolution Timer with periodic mode.
*
* Input Parameters:
* timer - HR Timer pointer.
* timeout - Timeout value.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_hr_timer_start_periodic(struct esp_hr_timer_s *timer,
uint64_t timeout)
{
esp_hr_timer_start(timer, timeout, true);
}
/****************************************************************************
* Name: esp_hr_timer_stop
*
arch/risc-v/src/common/espressif/esp_hr_timer.h
+37
View File
@@ -71,6 +71,8 @@ struct esp_hr_timer_args_s
{
void (*callback)(void *arg); /* Callback function */
void *arg; /* Private data */
const char *name; /* Timer name, used in esp_timer_dump function */
bool skip_unhandled_events; /* Skip unhandled events for periodic timers */
};
#undef EXTERN
@@ -127,6 +129,41 @@ void esp_hr_timer_start(struct esp_hr_timer_s *timer,
uint64_t timeout,
bool repeat);
/****************************************************************************
* Name: esp_hr_timer_start_once
*
* Description:
* Start the High Resolution Timer with one shot mode.
*
* Input Parameters:
* timer - HR Timer pointer.
* timeout - Timeout value.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_hr_timer_start_once(struct esp_hr_timer_s *timer, uint64_t timeout);
/****************************************************************************
* Name: esp_hr_timer_start_periodic
*
* Description:
* Start the High Resolution Timer with periodic mode.
*
* Input Parameters:
* timer - HR Timer pointer.
* timeout - Timeout value.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_hr_timer_start_periodic(struct esp_hr_timer_s *timer,
uint64_t timeout);
/****************************************************************************
* Name: esp_hr_timer_stop
*
arch/risc-v/src/common/espressif/esp_start.c
+5
View File
@@ -38,6 +38,7 @@
#include "esp_start.h"
#include "esp_clk_internal.h"
#include "esp_private/rtc_clk.h"
#include "esp_cpu.h"
#include "esp_private/brownout.h"
#include "hal/wdt_hal.h"
@@ -436,6 +437,10 @@ void __esp_start(void)
CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
#endif /* CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE */
#if CONFIG_ESP_SYSTEM_BBPLL_RECALIB
rtc_clk_recalib_bbpll();
#endif
#ifdef CONFIG_ESPRESSIF_REGION_PROTECTION
/* Configure region protection */
arch/risc-v/src/common/espressif/esp_wifi_init.c
+1 -1
View File
@@ -35,7 +35,7 @@
#include "esp_sleep.h"
#include "esp_private/esp_clk.h"
#include "esp_wpa.h"
#include "esp_coexist_internal.h"
#include "private/esp_coexist_internal.h"
#include "esp_phy_init.h"
#include "esp_private/phy.h"
arch/risc-v/src/esp32c3-legacy/Make.defs
+1 -1
View File
@@ -237,7 +237,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = 45c33111b441363e1267158186a60f42525228ca
ESP_HAL_3RDPARTY_VERSION = 51afbfd1a17e806fa6fd8227a18395c1bbecbad3
endif
ifndef ESP_HAL_3RDPARTY_URL
arch/risc-v/src/esp32c3/esp_coex_adapter.c
+2 -2
View File
@@ -41,11 +41,11 @@
#include "esp_timer.h"
#include "soc/rtc.h"
#include "esp_private/esp_clk.h"
#include "esp_coexist_adapter.h"
#include "private/esp_coexist_adapter.h"
#include "rom/ets_sys.h"
#include "soc/soc_caps.h"
#include "soc/system_reg.h"
#include "esp_modem_wrapper.h"
#include "private/esp_modem_wrapper.h"
/****************************************************************************
* Pre-processor Definitions
arch/risc-v/src/esp32c3/esp_wifi_adapter.c
+106 -4
View File
@@ -74,9 +74,9 @@
#include "esp_private/esp_clk.h"
#include "os.h"
#include "esp_smartconfig.h"
#include "esp_coexist_internal.h"
#include "private/esp_coexist_internal.h"
#include "rom/ets_sys.h"
#include "esp_modem_wrapper.h"
#include "private/esp_modem_wrapper.h"
#include "esp_wlan.h"
#include "esp_wifi_adapter.h"
@@ -282,6 +282,8 @@ int32_t esp_event_post_wrapper(const char *event_base,
uint32_t ticks);
static void wifi_apb80m_request_wrapper(void);
static void wifi_apb80m_release_wrapper(void);
static void esp_phy_enable_wrapper(void);
static void esp_phy_disable_wrapper(void);
static void timer_arm_wrapper(void *timer, uint32_t tmout, bool repeat);
static void wifi_reset_mac_wrapper(void);
static void wifi_rtc_enable_iso_wrapper(void);
@@ -327,6 +329,8 @@ static void *coex_schm_curr_phase_get_wrapper(void);
static int coex_register_start_cb_wrapper(int (* cb)(void));
static int coex_schm_process_restart_wrapper(void);
static int coex_schm_register_cb_wrapper(int type, int(*cb)(int));
static int coex_schm_flexible_period_set_wrapper(uint8_t period);
static uint8_t coex_schm_flexible_period_get_wrapper(void);
static void esp_empty_wrapper(void);
/* Second block of functions
@@ -501,8 +505,8 @@ wifi_osi_funcs_t g_wifi_osi_funcs =
esp_empty_wrapper,
._wifi_apb80m_request = wifi_apb80m_request_wrapper,
._wifi_apb80m_release = wifi_apb80m_release_wrapper,
._phy_disable = esp_phy_disable,
._phy_enable = esp_phy_enable,
._phy_disable = esp_phy_disable_wrapper,
._phy_enable = esp_phy_enable_wrapper,
._phy_update_country_info = esp_phy_update_country_info,
._read_mac = esp_read_mac_wrapper,
._timer_arm = timer_arm_wrapper,
@@ -564,6 +568,8 @@ wifi_osi_funcs_t g_wifi_osi_funcs =
._coex_register_start_cb = coex_register_start_cb_wrapper,
._coex_schm_process_restart = coex_schm_process_restart_wrapper,
._coex_schm_register_cb = coex_schm_register_cb_wrapper,
._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
};
@@ -1561,6 +1567,48 @@ static void IRAM_ATTR wifi_apb80m_release_wrapper(void)
#endif
}
/****************************************************************************
* Name: esp_phy_enable_wrapper
*
* Description:
* This function enables the WiFi PHY. It first enables the PHY for the
* WiFi modem, then sets the WiFi PHY enable flag to 1.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void esp_phy_enable_wrapper(void)
{
esp_phy_enable(PHY_MODEM_WIFI);
phy_wifi_enable_set(1);
}
/****************************************************************************
* Name: esp_phy_disable_wrapper
*
* Description:
* This function disables the WiFi PHY. It first sets the WiFi PHY enable
* flag to 0, then disables the PHY for the WiFi modem.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void esp_phy_disable_wrapper(void)
{
phy_wifi_enable_set(0);
esp_phy_disable(PHY_MODEM_WIFI);
}
/****************************************************************************
* Name: timer_arm_wrapper
*
@@ -2345,6 +2393,60 @@ static int coex_schm_register_cb_wrapper(int type, int(*cb)(int))
#endif
}
/****************************************************************************
* Name: coex_schm_flexible_period_set_wrapper
*
* Description:
* This function sets the coexistence scheme flexible period. If the
* coexistence power management feature is enabled
* (CONFIG_ESP_COEX_POWER_MANAGEMENT), it calls the function
* coex_schm_flexible_period_set with the given period and returns its
* result. If the feature is not enabled, it returns 0.
*
* Input Parameters:
* period - The flexible period to set.
*
* Returned Value:
* ESP_OK on success, or the result of coex_schm_flexible_period_set.
*
****************************************************************************/
static int coex_schm_flexible_period_set_wrapper(uint8_t period)
{
#if CONFIG_ESP_COEX_POWER_MANAGEMENT
return coex_schm_flexible_period_set(period);
#else
return 0;
#endif
}
/****************************************************************************
* Name: coex_schm_flexible_period_get_wrapper
*
* Description:
* This function gets the coexistence scheme flexible period. If the
* coexistence power management feature is enabled
* (CONFIG_ESP_COEX_POWER_MANAGEMENT), it calls the function
* coex_schm_flexible_period_get and returns its result. If the feature is
* not enabled, it returns 1.
*
* Input Parameters:
* None
*
* Returned Value:
* The coexistence scheme flexible period.
*
****************************************************************************/
static uint8_t coex_schm_flexible_period_get_wrapper(void)
{
#if CONFIG_ESP_COEX_POWER_MANAGEMENT
return coex_schm_flexible_period_get();
#else
return 1;
#endif
}
/****************************************************************************
* Name: esp_empty_wrapper
*
arch/risc-v/src/esp32c3/hal_esp32c3.mk
+5 -4
View File
@@ -69,9 +69,10 @@ endif
# Linker scripts
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.eco3.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.api.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.eco3.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.libgcc.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.version.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).peripherals.ld
@@ -106,6 +107,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sar_periph_ctrl.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)systimer.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)lib_printf.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_systimer.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_err.c
@@ -114,6 +116,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_hal_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gdma_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c
@@ -121,8 +124,6 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)systimer_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mpu_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c
arch/risc-v/src/esp32c6/esp_coex_adapter.c
+2 -2
View File
@@ -41,10 +41,10 @@
#include "esp_timer.h"
#include "soc/rtc.h"
#include "esp_private/esp_clk.h"
#include "esp_coexist_adapter.h"
#include "private/esp_coexist_adapter.h"
#include "rom/ets_sys.h"
#include "soc/soc_caps.h"
#include "esp_modem_wrapper.h"
#include "private/esp_modem_wrapper.h"
/****************************************************************************
* Pre-processor Definitions
arch/risc-v/src/esp32c6/esp_wifi_adapter.c
+106 -4
View File
@@ -73,9 +73,9 @@
#include "esp_private/esp_clk.h"
#include "os.h"
#include "esp_smartconfig.h"
#include "esp_coexist_internal.h"
#include "private/esp_coexist_internal.h"
#include "rom/ets_sys.h"
#include "esp_modem_wrapper.h"
#include "private/esp_modem_wrapper.h"
#if SOC_PM_MODEM_RETENTION_BY_REGDMA
#include "esp_private/esp_regdma.h"
@@ -284,6 +284,8 @@ int32_t esp_event_post_wrapper(const char *event_base,
uint32_t ticks);
static void wifi_apb80m_request_wrapper(void);
static void wifi_apb80m_release_wrapper(void);
static void esp_phy_enable_wrapper(void);
static void esp_phy_disable_wrapper(void);
static void timer_arm_wrapper(void *timer, uint32_t tmout, bool repeat);
static void wifi_reset_mac_wrapper(void);
static void wifi_clock_enable_wrapper(void);
@@ -327,6 +329,8 @@ static void *coex_schm_curr_phase_get_wrapper(void);
static int coex_register_start_cb_wrapper(int (* cb)(void));
static int coex_schm_process_restart_wrapper(void);
static int coex_schm_register_cb_wrapper(int type, int(*cb)(int));
static int coex_schm_flexible_period_set_wrapper(uint8_t period);
static uint8_t coex_schm_flexible_period_get_wrapper(void);
static void esp_empty_wrapper(void);
/* Second block of functions
@@ -501,8 +505,8 @@ wifi_osi_funcs_t g_wifi_osi_funcs =
esp_empty_wrapper,
._wifi_apb80m_request = wifi_apb80m_request_wrapper,
._wifi_apb80m_release = wifi_apb80m_release_wrapper,
._phy_disable = esp_phy_disable,
._phy_enable = esp_phy_enable,
._phy_disable = esp_phy_disable_wrapper,
._phy_enable = esp_phy_enable_wrapper,
._phy_update_country_info = esp_phy_update_country_info,
._read_mac = esp_read_mac_wrapper,
._timer_arm = timer_arm_wrapper,
@@ -564,6 +568,8 @@ wifi_osi_funcs_t g_wifi_osi_funcs =
._coex_register_start_cb = coex_register_start_cb_wrapper,
._coex_schm_process_restart = coex_schm_process_restart_wrapper,
._coex_schm_register_cb = coex_schm_register_cb_wrapper,
._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
};
@@ -1561,6 +1567,48 @@ static void IRAM_ATTR wifi_apb80m_release_wrapper(void)
#endif
}
/****************************************************************************
* Name: esp_phy_enable_wrapper
*
* Description:
* This function enables the WiFi PHY. It first enables the PHY for the
* WiFi modem, then sets the WiFi PHY enable flag to 1.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void esp_phy_enable_wrapper(void)
{
esp_phy_enable(PHY_MODEM_WIFI);
phy_wifi_enable_set(1);
}
/****************************************************************************
* Name: esp_phy_disable_wrapper
*
* Description:
* This function disables the WiFi PHY. It first sets the WiFi PHY enable
* flag to 0, then disables the PHY for the WiFi modem.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void esp_phy_disable_wrapper(void)
{
phy_wifi_enable_set(0);
esp_phy_disable(PHY_MODEM_WIFI);
}
/****************************************************************************
* Name: timer_arm_wrapper
*
@@ -2299,6 +2347,60 @@ static int coex_schm_register_cb_wrapper(int type, int(*cb)(int))
#endif
}
/****************************************************************************
* Name: coex_schm_flexible_period_set_wrapper
*
* Description:
* This function sets the coexistence scheme flexible period. If the
* coexistence power management feature is enabled
* (CONFIG_ESP_COEX_POWER_MANAGEMENT), it calls the function
* coex_schm_flexible_period_set with the given period and returns its
* result. If the feature is not enabled, it returns 0.
*
* Input Parameters:
* period - The flexible period to set.
*
* Returned Value:
* ESP_OK on success, or the result of coex_schm_flexible_period_set.
*
****************************************************************************/
static int coex_schm_flexible_period_set_wrapper(uint8_t period)
{
#if CONFIG_ESP_COEX_POWER_MANAGEMENT
return coex_schm_flexible_period_set(period);
#else
return 0;
#endif
}
/****************************************************************************
* Name: coex_schm_flexible_period_get_wrapper
*
* Description:
* This function gets the coexistence scheme flexible period. If the
* coexistence power management feature is enabled
* (CONFIG_ESP_COEX_POWER_MANAGEMENT), it calls the function
* coex_schm_flexible_period_get and returns its result. If the feature is
* not enabled, it returns 1.
*
* Input Parameters:
* None
*
* Returned Value:
* The coexistence scheme flexible period.
*
****************************************************************************/
static uint8_t coex_schm_flexible_period_get_wrapper(void)
{
#if CONFIG_ESP_COEX_POWER_MANAGEMENT
return coex_schm_flexible_period_get();
#else
return 1;
#endif
}
/****************************************************************************
* Name: esp_empty_wrapper
*
arch/risc-v/src/esp32c6/hal_esp32c6.mk
+5 -3
View File
@@ -61,17 +61,19 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)private_include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include
endif
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include
# Linker scripts
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.api.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.coexist.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.libgcc.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.net80211.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.phy.ld
@@ -112,8 +114,9 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sar_periph_ctrl.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)systimer.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)lib_printf.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_regi2c_$(CHIP_SERIES).c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_hp_regi2c_$(CHIP_SERIES).c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_systimer.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)brownout.c
@@ -131,7 +134,6 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)twai_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)twai_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c
arch/risc-v/src/esp32h2/hal_esp32h2.mk
+3 -2
View File
@@ -36,6 +36,7 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)ld
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include$(DELIM)private
@@ -65,8 +66,9 @@ endif
# Linker scripts
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.api.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.libgcc.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.spiflash.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.version.ld
@@ -117,7 +119,6 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mpu_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mcpwm_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c
arch/xtensa/src/esp32/Make.defs
+1 -1
View File
@@ -208,7 +208,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = 8e8e62cf6a7ae8a9659b91706024cab38af29118
ESP_HAL_3RDPARTY_VERSION = 51afbfd1a17e806fa6fd8227a18395c1bbecbad3
endif
ifndef ESP_HAL_3RDPARTY_URL
arch/xtensa/src/esp32/Wireless.mk
+4 -2
View File
@@ -79,6 +79,7 @@ CHIP_CSRCS += pkcs5.c
CHIP_CSRCS += platform_util.c
CHIP_CSRCS += platform.c
CHIP_CSRCS += sha1.c
CHIP_CSRCS += sha3.c
CHIP_CSRCS += sha256.c
CHIP_CSRCS += sha512.c
CHIP_CSRCS += pk.c
@@ -92,9 +93,9 @@ CHIP_CSRCS += md5.c
CHIP_CSRCS += oid.c
CHIP_CSRCS += pem.c
CHIP_CSRCS += hmac_drbg.c
CHIP_CSRCS += hash_info.c
CHIP_CSRCS += rsa_alt_helpers.c
CHIP_CSRCS += ecdh.c
CHIP_CSRCS += pk_ecc.c
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port
@@ -123,6 +124,7 @@ CFLAGS += $(DEFINE_PREFIX)IEEE8021X_EAPOL
CFLAGS += $(DEFINE_PREFIX)USE_WPA2_TASK
CFLAGS += $(DEFINE_PREFIX)CONFIG_SHA256
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE
CFLAGS += $(DEFINE_PREFIX)USE_WPS_TASK
ifeq ($(CONFIG_ESP_WIFI_ENABLE_SAE_PK),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE_PK
@@ -233,11 +235,11 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)
CHIP_CSRCS += esp_common.c
CHIP_CSRCS += esp_hostap.c
CHIP_CSRCS += esp_wpa_main.c
CHIP_CSRCS += esp_wpa2.c
CHIP_CSRCS += esp_wpa3.c
CHIP_CSRCS += esp_wpas_glue.c
CHIP_CSRCS += esp_owe.c
CHIP_CSRCS += esp_scan.c
CHIP_CSRCS += esp_wps.c
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src$(DELIM)crypto
arch/xtensa/src/esp32/esp32_ble_adapter.c
+68 -45
View File
@@ -71,7 +71,8 @@
#include "soc/soc_caps.h"
#include "xtensa/core-macros.h"
#include "xtensa/xtensa_api.h"
#include "esp_coexist_internal.h"
#include "private/esp_coexist_internal.h"
#include "private/esp_coexist_adapter.h"
#include "esp32_ble_adapter.h"
@@ -107,7 +108,7 @@
#define BTDM_MODEM_WAKE_UP_DELAY (4) /* delay in slots of modem wake up procedure, including re-enable PHY/RF */
#define OSI_FUNCS_TIME_BLOCKING 0xffffffff
#define OSI_VERSION 0x00010004
#define OSI_VERSION 0x00010005
#define OSI_MAGIC_VALUE 0xfadebead
#ifdef CONFIG_PM
@@ -228,6 +229,7 @@ struct osi_funcs_s
int (* _coex_version_get)(unsigned int *major,
unsigned int *minor,
unsigned int *patch);
void (* _patch_apply)(void);
uint32_t _magic;
};
@@ -381,6 +383,7 @@ static int coex_register_wifi_channel_change_callback_wrapper(void *cb);
static int coex_version_get_wrapper(unsigned int *major,
unsigned int *minor,
unsigned int *patch);
static void patch_apply(void);
/****************************************************************************
* Other functions
@@ -468,6 +471,8 @@ extern void btdm_controller_scan_duplicate_list_clear(void);
/* Shutdown */
extern void esp_bt_controller_shutdown(void);
extern void sdk_config_set_bt_pll_track_enable(bool enable);
extern void sdk_config_set_uart_flow_ctrl_enable(bool enable);
extern uint8_t _bss_start_btdm[];
extern uint8_t _bss_end_btdm[];
@@ -478,16 +483,16 @@ extern uint32_t _data_end_btdm_rom;
extern uint32_t _bt_bss_start;
extern uint32_t _bt_bss_end;
extern uint32_t _nimble_bss_start;
extern uint32_t _nimble_bss_end;
extern uint32_t _btdm_bss_start;
extern uint32_t _btdm_bss_end;
extern uint32_t _bt_controller_bss_start;
extern uint32_t _bt_controller_bss_end;
extern uint32_t _bt_data_start;
extern uint32_t _bt_data_end;
extern uint32_t _nimble_data_start;
extern uint32_t _nimble_data_end;
extern uint32_t _btdm_data_start;
extern uint32_t _btdm_data_end;
extern uint32_t _bt_controller_data_start;
extern uint32_t _bt_controller_data_end;
extern void config_bt_funcs_reset(void);
extern void config_ble_funcs_reset(void);
extern void config_btdm_funcs_reset(void);
/****************************************************************************
* Private Data
@@ -560,6 +565,7 @@ static struct osi_funcs_s g_osi_funcs_ro =
._interrupt_l3_restore = interrupt_restore,
._customer_queue_create = NULL,
._coex_version_get = coex_version_get_wrapper,
._patch_apply = patch_apply,
._magic = OSI_MAGIC_VALUE,
};
@@ -1834,7 +1840,7 @@ static void btdm_sleep_enter_phase2_wrapper(void)
{
if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_ORIG)
{
esp_phy_disable();
esp_phy_disable(PHY_MODEM_BT);
#ifdef CONFIG_PM
if (g_pm_lock_acquired)
{
@@ -1845,7 +1851,7 @@ static void btdm_sleep_enter_phase2_wrapper(void)
}
else if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_EVED)
{
esp_phy_disable();
esp_phy_disable(PHY_MODEM_BT);
/* pause bluetooth baseband */
@@ -1879,7 +1885,7 @@ void btdm_sleep_exit_phase3_wrapper(void)
if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_ORIG)
{
esp_phy_enable();
esp_phy_enable(PHY_MODEM_BT);
btdm_check_and_init_bb();
#ifdef CONFIG_PM
esp_timer_stop(g_btdm_slp_tmr);
@@ -1890,7 +1896,7 @@ void btdm_sleep_exit_phase3_wrapper(void)
/* resume bluetooth baseband */
periph_module_enable(PERIPH_BT_BASEBAND_MODULE);
esp_phy_enable();
esp_phy_enable(PHY_MODEM_BT);
}
}
@@ -2260,41 +2266,50 @@ static int coex_version_get_wrapper(unsigned int *major,
unsigned int *patch)
{
#ifdef CONFIG_ESP32_WIFI_BT_COEXIST
const char *ver_str = coex_version_get();
coex_version_t version;
if (ver_str != NULL)
{
unsigned int _major = 0;
unsigned int _minor = 0;
unsigned int _patch = 0;
ASSERT(coex_version_get_value(&version) == ESP_OK);
if (sscanf(ver_str, "%u.%u.%u", &_major, &_minor, &_patch) != 3)
{
return -1;
}
*major = (unsigned int)version.major;
*minor = (unsigned int)version.minor;
*patch = (unsigned int)version.patch;
if (major != NULL)
{
*major = _major;
}
if (minor != NULL)
{
*minor = _minor;
}
if (patch != NULL)
{
*patch = _patch;
}
return 0;
}
return 0;
#endif
return -1;
}
/****************************************************************************
* Name: patch_apply
*
* Description:
* This function resets the BTDM and BT functions based on the current
* configuration. If the configuration is not set to BLE only, it resets
* the BT functions. If the configuration is not set to BR/EDR only, it
* resets the BLE functions.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void patch_apply(void)
{
config_btdm_funcs_reset();
#ifndef CONFIG_BTDM_CTRL_MODE_BLE_ONLY
config_bt_funcs_reset();
#endif
#ifndef CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY
config_ble_funcs_reset();
#endif
}
/****************************************************************************
* Other functions
****************************************************************************/
@@ -3046,6 +3061,12 @@ int esp32_bt_controller_init(void)
UNUSED(set_div_ret);
#endif
#if CONFIG_BTDM_CTRL_HCI_UART_FLOW_CTRL_EN
sdk_config_set_uart_flow_ctrl_enable(true);
#else
sdk_config_set_uart_flow_ctrl_enable(false);
#endif
#ifdef CONFIG_PM
if ((err = esp_timer_create(&create_args, &g_btdm_slp_tmr) != OK))
{
@@ -3154,7 +3175,7 @@ int esp32_bt_controller_enable(esp_bt_mode_t mode)
esp32_pm_lockacquire();
#endif
esp_phy_enable();
esp_phy_enable(PHY_MODEM_BT);
#ifdef CONFIG_ESP32_WIFI_BT_COEXIST
coex_enable();
@@ -3165,6 +3186,8 @@ int esp32_bt_controller_enable(esp_bt_mode_t mode)
btdm_controller_enable_sleep(true);
}
sdk_config_set_bt_pll_track_enable(true);
/* inititalize bluetooth baseband */
btdm_check_and_init_bb();
@@ -3175,7 +3198,7 @@ int esp32_bt_controller_enable(esp_bt_mode_t mode)
#ifdef CONFIG_ESP32_WIFI_BT_COEXIST
coex_disable();
#endif
esp_phy_disable();
esp_phy_disable(PHY_MODEM_BT);
#ifdef CONFIG_PM
if (g_btdm_allow_light_sleep == false)
{
@@ -3189,7 +3212,7 @@ int esp32_bt_controller_enable(esp_bt_mode_t mode)
g_btdm_controller_status = ESP_BT_CONTROLLER_STATUS_ENABLED;
return OK;
return esp_wifi_to_errno(ret);
}
/****************************************************************************
@@ -3232,7 +3255,7 @@ int esp32_bt_controller_disable(void)
coex_disable();
#endif
esp_phy_disable();
esp_phy_disable(PHY_MODEM_BT);
g_btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
#ifdef CONFIG_PM
arch/xtensa/src/esp32/esp32_wifi_adapter.c
+108 -3
View File
@@ -71,7 +71,7 @@
#ifdef CONFIG_ESP32_BLE
# include "esp32_ble_adapter.h"
# ifdef CONFIG_ESP32_WIFI_BT_COEXIST
# include "esp_coexist_internal.h"
# include "private/esp_coexist_internal.h"
# endif
#endif
@@ -266,6 +266,8 @@ static void esp_dport_access_stall_other_cpu_start(void);
static void esp_dport_access_stall_other_cpu_end(void);
static void wifi_apb80m_request(void);
static void wifi_apb80m_release(void);
static void esp_phy_enable_wrapper(void);
static void esp_phy_disable_wrapper(void);
static int32_t esp_wifi_read_mac(uint8_t *mac, uint32_t type);
static void esp_timer_arm(void *timer, uint32_t tmout, bool repeat);
static void esp_timer_disarm(void *timer);
@@ -340,6 +342,8 @@ static void *coex_schm_curr_phase_get_wrapper(void);
static int coex_register_start_cb_wrapper(int (* cb)(void));
static int coex_schm_process_restart_wrapper(void);
static int coex_schm_register_cb_wrapper(int type, int(*cb)(int));
static int coex_schm_flexible_period_set_wrapper(uint8_t period);
static uint8_t coex_schm_flexible_period_get_wrapper(void);
/****************************************************************************
* Private Data
@@ -491,8 +495,8 @@ wifi_osi_funcs_t g_wifi_osi_funcs =
esp_dport_access_stall_other_cpu_end,
._wifi_apb80m_request = wifi_apb80m_request,
._wifi_apb80m_release = wifi_apb80m_release,
._phy_disable = esp_phy_disable,
._phy_enable = esp_phy_enable,
._phy_disable = esp_phy_disable_wrapper,
._phy_enable = esp_phy_enable_wrapper,
._phy_common_clock_enable = esp_phy_common_clock_enable,
._phy_common_clock_disable = esp_phy_common_clock_disable,
._phy_update_country_info = esp32_phy_update_country_info,
@@ -555,6 +559,8 @@ wifi_osi_funcs_t g_wifi_osi_funcs =
._coex_register_start_cb = coex_register_start_cb_wrapper,
._coex_schm_process_restart = coex_schm_process_restart_wrapper,
._coex_schm_register_cb = coex_schm_register_cb_wrapper,
._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
};
@@ -2531,6 +2537,50 @@ static void wifi_apb80m_release(void)
#endif
}
/****************************************************************************
* Name: esp_phy_enable_wrapper
*
* Description:
* This is a wrapper for enabling the ESP PHY. It calls the esp_phy_enable
* function with PHY_MODEM_WIFI as the argument, and then calls the
* phy_wifi_enable_set function with 1 as the argument.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void esp_phy_enable_wrapper(void)
{
esp_phy_enable(PHY_MODEM_WIFI);
phy_wifi_enable_set(1);
}
/****************************************************************************
* Name: esp_phy_disable_wrapper
*
* Description:
* This is a wrapper for disabling the ESP PHY. It first calls the
* phy_wifi_enable_set function with 0 as the argument, and then calls the
* esp_phy_disable function with PHY_MODEM_WIFI as the argument.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void esp_phy_disable_wrapper(void)
{
phy_wifi_enable_set(0);
esp_phy_disable(PHY_MODEM_WIFI);
}
/****************************************************************************
* Name: esp_wifi_read_mac
*
@@ -3997,6 +4047,61 @@ static int coex_schm_register_cb_wrapper(int type, int(*cb)(int))
#endif
}
/****************************************************************************
* Name: coex_schm_flexible_period_set_wrapper
*
* Description:
* This is a wrapper for coex_schm_flexible_period_set. It sets the
* flexible period for the coexistence mechanism. If power management
* feature is enabled (CONFIG_ESP_COEX_POWER_MANAGEMENT), it calls the
* function with the given period. If the feature is not enabled, it
* returns 0.
*
* Input Parameters:
* period - The period to set for the coexistence mechanism.
*
* Returned Value:
* If power management is enabled, it returns the result of the
* coex_schm_flexible_period_set function. Otherwise, it returns 0.
*
****************************************************************************/
static int coex_schm_flexible_period_set_wrapper(uint8_t period)
{
#if CONFIG_ESP_COEX_POWER_MANAGEMENT
return coex_schm_flexible_period_set(period);
#else
return 0;
#endif
}
/****************************************************************************
* Name: coex_schm_flexible_period_get_wrapper
*
* Description:
* This is a wrapper for coex_schm_flexible_period_get. If power management
* feature is enabled (CONFIG_ESP_COEX_POWER_MANAGEMENT), it calls the
* function and returns its result. If the feature is not enabled, it
* returns 1.
*
* Input Parameters:
* None
*
* Returned Value:
* If power management is enabled, it returns the result of the
* coex_schm_flexible_period_get function. Otherwise, it returns 1.
*
****************************************************************************/
static uint8_t coex_schm_flexible_period_get_wrapper(void)
{
#if CONFIG_ESP_COEX_POWER_MANAGEMENT
return coex_schm_flexible_period_get();
#else
return 1;
#endif
}
/****************************************************************************
* Name: esp_random_ulong
*
arch/xtensa/src/esp32/esp32_wireless.c
+80 -1
View File
@@ -43,7 +43,7 @@
# include "esp_private/wifi.h"
# include "esp_wpa.h"
#endif
#include "esp_coexist_internal.h"
#include "private/esp_coexist_internal.h"
#include "periph_ctrl.h"
#include "esp_phy_init.h"
#include "phy_init_data.h"
@@ -351,6 +351,85 @@ static void esp_wifi_set_log_level(void)
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp_wifi_to_errno
*
* Description:
* Transform from ESP Wi-Fi error code to NuttX error code
*
* Input Parameters:
* err - ESP Wi-Fi error code
*
* Returned Value:
* NuttX error code defined in errno.h
*
****************************************************************************/
int32_t esp_wifi_to_errno(int err)
{
int ret;
if (err < ESP_ERR_WIFI_BASE)
{
/* Unmask component error bits */
ret = err & 0xfff;
switch (ret)
{
case ESP_OK:
ret = OK;
break;
case ESP_ERR_NO_MEM:
ret = -ENOMEM;
break;
case ESP_ERR_INVALID_ARG:
ret = -EINVAL;
break;
case ESP_ERR_INVALID_STATE:
ret = -EIO;
break;
case ESP_ERR_INVALID_SIZE:
ret = -EINVAL;
break;
case ESP_ERR_NOT_FOUND:
ret = -ENOSYS;
break;
case ESP_ERR_NOT_SUPPORTED:
ret = -ENOSYS;
break;
case ESP_ERR_TIMEOUT:
ret = -ETIMEDOUT;
break;
case ESP_ERR_INVALID_MAC:
ret = -EINVAL;
break;
default:
ret = ERROR;
break;
}
}
else
{
ret = ERROR;
}
if (ret != OK)
{
wlerr("ERROR: %s\n", esp_err_to_name(err));
}
return ret;
}
/****************************************************************************
* Functions needed by libphy.a
****************************************************************************/
arch/xtensa/src/esp32/esp32_wireless.h
+39
View File
@@ -85,10 +85,49 @@ struct esp_queuecache_s
uint8_t *buffer;
};
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: nuttx_err_to_freertos
*
* Description:
* Transform from Nuttx OS error code to FreeRTOS's pdTRUE or pdFALSE.
*
* Input Parameters:
* ret - NuttX error code
*
* Returned Value:
* Wi-Fi adapter error code
*
****************************************************************************/
static inline int32_t nuttx_err_to_freertos(int ret)
{
return ret >= 0;
}
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp_wifi_to_errno
*
* Description:
* Transform from ESP Wi-Fi error code to NuttX error code
*
* Input Parameters:
* err - ESP Wi-Fi error code
*
* Returned Value:
* NuttX error code defined in errno.h
*
****************************************************************************/
int32_t esp_wifi_to_errno(int err);
/****************************************************************************
* Functions needed by libphy.a
****************************************************************************/
arch/xtensa/src/esp32/hal.mk
+5 -1
View File
@@ -65,6 +65,10 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.api.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.libgcc.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib-data.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib-funcs.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.syscalls.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).peripherals.ld
# Source files
@@ -90,6 +94,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c
@@ -103,7 +108,6 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mcpwm_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c
arch/xtensa/src/esp32s2/Make.defs
+1 -1
View File
@@ -151,7 +151,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = 8e8e62cf6a7ae8a9659b91706024cab38af29118
ESP_HAL_3RDPARTY_VERSION = 51afbfd1a17e806fa6fd8227a18395c1bbecbad3
endif
ifndef ESP_HAL_3RDPARTY_URL
arch/xtensa/src/esp32s2/esp32s2_spi.c
+24 -17
View File
@@ -1193,8 +1193,12 @@ static void esp32s2_spi_poll_exchange(struct esp32s2_spi_priv_s *priv,
void *rxbuffer,
size_t nwords)
{
const uintptr_t spi_user_reg = SPI_USER_REG(priv->config->id);
const uintptr_t spi_w0_reg = SPI_W0_REG(priv->config->id);
const uintptr_t spi_cmd_reg = SPI_CMD_REG(priv->config->id);
const uintptr_t spi_miso_dlen_reg = SPI_MISO_DLEN_REG(priv->config->id);
const uintptr_t spi_mosi_dlen_reg = SPI_MOSI_DLEN_REG(priv->config->id);
const uint32_t total_bytes = nwords * (priv->nbits / 8);
const uint32_t id = priv->config->id;
uintptr_t bytes_remaining = total_bytes;
const uint8_t *tp = (const uint8_t *)txbuffer;
uint8_t *rp = (uint8_t *)rxbuffer;
@@ -1205,7 +1209,7 @@ static void esp32s2_spi_poll_exchange(struct esp32s2_spi_priv_s *priv,
* register (W0).
*/
uintptr_t data_buf_reg = SPI_W0_REG(id);
uintptr_t data_buf_reg = spi_w0_reg;
uint32_t transfer_size = MIN(SPI_MAX_BUF_SIZE, bytes_remaining);
/* Write data words to data buffer registers.
@@ -1233,28 +1237,27 @@ static void esp32s2_spi_poll_exchange(struct esp32s2_spi_priv_s *priv,
data_buf_reg += sizeof(uintptr_t);
}
esp32s2_spi_set_regbits(SPI_USER_REG(id), SPI_USR_MOSI_M);
esp32s2_spi_set_regbits(spi_user_reg, SPI_USR_MOSI_M);
if (rp == NULL)
{
esp32s2_spi_clr_regbits(SPI_USER_REG(id), SPI_USR_MISO_M);
esp32s2_spi_clr_regbits(spi_user_reg, SPI_USR_MISO_M);
}
else
{
esp32s2_spi_set_regbits(SPI_USER_REG(id), SPI_USR_MISO_M);
esp32s2_spi_set_regbits(spi_user_reg, SPI_USR_MISO_M);
}
putreg32((transfer_size * 8) - 1, SPI_MOSI_DLEN_REG(id));
putreg32((transfer_size * 8) - 1, SPI_MISO_DLEN_REG(id));
putreg32((transfer_size * 8) - 1, spi_mosi_dlen_reg);
putreg32((transfer_size * 8) - 1, spi_miso_dlen_reg);
/* Trigger start of user-defined transaction for master. */
esp32s2_spi_set_regbits(SPI_CMD_REG(id), SPI_USR_M);
esp32s2_spi_set_regbits(spi_cmd_reg, SPI_USR_M);
/* Wait for the user-defined transaction to finish. */
while ((getreg32(SPI_CMD_REG(id)) & SPI_USR_M) != 0)
while ((getreg32(spi_cmd_reg) & SPI_USR_M) != 0)
{
;
}
@@ -1265,7 +1268,7 @@ static void esp32s2_spi_poll_exchange(struct esp32s2_spi_priv_s *priv,
* register (W0).
*/
data_buf_reg = SPI_W0_REG(id);
data_buf_reg = spi_w0_reg;
/* Read received data words from SPI data buffer registers. */
@@ -1478,6 +1481,10 @@ void esp32s2_spi_dma_init(struct spi_dev_s *dev)
static void esp32s2_spi_init(struct spi_dev_s *dev)
{
struct esp32s2_spi_priv_s *priv = (struct esp32s2_spi_priv_s *)dev;
const uintptr_t spi_user_reg = SPI_USER_REG(priv->config->id);
const uintptr_t spi_user1_reg = SPI_USER1_REG(priv->config->id);
const uintptr_t spi_slave_reg = SPI_SLAVE_REG(priv->config->id);
const uintptr_t spi_misc_reg = SPI_MISC_REG(priv->config->id);
const struct esp32s2_spi_config_s *config = priv->config;
const uint32_t id = config->id;
uint32_t regval;
@@ -1529,19 +1536,19 @@ static void esp32s2_spi_init(struct spi_dev_s *dev)
modifyreg32(SYSTEM_PERIP_RST_EN0_REG, config->rst_bit, 0);
regval = SPI_DOUTDIN_M | SPI_USR_MISO_M | SPI_USR_MOSI_M | SPI_CS_HOLD_M;
putreg32(regval, SPI_USER_REG(id));
putreg32(0, SPI_USER1_REG(id));
putreg32(0, SPI_SLAVE_REG(id));
putreg32(regval, spi_user_reg);
putreg32(0, spi_user1_reg);
putreg32(0, spi_slave_reg);
putreg32(SPI_CS1_DIS_M | SPI_CS2_DIS_M,
SPI_MISC_REG(id));
spi_misc_reg);
#if SPI_HAVE_SWCS
esp32s2_spi_set_regbits(SPI_MISC_REG(id), SPI_CS0_DIS_M);
esp32s2_spi_set_regbits(spi_misc_reg, SPI_CS0_DIS_M);
#endif
putreg32(0, SPI_CTRL_REG(id));
putreg32(VALUE_TO_FIELD(0, SPI_CS_HOLD_TIME),
SPI_USER1_REG(id));
spi_user1_reg);
#if defined(CONFIG_ESP32S2_SPI2_DMA) || defined(CONFIG_ESP32S2_SPI3_DMA)
esp32s2_spi_dma_init(dev);
arch/xtensa/src/esp32s2/esp32s2_spiflash_mtd.c
+9 -9
View File
@@ -183,7 +183,7 @@ static int esp32s2_erase(struct mtd_dev_s *dev, off_t startblock,
#ifdef CONFIG_ESP32S2_STORAGE_MTD_DEBUG
finfo("%s(%p, 0x%x, %d)\n", __func__, dev, startblock, nblocks);
finfo("spi_flash_erase_range(0x%x, %d)\n", offset, nbytes);
finfo("esp32s2_erase(0x%x, %d)\n", offset, nbytes);
#endif
ret = nxmutex_lock(&g_lock);
@@ -239,7 +239,7 @@ static ssize_t esp32s2_read(struct mtd_dev_s *dev, off_t offset,
#ifdef CONFIG_ESP32S2_STORAGE_MTD_DEBUG
finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, offset, nbytes, buffer);
finfo("spi_flash_read(0x%x, %p, %d)\n", offset, buffer, nbytes);
finfo("esp32s2_read(0x%x, %p, %d)\n", offset, buffer, nbytes);
#endif
/* Acquire the mutex. */
@@ -293,7 +293,7 @@ static ssize_t esp32s2_bread(struct mtd_dev_s *dev, off_t startblock,
finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, startblock, nblocks,
buffer);
finfo("spi_flash_read(0x%x, %p, %d)\n", addr, buffer, size);
finfo("esp32s2_bread(0x%x, %p, %d)\n", addr, buffer, size);
#endif
ret = nxmutex_lock(&g_lock);
@@ -345,7 +345,7 @@ static ssize_t esp32s2_read_decrypt(struct mtd_dev_s *dev,
#ifdef CONFIG_ESP32S2_STORAGE_MTD_DEBUG
finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, offset, nbytes, buffer);
finfo("spi_flash_read_encrypted(0x%x, %p, %d)\n", offset, buffer,
finfo("esp32s2_read_decrypt(0x%x, %p, %d)\n", offset, buffer,
nbytes);
#endif
@@ -402,7 +402,7 @@ static ssize_t esp32s2_bread_decrypt(struct mtd_dev_s *dev,
finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, startblock, nblocks,
buffer);
finfo("spi_flash_read_encrypted(0x%x, %p, %d)\n", addr, buffer, size);
finfo("esp32s2_bread_decrypt(0x%x, %p, %d)\n", addr, buffer, size);
#endif
ret = nxmutex_lock(&g_lock);
@@ -458,7 +458,7 @@ static ssize_t esp32s2_write(struct mtd_dev_s *dev, off_t offset,
#ifdef CONFIG_ESP32S2_STORAGE_MTD_DEBUG
finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, offset, nbytes, buffer);
finfo("spi_flash_write(0x%x, %p, %d)\n", offset, buffer, nbytes);
finfo("esp32s2_write(0x%x, %p, %d)\n", offset, buffer, nbytes);
#endif
/* Acquire the mutex. */
@@ -514,7 +514,7 @@ static ssize_t esp32s2_bwrite_encrypt(struct mtd_dev_s *dev,
finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, startblock,
nblocks, buffer);
finfo("spi_flash_write_encrypted(0x%x, %p, %d)\n", addr, buffer, size);
finfo("esp32s2_bwrite_encrypt(0x%x, %p, %d)\n", addr, buffer, size);
#endif
ret = nxmutex_lock(&g_lock);
@@ -523,7 +523,7 @@ static ssize_t esp32s2_bwrite_encrypt(struct mtd_dev_s *dev,
return ret;
}
ret = spi_flash_write_encrypted(addr, buffer, size);
ret = esp_rom_spiflash_write_encrypted(addr, (uint32_t *)buffer, size);
nxmutex_unlock(&g_lock);
if (ret == OK)
@@ -566,7 +566,7 @@ static ssize_t esp32s2_bwrite(struct mtd_dev_s *dev, off_t startblock,
finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, startblock,
nblocks, buffer);
finfo("spi_flash_write(0x%x, %p, %d)\n", addr, buffer, size);
finfo("esp32s2_bwrite(0x%x, %p, %d)\n", addr, buffer, size);
#endif
ret = nxmutex_lock(&g_lock);
arch/xtensa/src/esp32s2/hal.mk
+3 -1
View File
@@ -61,6 +61,9 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.api.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.libgcc.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib-data.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib-funcs.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.spiflash.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).peripherals.ld
@@ -96,7 +99,6 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c
arch/xtensa/src/esp32s3/Make.defs
+1 -1
View File
@@ -209,7 +209,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = 8e8e62cf6a7ae8a9659b91706024cab38af29118
ESP_HAL_3RDPARTY_VERSION = 51afbfd1a17e806fa6fd8227a18395c1bbecbad3
endif
ifndef ESP_HAL_3RDPARTY_URL
arch/xtensa/src/esp32s3/Wireless.mk
+4 -2
View File
@@ -80,6 +80,7 @@ CHIP_CSRCS += pkcs5.c
CHIP_CSRCS += platform_util.c
CHIP_CSRCS += platform.c
CHIP_CSRCS += sha1.c
CHIP_CSRCS += sha3.c
CHIP_CSRCS += sha256.c
CHIP_CSRCS += sha512.c
CHIP_CSRCS += pk.c
@@ -93,9 +94,9 @@ CHIP_CSRCS += md5.c
CHIP_CSRCS += oid.c
CHIP_CSRCS += pem.c
CHIP_CSRCS += hmac_drbg.c
CHIP_CSRCS += hash_info.c
CHIP_CSRCS += rsa_alt_helpers.c
CHIP_CSRCS += ecdh.c
CHIP_CSRCS += pk_ecc.c
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port
@@ -124,6 +125,7 @@ CFLAGS += $(DEFINE_PREFIX)IEEE8021X_EAPOL
CFLAGS += $(DEFINE_PREFIX)USE_WPA2_TASK
CFLAGS += $(DEFINE_PREFIX)CONFIG_SHA256
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE
CFLAGS += $(DEFINE_PREFIX)USE_WPS_TASK
ifeq ($(CONFIG_ESP_WIFI_ENABLE_SAE_PK),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE_PK
@@ -234,11 +236,11 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)
CHIP_CSRCS += esp_common.c
CHIP_CSRCS += esp_hostap.c
CHIP_CSRCS += esp_wpa_main.c
CHIP_CSRCS += esp_wpa2.c
CHIP_CSRCS += esp_wpa3.c
CHIP_CSRCS += esp_wpas_glue.c
CHIP_CSRCS += esp_owe.c
CHIP_CSRCS += esp_scan.c
CHIP_CSRCS += esp_wps.c
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src$(DELIM)crypto
arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c
+818 -330
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32s3/esp32s3_irq.c
+7 -21
View File
@@ -115,13 +115,6 @@
# define ESP32S3_WIFI_RESERVE_INT 0
#endif
#ifdef CONFIG_ESP32S3_BLE
# define ESP32S3_BLE_RESERVE_INT ((1 << ESP32S3_CPUINT_BT_BB) | \
(1 << ESP32S3_CPUINT_RWBLE))
#else
# define ESP32S3_BLE_RESERVE_INT 0
#endif
/****************************************************************************
* Public Data
****************************************************************************/
@@ -186,8 +179,7 @@ static bool g_non_iram_int_disabled_flag[CONFIG_SMP_NCPUS];
*/
static uint32_t g_cpu0_freeints = ESP32S3_CPUINT_PERIPHSET &
~(ESP32S3_WIFI_RESERVE_INT |
ESP32S3_BLE_RESERVE_INT);
~ESP32S3_WIFI_RESERVE_INT;
#ifdef CONFIG_SMP
static uint32_t g_cpu1_freeints = ESP32S3_CPUINT_PERIPHSET;
@@ -498,11 +490,6 @@ void up_irqinitialize(void)
g_irqmap[ESP32S3_IRQ_PWR] = IRQ_MKMAP(0, ESP32S3_CPUINT_PWR);
#endif
#ifdef CONFIG_ESP32S3_BLE
g_irqmap[ESP32S3_IRQ_BT_BB] = IRQ_MKMAP(0, ESP32S3_CPUINT_BT_BB);
g_irqmap[ESP32S3_IRQ_RWBLE] = IRQ_MKMAP(0, ESP32S3_CPUINT_RWBLE);
#endif
/* Initialize CPU interrupts */
esp32s3_cpuint_initialize();
@@ -515,13 +502,6 @@ void up_irqinitialize(void)
xtensa_enable_cpuint(&g_intenable[0], 1 << ESP32S3_CPUINT_MAC);
#endif
#ifdef CONFIG_ESP32S3_BLE
g_cpu0_intmap[ESP32S3_CPUINT_BT_BB] = CPUINT_ASSIGN(ESP32S3_IRQ_BT_BB);
g_cpu0_intmap[ESP32S3_CPUINT_RWBLE] = CPUINT_ASSIGN(ESP32S3_IRQ_RWBLE);
xtensa_enable_cpuint(&g_intenable[0], 1 << ESP32S3_CPUINT_BT_BB);
xtensa_enable_cpuint(&g_intenable[0], 1 << ESP32S3_CPUINT_RWBLE);
#endif
#ifdef CONFIG_SMP
/* Attach and enable the inter-CPU interrupt */
@@ -828,6 +808,12 @@ int esp32s3_setup_irq(int cpu, int periphid, int priority, int flags)
return -EINVAL;
}
if (priority > XCHAL_SYSCALL_LEVEL)
{
irqerr("Invalid priority %d\n", priority);
return -EINVAL;
}
irqstate = enter_critical_section();
/* Setting up an IRQ includes the following steps:
arch/xtensa/src/esp32s3/esp32s3_rtc.c
+15 -2
View File
@@ -378,7 +378,6 @@ static void IRAM_ATTR esp32s3_rtc_clk_fast_freq_set(
static uint32_t IRAM_ATTR esp32s3_rtc_clk_cal_internal(
enum esp32s3_rtc_cal_sel_e cal_clk,
uint32_t slowclk_cycles);
static int IRAM_ATTR esp32s3_rtc_clk_slow_freq_get(void);
static void IRAM_ATTR esp32s3_rtc_clk_slow_freq_set(
enum esp32s3_rtc_slow_freq_e slow_freq);
static void esp32s3_select_rtc_slow_clk(enum esp32s3_slow_clk_sel_e
@@ -1167,7 +1166,21 @@ static void esp32s3_rtc_calibrate_ocode(void)
* Public Functions
****************************************************************************/
static int IRAM_ATTR esp32s3_rtc_clk_slow_freq_get(void)
/****************************************************************************
* Name: esp32s3_rtc_clk_slow_freq_get
*
* Description:
* This function gets the frequency of the slow clock from the RTC.
*
* Input Parameters:
* None
*
* Returned Value:
* The frequency of the slow clock from the RTC.
*
****************************************************************************/
int IRAM_ATTR esp32s3_rtc_clk_slow_freq_get(void)
{
return REG_GET_FIELD(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
}
arch/xtensa/src/esp32s3/esp32s3_rtc.h
+16
View File
@@ -198,6 +198,22 @@ struct alm_setalarm_s
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s3_rtc_clk_slow_freq_get
*
* Description:
* This function gets the frequency of the slow clock from the RTC.
*
* Input Parameters:
* None
*
* Returned Value:
* The frequency of the slow clock from the RTC.
*
****************************************************************************/
int esp32s3_rtc_clk_slow_freq_get(void);
/****************************************************************************
* Name: esp32s3_rtc_clk_slow_freq_get_hz
*
arch/xtensa/src/esp32s3/esp32s3_spiflash.c
+17 -19
View File
@@ -48,6 +48,7 @@
#include "esp32s3_irq.h"
#include "esp32s3_spiflash.h"
#include "hal/cache_hal.h"
#include "soc/extmem_reg.h"
#include "soc/spi_mem_reg.h"
#include "rom/opi_flash.h"
@@ -187,8 +188,8 @@
static void spiflash_start(void);
static void spiflash_end(void);
static void spi_flash_disable_cache(uint32_t cpuid);
static void spi_flash_restore_cache(uint32_t cpuid);
static void spi_flash_disable_cache(void);
static void spi_flash_restore_cache(void);
#ifdef CONFIG_SMP
static int spi_flash_op_block_task(int argc, char *argv[]);
static int spiflash_init_spi_flash_op_block_task(int cpu);
@@ -220,6 +221,7 @@ static uint32_t s_flash_op_cache_state[CONFIG_SMP_NCPUS];
static rmutex_t g_flash_op_mutex;
static volatile bool g_flash_op_can_start = false;
static volatile bool g_flash_op_complete = false;
static volatile bool g_spi_flash_cache_suspended = false;
static volatile bool g_sched_suspended[CONFIG_SMP_NCPUS];
#ifdef CONFIG_SMP
static sem_t g_disable_non_iram_isr_on_core[CONFIG_SMP_NCPUS];
@@ -244,10 +246,9 @@ static void spiflash_suspend_cache(void)
int other_cpu = cpu ? 0 : 1;
#endif
spi_flash_disable_cache(cpu);
#ifdef CONFIG_SMP
spi_flash_disable_cache(other_cpu);
#endif
spi_flash_disable_cache();
g_spi_flash_cache_suspended = true;
}
/****************************************************************************
@@ -265,10 +266,9 @@ static void spiflash_resume_cache(void)
int other_cpu = cpu ? 0 : 1;
#endif
spi_flash_restore_cache(cpu);
#ifdef CONFIG_SMP
spi_flash_restore_cache(other_cpu);
#endif
spi_flash_restore_cache();
g_spi_flash_cache_suspended = false;
}
/****************************************************************************
@@ -765,17 +765,16 @@ static inline void IRAM_ATTR spiflash_os_yield(void)
* s_flash_op_cache_state.
*
* Input Parameters:
* cpuid - The CPU core whose cache will be disabled.
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
static void spi_flash_disable_cache(uint32_t cpuid)
static void spi_flash_disable_cache(void)
{
s_flash_op_cache_state[cpuid] = cache_suspend_icache() << 16;
s_flash_op_cache_state[cpuid] |= cache_suspend_dcache();
cache_hal_suspend(CACHE_TYPE_ALL);
}
/****************************************************************************
@@ -786,17 +785,16 @@ static void spi_flash_disable_cache(uint32_t cpuid)
* s_flash_op_cache_state.
*
* Input Parameters:
* cpuid - The CPU core whose cache will be restored.
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
static void spi_flash_restore_cache(uint32_t cpuid)
static void spi_flash_restore_cache(void)
{
cache_resume_dcache(s_flash_op_cache_state[cpuid] & 0xffff);
cache_resume_icache(s_flash_op_cache_state[cpuid] >> 16);
cache_hal_resume(CACHE_TYPE_ALL);
}
#ifdef CONFIG_SMP
@@ -855,7 +853,7 @@ static int spi_flash_op_block_task(int argc, char *argv[])
/* Flash operation is complete, re-enable cache */
spi_flash_restore_cache(cpu);
spi_flash_restore_cache();
/* Restore interrupts that aren't located in IRAM */
arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c
+108 -7
View File
@@ -73,7 +73,7 @@
#ifdef CONFIG_ESP32S3_BLE
# include "esp32s3_ble_adapter.h"
# ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
# include "esp_coexist_internal.h"
# include "private/esp_coexist_internal.h"
# endif
#endif
@@ -270,6 +270,8 @@ static void esp_dport_access_stall_other_cpu_start(void);
static void esp_dport_access_stall_other_cpu_end(void);
static void wifi_apb80m_request(void);
static void wifi_apb80m_release(void);
static void esp_phy_enable_wrapper(void);
static void esp_phy_disable_wrapper(void);
static int32_t esp_wifi_read_mac(uint8_t *mac, uint32_t type);
static void esp_timer_arm(void *timer, uint32_t tmout, bool repeat);
static void esp_timer_disarm(void *timer);
@@ -345,6 +347,8 @@ static void *coex_schm_curr_phase_get_wrapper(void);
static int coex_register_start_cb_wrapper(int (* cb)(void));
static int coex_schm_process_restart_wrapper(void);
static int coex_schm_register_cb_wrapper(int type, int(*cb)(int));
static int coex_schm_flexible_period_set_wrapper(uint8_t period);
static uint8_t coex_schm_flexible_period_get_wrapper(void);
/****************************************************************************
* Private Data
@@ -492,8 +496,8 @@ wifi_osi_funcs_t g_wifi_osi_funcs =
esp_dport_access_stall_other_cpu_end,
._wifi_apb80m_request = wifi_apb80m_request,
._wifi_apb80m_release = wifi_apb80m_release,
._phy_disable = esp_phy_disable,
._phy_enable = esp_phy_enable,
._phy_disable = esp_phy_disable_wrapper,
._phy_enable = esp_phy_enable_wrapper,
._phy_update_country_info = esp32s3_phy_update_country_info,
._read_mac = esp_wifi_read_mac,
._timer_arm = esp_timer_arm,
@@ -555,13 +559,11 @@ wifi_osi_funcs_t g_wifi_osi_funcs =
._coex_register_start_cb = coex_register_start_cb_wrapper,
._coex_schm_process_restart = coex_schm_process_restart_wrapper,
._coex_schm_register_cb = coex_schm_register_cb_wrapper,
._coex_schm_flexible_period_set = coex_schm_flexible_period_set_wrapper,
._coex_schm_flexible_period_get = coex_schm_flexible_period_get_wrapper,
._magic = ESP_WIFI_OS_ADAPTER_MAGIC,
};
/* Wi-Fi feature capacity data */
uint64_t g_wifi_feature_caps = CONFIG_FEATURE_WPA3_SAE_BIT;
/* Wi-Fi TAG string data */
ESP_EVENT_DEFINE_BASE(WIFI_EVENT);
@@ -2538,6 +2540,50 @@ static void wifi_apb80m_release(void)
#endif
}
/****************************************************************************
* Name: esp_phy_enable_wrapper
*
* Description:
* This is a wrapper for enabling the ESP PHY. It calls the esp_phy_enable
* function with PHY_MODEM_WIFI as the argument, and then calls the
* phy_wifi_enable_set function with 1 as the argument.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void esp_phy_enable_wrapper(void)
{
esp_phy_enable(PHY_MODEM_WIFI);
phy_wifi_enable_set(1);
}
/****************************************************************************
* Name: esp_phy_disable_wrapper
*
* Description:
* This is a wrapper for disabling the ESP PHY. It first calls the
* phy_wifi_enable_set function with 0 as the argument, and then calls the
* esp_phy_disable function with PHY_MODEM_WIFI as the argument.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void esp_phy_disable_wrapper(void)
{
phy_wifi_enable_set(0);
esp_phy_disable(PHY_MODEM_WIFI);
}
/****************************************************************************
* Name: esp_wifi_read_mac
*
@@ -4041,6 +4087,61 @@ static int coex_schm_register_cb_wrapper(int type, int(*cb)(int))
#endif
}
/****************************************************************************
* Name: coex_schm_flexible_period_set_wrapper
*
* Description:
* This is a wrapper for coex_schm_flexible_period_set. It sets the
* flexible period for the coexistence mechanism. If power management
* feature is enabled (CONFIG_ESP_COEX_POWER_MANAGEMENT), it calls the
* function with the given period. If the feature is not enabled, it
* returns 0.
*
* Input Parameters:
* period - The period to set for the coexistence mechanism.
*
* Returned Value:
* If power management is enabled, it returns the result of the
* coex_schm_flexible_period_set function. Otherwise, it returns 0.
*
****************************************************************************/
static int coex_schm_flexible_period_set_wrapper(uint8_t period)
{
#if CONFIG_ESP_COEX_POWER_MANAGEMENT
return coex_schm_flexible_period_set(period);
#else
return 0;
#endif
}
/****************************************************************************
* Name: coex_schm_flexible_period_get_wrapper
*
* Description:
* This is a wrapper for coex_schm_flexible_period_get. If power management
* feature is enabled (CONFIG_ESP_COEX_POWER_MANAGEMENT), it calls the
* function and returns its result. If the feature is not enabled, it
* returns 1.
*
* Input Parameters:
* None
*
* Returned Value:
* If power management is enabled, it returns the result of the
* coex_schm_flexible_period_get function. Otherwise, it returns 1.
*
****************************************************************************/
static uint8_t coex_schm_flexible_period_get_wrapper(void)
{
#if CONFIG_ESP_COEX_POWER_MANAGEMENT
return coex_schm_flexible_period_get();
#else
return 1;
#endif
}
/****************************************************************************
* Name: esp_random_ulong
*
arch/xtensa/src/esp32s3/esp32s3_wireless.c
+90 -2
View File
@@ -45,7 +45,7 @@
# include "esp_private/wifi.h"
# include "esp_wpa.h"
#endif
#include "esp_coexist_internal.h"
#include "private/esp_coexist_internal.h"
#include "periph_ctrl.h"
#include "esp_phy_init.h"
#include "phy_init_data.h"
@@ -339,6 +339,85 @@ static void esp_wifi_set_log_level(void)
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp_wifi_to_errno
*
* Description:
* Transform from ESP Wi-Fi error code to NuttX error code
*
* Input Parameters:
* err - ESP Wi-Fi error code
*
* Returned Value:
* NuttX error code defined in errno.h
*
****************************************************************************/
int32_t esp_wifi_to_errno(int err)
{
int ret;
if (err < ESP_ERR_WIFI_BASE)
{
/* Unmask component error bits */
ret = err & 0xfff;
switch (ret)
{
case ESP_OK:
ret = OK;
break;
case ESP_ERR_NO_MEM:
ret = -ENOMEM;
break;
case ESP_ERR_INVALID_ARG:
ret = -EINVAL;
break;
case ESP_ERR_INVALID_STATE:
ret = -EIO;
break;
case ESP_ERR_INVALID_SIZE:
ret = -EINVAL;
break;
case ESP_ERR_NOT_FOUND:
ret = -ENOSYS;
break;
case ESP_ERR_NOT_SUPPORTED:
ret = -ENOSYS;
break;
case ESP_ERR_TIMEOUT:
ret = -ETIMEDOUT;
break;
case ESP_ERR_INVALID_MAC:
ret = -EINVAL;
break;
default:
ret = ERROR;
break;
}
}
else
{
ret = ERROR;
}
if (ret != OK)
{
wlerr("ERROR: %s\n", esp_err_to_name(err));
}
return ret;
}
/****************************************************************************
* Functions needed by libphy.a
****************************************************************************/
@@ -1281,8 +1360,16 @@ int esp_wireless_deinit(void)
int32_t esp_wifi_init(const wifi_init_config_t *config)
{
int32_t ret;
uint32_t min_active_time_us =
CONFIG_ESP_WIFI_SLP_DEFAULT_MIN_ACTIVE_TIME * 1000;
uint32_t keep_alive_time_us =
CONFIG_ESP_WIFI_SLP_DEFAULT_MAX_ACTIVE_TIME * 1000 * 1000;
uint32_t wait_broadcast_data_time_us =
CONFIG_ESP_WIFI_SLP_DEFAULT_WAIT_BROADCAST_DATA_TIME * 1000;
esp_wifi_power_domain_on();
esp_wifi_set_sleep_min_active_time(min_active_time_us);
esp_wifi_set_keep_alive_time(keep_alive_time_us);
esp_wifi_set_sleep_wait_broadcast_data_time(wait_broadcast_data_time_us);
#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST
ret = coex_init();
@@ -1294,6 +1381,7 @@ int32_t esp_wifi_init(const wifi_init_config_t *config)
#endif /* CONFIG_ESP32S3_WIFI_BT_COEXIST */
esp_wifi_set_log_level();
esp_wifi_power_domain_on();
ret = esp_wifi_init_internal(config);
if (ret)
arch/xtensa/src/esp32s3/esp32s3_wireless.h
+39
View File
@@ -79,10 +79,49 @@ struct esp_queuecache_s
uint8_t *buffer;
};
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: nuttx_err_to_freertos
*
* Description:
* Transform from Nuttx OS error code to FreeRTOS's pdTRUE or pdFALSE.
*
* Input Parameters:
* ret - NuttX error code
*
* Returned Value:
* Wi-Fi adapter error code
*
****************************************************************************/
static inline int32_t nuttx_err_to_freertos(int ret)
{
return ret >= 0;
}
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp_wifi_to_errno
*
* Description:
* Transform from ESP Wi-Fi error code to NuttX error code
*
* Input Parameters:
* err - ESP Wi-Fi error code
*
* Returned Value:
* NuttX error code defined in errno.h
*
****************************************************************************/
int32_t esp_wifi_to_errno(int err);
/****************************************************************************
* Functions needed by libphy.a
****************************************************************************/
arch/xtensa/src/esp32s3/hal.mk
+6 -2
View File
@@ -65,6 +65,9 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.api.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.libgcc.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.version.ld
ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).peripherals.ld
# Source files
@@ -75,6 +78,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efus
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_rtc_calib.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_table.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_utility.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)src$(DELIM)esp_err_to_name.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c
@@ -91,9 +95,11 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)mspi_timing_config.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_common.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_esp32s2_esp32s3.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c
@@ -105,7 +111,6 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mcpwm_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal_iram.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mpu_hal.c
@@ -145,7 +150,6 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_systimer.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_esp32s2_esp32s3.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_fields.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)efuse_controller$(DELIM)keys$(DELIM)with_key_purposes$(DELIM)esp_efuse_api_key.c
arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h
-2
View File
@@ -39,8 +39,6 @@
* Pre-processor Definitions
****************************************************************************/
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i) > 3) ? ((((i) - 2) * 0x1000) + 0x10000) : (((i) - 2) * 0x1000)))
#define DR_REG_USB_BASE 0x60080000
#define DR_REG_ASSIST_DEBUG_BASE 0x600CE000
boards/risc-v/esp32c3/common/scripts/esp32c3_sections.ld
+15
View File
@@ -137,6 +137,12 @@ SECTIONS
esp_head.*(.literal .text .literal.* .text.*)
esp_start.*(.literal .text .literal.* .text.*)
*libesp_wifi.a:esp_adapter.*(.literal.coex_pti_get_wrapper .text.coex_pti_get_wrapper)
*libesp_wifi.a:wifi_netif.*(.literal.wifi_sta_receive .text.wifi_sta_receive)
*libesp_wifi.a:wifi_netif.*(.literal.wifi_transmit_wrap .text.wifi_transmit_wrap)
*libhal.a:timer_hal.*(.literal.timer_hal_capture_and_get_counter_value .text.timer_hal_capture_and_get_counter_value)
*(.wifi0iram.*)
*(.wifirxiram.*)
*(.wifislpiram.*)
@@ -291,6 +297,15 @@ SECTIONS
_instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */
_text_start = ABSOLUTE(.);
*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifi0iram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifi0iram.*)
*(.wifiextrairam .wifiextrairam.*)
*(EXCLUDE_FILE(*libpp.a) .wifiorslpiram EXCLUDE_FILE(*libpp.a) .wifiorslpiram.*)
*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifirxiram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifirxiram.*)
*(.wifislpiram .wifislpiram.*)
*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifislprxiram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifislprxiram.*)
*libesp_wifi.a:esp_adapter.*(.text .text.clear_intr_wrapper .text.coex_deinit_wrapper .text.coex_disable_wrapper .text.coex_enable_wrapper .text.coex_init_wrapper .text.coex_register_start_cb_wrapper .text.coex_schm_curr_period_get_wrapper .text.coex_schm_curr_phase_get_wrapper .text.coex_schm_flexible_period_get_wrapper .text.coex_schm_flexible_period_set_wrapper .text.coex_schm_interval_get_wrapper .text.coex_schm_process_restart_wrapper .text.coex_schm_register_cb_wrapper .text.coex_schm_status_bit_clear_wrapper .text.coex_schm_status_bit_set_wrapper .text.coex_wifi_channel_set_wrapper .text.coex_wifi_request_wrapper .text.disable_intr_wrapper .text.enable_intr_wrapper .text.esp_event_post_wrapper .text.esp_log_write_wrapper .text.esp_log_writev_wrapper .text.esp_phy_disable_wrapper .text.esp_phy_enable_wrapper .text.esp_read_mac_wrapper .text.event_group_wait_bits_wrapper .text.get_time_wrapper .text.mutex_create_wrapper .text.mutex_delete_wrapper .text.nvs_open_wrapper .text.queue_create_wrapper .text.queue_recv_wrapper .text.queue_send_to_back_wrapper .text.queue_send_to_front_wrapper .text.queue_send_wrapper .text.recursive_mutex_create_wrapper .text.set_intr_wrapper .text.set_isr_wrapper .text.task_create_pinned_to_core_wrapper .text.task_create_wrapper .text.task_get_max_priority_wrapper .text.wifi_clock_disable_wrapper .text.wifi_clock_enable_wrapper .text.wifi_create_queue .text.wifi_create_queue_wrapper .text.wifi_delete_queue .text.wifi_delete_queue_wrapper .text.wifi_reset_mac_wrapper .text.wifi_thread_semphr_free .text.wifi_thread_semphr_get_wrapper)
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_bringup.c
+1 -1
View File
@@ -77,7 +77,7 @@
#endif
#ifdef CONFIG_ESPRESSIF_WIFI_BT_COEXIST
# include "esp_coexist_internal.h"
# include "private/esp_coexist_internal.h"
#endif
#ifdef CONFIG_ESPRESSIF_WIFI
boards/risc-v/esp32c6/common/scripts/esp32c6_sections.ld
+7
View File
@@ -334,6 +334,13 @@ SECTIONS
_instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */
_text_start = ABSOLUTE(.);
*(.wifi0iram .wifi0iram.*)
*(.wifiextrairam .wifiextrairam.*)
*(.wifiorslpiram .wifiorslpiram.*)
*(.wifirxiram .wifirxiram.*)
*(.wifislpiram .wifislpiram.*)
*(.wifislprxiram .wifislprxiram.*)
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_bringup.c
+1 -1
View File
@@ -77,7 +77,7 @@
#endif
#ifdef CONFIG_ESPRESSIF_WIFI_BT_COEXIST
# include "esp_coexist_internal.h"
# include "private/esp_coexist_internal.h"
#endif
#ifdef CONFIG_ESPRESSIF_WIFI
boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_bringup.c
+1 -1
View File
@@ -77,7 +77,7 @@
#endif
#ifdef CONFIG_ESPRESSIF_WIFI_BT_COEXIST
# include "esp_coexist_internal.h"
# include "private/esp_coexist_internal.h"
#endif
#ifdef CONFIG_ESPRESSIF_WIFI
boards/risc-v/esp32h2/common/scripts/common.ld
+4
View File
@@ -19,6 +19,10 @@
****************************************************************************/
#include <nuttx/config.h>
/* From esp-hal-3rdparty */
#include "sdkconfig.h"
#include "ld.common"
#if CONFIG_ESPRESSIF_SOC_RTC_MEM_SUPPORTED
# define ESP_BOOTLOADER_RESERVE_RTC 0
boards/risc-v/esp32h2/common/scripts/esp32h2_aliases.ld
+1
View File
@@ -18,6 +18,7 @@
*
****************************************************************************/
cache_set_idrom_mmu_size = Cache_Set_IDROM_MMU_Size;
cache_resume_icache = Cache_Resume_ICache;
cache_suspend_icache = Cache_Suspend_ICache;
cache_invalidate_icache_all = Cache_Invalidate_ICache_All;
boards/risc-v/esp32h2/common/scripts/esp32h2_sections.ld
+20
View File
@@ -88,6 +88,7 @@ SECTIONS
*libarch.a:*gpio_periph.*(.text .text.* .literal .literal.*)
*libarch.a:*modem_clock_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_systimer.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_tlsf.*(.literal .literal.* .text .text.*)
*libarch.a:*esp_rom_wdt.*(.text .text.* .literal .literal.*)
*libarch.a:*ocode_init.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_regi2c_esp32h2.*(.text .text.* .literal .literal.*)
@@ -124,6 +125,7 @@ SECTIONS
*libarch.a:*uart_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*pmu_hal.*(.literal .literal.* .text .text.*)
*libarch.a:*uart_periph.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*)
*libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*)
@@ -226,6 +228,7 @@ SECTIONS
*libarch.a:*gpio_periph.*(.rodata .rodata.*)
*libarch.a:*modem_clock_hal.*(.rodata .rodata.*)
*libarch.a:*esp_rom_systimer.*(.rodata .rodata.*)
*libarch.a:*esp_rom_tlsf.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
*libarch.a:*esp_rom_wdt.*(.rodata .rodata.*)
*libarch.a:*ocode_init.*(.rodata .rodata.*)
*libarch.a:*esp_rom_regi2c_esp32h2.*(.rodata .rodata.*)
@@ -262,6 +265,7 @@ SECTIONS
*libarch.a:*uart_hal.*(.rodata .rodata.*)
*libarch.a:*mpu_hal.*(.rodata .rodata.*)
*libarch.a:*mmu_hal.*(.rodata .rodata.*)
*libarch.a:*pmu_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
*libarch.a:*uart_periph.*(.rodata .rodata.*)
*libarch.a:*esp_rom_uart.*(.rodata .rodata.*)
*libarch.a:*esp_rom_sys.*(.rodata .rodata.*)
@@ -326,12 +330,24 @@ SECTIONS
.flash.text : ALIGN(0xFFFF)
{
_stext = .;
_instruction_reserved_start = ABSOLUTE(.);
_text_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
*(.fini)
*(.gnu.version)
/** CPU will try to prefetch up to 16 bytes of
* of instructions. This means that any configuration (e.g. MMU, PMS) must allow
* safe access to up to 16 bytes after the last real instruction, add
* dummy bytes to ensure this
*/
. += _esp_flash_mmap_prefetch_pad_size;
_text_end = ABSOLUTE(.);
_instruction_reserved_end = ABSOLUTE(.);
_etext = .;
/* Similar to _iram_start, this symbol goes here so it is
@@ -435,6 +451,10 @@ SECTIONS
.rtc.text :
{
. = ALIGN(4);
_rtc_fast_start = ABSOLUTE(.);
_rtc_text_start = ABSOLUTE(.);
*(.rtc.entry.text)
*(.rtc.literal .rtc.text)
} >rtc_iram_seg
boards/xtensa/esp32/common/scripts/esp32_aliases.ld
+7
View File
@@ -22,6 +22,13 @@
/* Lower-case aliases for symbols not compliant to nxstyle */
PROVIDE( rom_i2c_writereg = rom_i2c_writeReg );
PROVIDE( cache_flash_mmu_set = cache_flash_mmu_set_rom);
PROVIDE( cache_flush = Cache_Flush_rom );
PROVIDE( cache_read_disable = Cache_Read_Disable_rom );
PROVIDE( cache_read_enable = Cache_Read_Enable_rom );
/* Bluetooth needs symbol alias, to be removed after IDF rename it */
#ifdef CONFIG_ESP32_BLE
boards/xtensa/esp32/common/scripts/esp32_rom.ld
-2088
View File
File diff suppressed because it is too large Load Diff
boards/xtensa/esp32/common/scripts/mcuboot_sections.ld
+8
View File
@@ -291,6 +291,14 @@ SECTIONS
*(.fini.literal)
*(.fini)
*(.gnu.version)
*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifi0iram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifi0iram.*)
*(.wifiextrairam .wifiextrairam.*)
*(EXCLUDE_FILE(*libpp.a) .wifiorslpiram EXCLUDE_FILE(*libpp.a) .wifiorslpiram.*)
*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifirxiram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifirxiram.*)
*(.wifislpiram .wifislpiram.*)
*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifislprxiram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifislprxiram.*)
. = ALIGN(4);
_text_end = ABSOLUTE(.);
_etext = .;
boards/xtensa/esp32/common/scripts/simple_boot_sections.ld
+8
View File
@@ -502,6 +502,14 @@ SECTIONS
*(.fini.literal)
*(.fini)
*(.gnu.version)
*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifi0iram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifi0iram.*)
*(.wifiextrairam .wifiextrairam.*)
*(EXCLUDE_FILE(*libpp.a) .wifiorslpiram EXCLUDE_FILE(*libpp.a) .wifiorslpiram.*)
*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifirxiram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifirxiram.*)
*(.wifislpiram .wifislpiram.*)
*(EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifislprxiram EXCLUDE_FILE(*libnet80211.a *libpp.a) .wifislprxiram.*)
. = ALIGN(4);
. += 16;
boards/xtensa/esp32/esp32-2432S028/scripts/Make.defs
-2
View File
@@ -23,8 +23,6 @@ include $(TOPDIR)/tools/Config.mk
include $(TOPDIR)/tools/esp32/Config.mk
include $(TOPDIR)/arch/xtensa/src/lx6/Toolchain.defs
ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32_rom.ld
# Pick the linker scripts from the board level if they exist, if not
# pick the common linker scripts.

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