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Add Timer Support to STM32H5 ADC Driver
Added support for using timers with ADCs. Updated Kconfig to support TRGO2, although driver support for TRGO and TRGO2 not developed yet. Updated hardware/stm32_tim.h with missing CCER bits needed for compilation.
This commit is contained in:
Kyle Wilson
Xiang Xiao
@@ -2920,10 +2920,10 @@ config STM32H5_ADC1_SAMPLE_FREQUENCY
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config STM32H5_ADC1_TIMTRIG
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int "ADC1 Timer Trigger"
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default 0
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range 0 4
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range 0 5
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depends on STM32H5_HAVE_ADC1_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2
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config STM32H5_ADC2_SAMPLE_FREQUENCY
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int "ADC2 Sampling Frequency"
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@@ -2935,10 +2935,10 @@ config STM32H5_ADC2_SAMPLE_FREQUENCY
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config STM32H5_ADC2_TIMTRIG
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int "ADC2 Timer Trigger"
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default 0
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range 0 4
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range 0 5
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depends on STM32H5_HAVE_ADC2_TIMER
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---help---
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
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Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2
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config STM32H5_TIM1_CAP
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bool "TIM1 Capture"
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@@ -363,6 +363,26 @@
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#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET)
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#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET)
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#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET)
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#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET)
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#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET)
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#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET)
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#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET)
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#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET)
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#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET)
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#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET)
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#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET)
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#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET)
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#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET)
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#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET)
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#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET)
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#define STM32_TIM17_DTR2 (STM32_TIM17_BASE+STM32_GTIM_DTR2_OFFSET)
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#define STM32_TIM17_TISEL (STM32_TIM17_BASE+STM32_GTIM_TISEL_OFFSET)
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#define STM32_TIM17_AF1 (STM32_TIM17_BASE+STM32_GTIM_AF1_OFFSET)
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#define STM32_TIM17_AF2 (STM32_TIM17_BASE+STM32_GTIM_AF2_OFFSET)
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#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET)
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#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET)
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/* Register Bitfield Definitions ********************************************/
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/* Basic Timers - TIM6 and TIM7 */
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@@ -764,6 +784,12 @@
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#define ATIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
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#define ATIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
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#define ATIM_CCER_CC4NE (1 << 14) /* Bit 14: Capture/compare 4 Complementary output enable */
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#define ATIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */
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#define ATIM_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */
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#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */
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#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */
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#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */
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#define ATIM_CCER_CCXBASE(ch) ((ch) << 2) /* Each channel uses 4-bits */
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/* Counter Register */
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File diff suppressed because it is too large
Load Diff
@@ -38,6 +38,462 @@
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#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2)
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/* Configuration ************************************************************/
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/* Timer devices may be used for different purposes. One special purpose is
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* to control periodic ADC sampling. If CONFIG_STM32H5_TIMn is defined then
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* CONFIG_STM32H5_TIMn_ADC must also be defined to indicate that timer "n"
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* is intended to be used for that purpose. Timers 1,2,3,6 and 15 may be
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* used on STM32H5X3, while STM32H5X6 adds support for timers 4 and 8 as
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* well.
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*/
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#ifndef CONFIG_STM32H5_TIM1
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# undef CONFIG_STM32H5_TIM1_ADC
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# undef CONFIG_STM32H5_TIM1_ADC1
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# undef CONFIG_STM32H5_TIM1_ADC2
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# undef CONFIG_STM32H5_TIM1_ADC3
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#endif
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#ifndef CONFIG_STM32H5_TIM2
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# undef CONFIG_STM32H5_TIM2_ADC
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# undef CONFIG_STM32H5_TIM2_ADC1
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# undef CONFIG_STM32H5_TIM2_ADC2
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# undef CONFIG_STM32H5_TIM2_ADC3
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#endif
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#ifndef CONFIG_STM32H5_TIM3
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# undef CONFIG_STM32H5_TIM3_ADC
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# undef CONFIG_STM32H5_TIM3_ADC1
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# undef CONFIG_STM32H5_TIM3_ADC2
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# undef CONFIG_STM32H5_TIM3_ADC3
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#endif
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#ifndef CONFIG_STM32H5_TIM4
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# undef CONFIG_STM32H5_TIM4_ADC
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# undef CONFIG_STM32H5_TIM4_ADC1
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# undef CONFIG_STM32H5_TIM4_ADC2
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# undef CONFIG_STM32H5_TIM4_ADC3
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#endif
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#ifndef CONFIG_STM32H5_TIM6
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# undef CONFIG_STM32H5_TIM6_ADC
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# undef CONFIG_STM32H5_TIM6_ADC1
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# undef CONFIG_STM32H5_TIM6_ADC2
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# undef CONFIG_STM32H5_TIM6_ADC3
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#endif
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#ifndef CONFIG_STM32H5_TIM8
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# undef CONFIG_STM32H5_TIM8_ADC
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# undef CONFIG_STM32H5_TIM8_ADC1
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# undef CONFIG_STM32H5_TIM8_ADC2
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# undef CONFIG_STM32H5_TIM8_ADC3
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#endif
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#ifndef CONFIG_STM32H5_TIM15
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# undef CONFIG_STM32H5_TIM15_ADC
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# undef CONFIG_STM32H5_TIM15_ADC1
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# undef CONFIG_STM32H5_TIM15_ADC2
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# undef CONFIG_STM32H5_TIM15_ADC3
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#endif
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/* Timer configuration: If a timer trigger is specified, then get
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* information about the timer.
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*/
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#if defined(CONFIG_STM32H5_TIM1_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32_TIM1_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
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# define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR
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# define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM1EN
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#elif defined(CONFIG_STM32H5_TIM2_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32_TIM2_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
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# define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR
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# define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM2EN
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#elif defined(CONFIG_STM32H5_TIM3_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32_TIM3_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
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# define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR
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# define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM3EN
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#elif defined(CONFIG_STM32H5_TIM4_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32_TIM4_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
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# define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR
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# define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM4EN
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#elif defined(CONFIG_STM32H5_TIM6_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32_TIM6_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
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# define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR
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# define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM6EN
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#elif defined(CONFIG_STM32H5_TIM8_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32_TIM8_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
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# define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR
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# define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM8EN
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#elif defined(CONFIG_STM32H5_TIM15_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32_TIM15_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
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# define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR
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# define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM15EN
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#else
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# undef ADC1_HAVE_TIMER
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#endif
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#ifdef ADC1_HAVE_TIMER
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# ifndef CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY
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# error "CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY not defined"
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# endif
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# ifndef CONFIG_STM32H5_ADC1_TIMTRIG
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# error "CONFIG_STM32H5_ADC1_TIMTRIG not defined"
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# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
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# endif
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#endif
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#if defined(CONFIG_STM32H5_TIM1_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32_TIM1_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN
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# define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR
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# define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM1EN
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#elif defined(CONFIG_STM32H5_TIM2_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32_TIM2_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN
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# define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR
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# define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM2EN
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#elif defined(CONFIG_STM32H5_TIM3_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32_TIM3_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN
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# define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR
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# define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM3EN
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#elif defined(CONFIG_STM32H5_TIM4_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32_TIM4_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN
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# define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR
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# define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM4EN
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#elif defined(CONFIG_STM32H5_TIM6_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32_TIM6_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN
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# define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR
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# define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM6EN
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#elif defined(CONFIG_STM32H5_TIM8_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32_TIM8_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN
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# define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR
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# define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM8EN
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#elif defined(CONFIG_STM32H5_TIM15_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32_TIM15_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN
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# define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR
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# define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM15EN
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#else
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# undef ADC2_HAVE_TIMER
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#endif
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#ifdef ADC2_HAVE_TIMER
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# ifndef CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY
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# error "CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY not defined"
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# endif
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# ifndef CONFIG_STM32H5_ADC2_TIMTRIG
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# error "CONFIG_STM32H5_ADC2_TIMTRIG not defined"
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# warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO"
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# endif
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#endif
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#if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER)
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# define ADC_HAVE_TIMER 1
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#else
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# undef ADC_HAVE_TIMER
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#endif
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/* Timer 1 */
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#define ADC1_EXTSEL_T1CC1 ADC_CFGR_EXTSEL_T1CC1
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#define ADC1_EXTSEL_T1CC2 ADC_CFGR_EXTSEL_T1CC2
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#define ADC1_EXTSEL_T1CC3 ADC_CFGR_EXTSEL_T1CC3
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#define ADC1_EXTSEL_T1CC4 ADC_CFGR_EXTSEL_T1CC4
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#define ADC1_EXTSEL_T1TRGO ADC_CFGR_EXTSEL_T1TRGO
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#define ADC1_EXTSEL_T1TRGO2 ADC_CFGR_EXTSEL_T1TRGO2
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#define ADC2_EXTSEL_T1CC1 ADC_CFGR_EXTSEL_T1CC1
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#define ADC2_EXTSEL_T1CC2 ADC_CFGR_EXTSEL_T1CC2
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#define ADC2_EXTSEL_T1CC3 ADC_CFGR_EXTSEL_T1CC3
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#define ADC2_EXTSEL_T1CC4 ADC_CFGR_EXTSEL_T1CC4
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#define ADC2_EXTSEL_T1TRGO ADC_CFGR_EXTSEL_T1TRGO
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#define ADC2_EXTSEL_T1TRGO2 ADC_CFGR_EXTSEL_T1TRGO2
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/* Timer 2 */
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#define ADC1_EXTSEL_T2CC2 ADC_CFGR_EXTSEL_T2CC2
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#define ADC1_EXTSEL_T2TRGO ADC_CFGR_EXTSEL_T2TRGO
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#define ADC2_EXTSEL_T2CC2 ADC_CFGR_EXTSEL_T2CC2
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#define ADC2_EXTSEL_T2TRGO ADC_CFGR_EXTSEL_T2TRGO
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/* Timer 3 */
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#define ADC1_EXTSEL_T3CC4 ADC_CFGR_EXTSEL_T3CC4
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#define ADC1_EXTSEL_T3TRGO ADC_CFGR_EXTSEL_T3TRGO
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#define ADC2_EXTSEL_T3CC4 ADC_CFGR_EXTSEL_T3CC4
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#define ADC2_EXTSEL_T3TRGO ADC_CFGR_EXTSEL_T3TRGO
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/* Timer 4 */
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#define ADC1_EXTSEL_T4CC4 ADC_CFGR_EXTSEL_T4CC4
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#define ADC1_EXTSEL_T4TRGO ADC_CFGR_EXTSEL_T4TRGO
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#define ADC2_EXTSEL_T4CC4 ADC_CFGR_EXTSEL_T4CC4
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#define ADC2_EXTSEL_T4TRGO ADC_CFGR_EXTSEL_T4TRGO
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/* Timer 6 */
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#define ADC1_EXTSEL_T6TRGO ADC_CFGR_EXTSEL_T6TRGO
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#define ADC2_EXTSEL_T6TRGO ADC_CFGR_EXTSEL_T6TRGO
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/* Timer 8 */
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#define ADC1_EXTSEL_T8TRGO ADC_CFGR_EXTSEL_T8TRGO
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#define ADC1_EXTSEL_T8TRGO2 ADC_CFGR_EXTSEL_T8TRGO2
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#define ADC2_EXTSEL_T8TRGO ADC_CFGR_EXTSEL_T8TRGO
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#define ADC2_EXTSEL_T8TRGO2 ADC_CFGR_EXTSEL_T8TRGO2
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/* Timer 15 */
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#define ADC1_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO
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#define ADC2_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO
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#if defined(CONFIG_STM32H5_TIM1_ADC1)
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# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
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# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1
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# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
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# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2
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# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
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# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3
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# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
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# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4
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# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
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# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO
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# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
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# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2
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# else
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# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM1)"
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# endif
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#elif defined(CONFIG_STM32H5_TIM2_ADC1)
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# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
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# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
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# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
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# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2
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# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
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# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
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# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
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# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
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# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
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# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO
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# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
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# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)"
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# else
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# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM2)"
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# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM3_ADC1)
|
||||
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM3)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM4_ADC1)
|
||||
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM4)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM6_ADC1)
|
||||
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM6)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM8_ADC1)
|
||||
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM8)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM15_ADC1)
|
||||
# if CONFIG_STM32H5_ADC1_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4
|
||||
# define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO
|
||||
# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM15)"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32H5_TIM1_ADC2)
|
||||
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM1)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM2_ADC2)
|
||||
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM2)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM3_ADC2)
|
||||
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM3)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM4_ADC2)
|
||||
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM4)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM6_ADC2)
|
||||
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM6)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM8_ADC2)
|
||||
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM8)"
|
||||
# endif
|
||||
#elif defined(CONFIG_STM32H5_TIM15_ADC2)
|
||||
# if CONFIG_STM32H5_ADC2_TIMTRIG == 0
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4
|
||||
# define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15TRGO
|
||||
# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)"
|
||||
# else
|
||||
# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM15)"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
Reference in New Issue
Block a user