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xtensa_int_handlers.S: Refactor the calls to ps_setup.
Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit is contained in:
Abdelatif Guettouche
committed by
Gustavo Henrique Nihei
Gustavo Henrique Nihei
parent
54b770d46a
commit
541eabb535
@@ -121,18 +121,58 @@ g_intstacktop:
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#endif
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/****************************************************************************
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* Macro dispatch_c_isr level mask
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* Macro: ps_setup
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*
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* Description:
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* Set up PS for C, enable interrupts above this level and clear EXCM.
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*
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* Entry Conditions:
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* level - interrupt level
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* tmp - scratch register
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*
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* Side Effects:
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* PS and scratch register modified
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*
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* Assumptions:
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* - PS.EXCM = 1, C calling disabled
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*
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****************************************************************************/
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.macro ps_setup level tmp
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#if 0 /* Nested interrupts no yet supported */
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# ifdef __XTENSA_CALL0_ABI__
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/* Disable interrupts at level and below */
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movi \tmp, PS_INTLEVEL(\level) | PS_UM
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# else
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movi \tmp, PS_INTLEVEL(\level) | PS_UM | PS_WOE
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# endif
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#else
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# ifdef __XTENSA_CALL0_ABI__
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/* Disable all low- and medium-priority interrupts. Nested are not yet
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* supported.
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*/
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movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
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# else
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movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
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# endif
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#endif
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wsr \tmp, PS
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rsync
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.endm
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/****************************************************************************
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* Macro dispatch_c_isr level mask tmp
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*
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* Description:
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*
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* This will dispatch to user handlers (if any) that are registered in the
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* XTOS dispatch table (_xtos_interrupt_table). These handlers would have
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* been registered by calling _xtos_set_interrupt_handler(). There is one
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* exception - the timer interrupt used by the OS will not be dispatched
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* to a user handler - this must be handled by the caller of this macro.
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*
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* Level triggered and software interrupts are automatically deasserted by
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* this code.
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* This macro will dispatch the set of pending and enabled interrupts to
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* their handlers. It just does the necessary configuration and ends up
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* calling xtensa_int_decode.
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*
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* Assumptions:
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* - PS.INTLEVEL is set to "level" at entry
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@@ -150,7 +190,11 @@ g_intstacktop:
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*
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****************************************************************************/
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.macro dispatch_c_isr level mask
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.macro dispatch_c_isr level mask tmp
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/* Set up PS for C, enable interrupts above this level and clear EXCM. */
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ps_setup \level \tmp
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#ifdef __XTENSA_CALL0_ABI__
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/* Get mask of pending, enabled interrupts at this level into a2. */
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@@ -233,51 +277,6 @@ g_intstacktop:
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1:
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.endm
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/****************************************************************************
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* Macro: ps_setup
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*
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* Description:
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* Set up PS for C, enable interrupts above this level and clear EXCM.
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*
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* Entry Conditions:
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* level - interrupt level
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* tmp - scratch register
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*
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* Side Effects:
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* PS and scratch register modified
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*
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* Assumptions:
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* - PS.EXCM = 1, C calling disabled
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*
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****************************************************************************/
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.macro ps_setup level tmp
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#if 0 /* Nested interrupts no yet supported */
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# ifdef __XTENSA_CALL0_ABI__
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/* Disable interrupts at level and below */
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movi \tmp, PS_INTLEVEL(\level) | PS_UM
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# else
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movi \tmp, PS_INTLEVEL(\level) | PS_UM | PS_WOE
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# endif
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#else
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# ifdef __XTENSA_CALL0_ABI__
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/* Disable all low- and medium-priority interrupts. Nested are not yet
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* supported.
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*/
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movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
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# else
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movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
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# endif
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#endif
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wsr \tmp, PS
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rsync
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.endm
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@@ -322,10 +321,6 @@ _xtensa_level1_handler:
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setintstack a13 a14
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#endif
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/* Set up PS for C, enable interrupts above this level and clear EXCM. */
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ps_setup 1 a0
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/* Decode and dispatch the interrupt. In the event of an interrupt
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* level context dispatch_c_isr() will (1) switch stacks to the new
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* thread's and (2) provide the address of the register state save
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@@ -333,7 +328,7 @@ _xtensa_level1_handler:
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* in the new thread's stack.
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*/
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dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK
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dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK a0
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/* Restore registers in preparation to return from interrupt */
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@@ -420,10 +415,6 @@ _xtensa_level2_handler:
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setintstack a13 a14
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#endif
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/* Set up PS for C, enable interrupts above this level and clear EXCM. */
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ps_setup 2 a0
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/* Decode and dispatch the interrupt. In the event of an interrupt
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* level context dispatch_c_isr() will (1) switch stacks to the new
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* thread's and (2) provide the address of the register state save
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@@ -431,7 +422,7 @@ _xtensa_level2_handler:
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* in the new thread's stack.
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*/
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dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK
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dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK a0
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/* Restore registers in preparation to return from interrupt */
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@@ -493,10 +484,6 @@ _xtensa_level3_handler:
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setintstack a13 a14
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#endif
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/* Set up PS for C, enable interrupts above this level and clear EXCM. */
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ps_setup 3 a0
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/* Decode and dispatch the interrupt. In the event of an interrupt
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* level context dispatch_c_isr() will (1) switch stacks to the new
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* thread's and (2) provide the address of the register state save
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@@ -504,7 +491,7 @@ _xtensa_level3_handler:
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* in the new thread's stack.
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*/
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dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK
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dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK a0
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/* Restore registers in preparation to return from interrupt */
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@@ -566,10 +553,6 @@ _xtensa_level4_handler:
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setintstack a13 a14
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#endif
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/* Set up PS for C, enable interrupts above this level and clear EXCM. */
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ps_setup 4 a0
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/* Decode and dispatch the interrupt. In the event of an interrupt
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* level context dispatch_c_isr() will (1) switch stacks to the new
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* thread's and (2) provide the address of the register state save
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@@ -577,7 +560,7 @@ _xtensa_level4_handler:
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* in the new thread's stack.
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*/
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dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK
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dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK a0
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/* Restore registers in preparation to return from interrupt */
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@@ -639,10 +622,6 @@ _xtensa_level5_handler:
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setintstack a13 a14
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#endif
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/* Set up PS for C, enable interrupts above this level and clear EXCM. */
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ps_setup 5 a0
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/* Decode and dispatch the interrupt. In the event of an interrupt
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* level context dispatch_c_isr() will (1) switch stacks to the new
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* thread's and (2) provide the address of the register state save
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@@ -650,7 +629,7 @@ _xtensa_level5_handler:
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* in the new thread's stack.
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*/
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dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK
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dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK a0
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/* Restore registers in preparation to return from interrupt */
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@@ -712,10 +691,6 @@ _xtensa_level6_handler:
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setintstack a13 a14
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#endif
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/* Set up PS for C, enable interrupts above this level and clear EXCM. */
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ps_setup 6 a0
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/* Decode and dispatch the interrupt. In the event of an interrupt
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* level context dispatch_c_isr() will (1) switch stacks to the new
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* thread's and (2) provide the address of the register state save
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@@ -723,7 +698,7 @@ _xtensa_level6_handler:
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* in the new thread's stack.
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*/
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dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK
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dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK a0
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/* Restore registers in preparation to return from interrupt */
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