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libs/libc/machine/arm: add Cortex-M0/M23 support to arch_mcount

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Add support for ARMv6-M and ARMv8-M Baseline architectures
(Cortex-M0/M0+/M23) in the mcount profiling function. These cores
only support limited Thumb-1 instruction set and require different
assembly instructions compared to ARMv7-M and higher.

Changes:
- Use MOVS+BICS instead of BIC for bit clearing on M0/M23
- Separate register restore for limited push/pop instructions
- Use BX instead of direct POP to PC on M0/M23

Signed-off-by: yinshengkai <yinshengkai@bytedance.com>
This commit is contained in:
yinshengkai
2026-02-03 16:41:39 +08:00
committed by Xiang Xiao
parent 871a9b3261
commit 54040c6888
1 changed files with 15 additions and 0 deletions
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15
libs/libc/machine/arm/arch_mcount.S
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@@ -29,6 +29,20 @@
.type __gnu_mcount_nc, %function
__gnu_mcount_nc:
#if defined(CONFIG_ARCH_CORTEXM0) || defined(CONFIG_ARCH_CORTEXM23)
/* Cortex-M0/M0+/M23 - ARMv6-M and ARMv8-M Baseline */
/* These cores only support limited Thumb-1 instruction set */
push {r0, r1, r2, r3, lr} /* Save registers */
mov r1, lr
movs r2, #1
bics r1, r2 /* R1 contains callee address, with thumb bit cleared */
ldr r0, [sp, #20] /* R0 contains caller address */
movs r2, #1
bics r0, r2 /* Clear thumb bit */
bl mcount_internal /* Jump to internal _mcount() implementation */
pop {r0, r1, r2, r3, pc} /* Restore r0-r3 and return to caller */
#else
/* ARMv7-M/A/R and higher - Full Thumb-2 support */
push {r0, r1, r2, r3, lr} /* Save registers */
mov r1, lr
bic r1, r1, #1 /* R1 contains callee address, with thumb bit cleared */
@@ -37,6 +51,7 @@ __gnu_mcount_nc:
bl mcount_internal /* Jump to internal _mcount() implementation */
pop {r0, r1, r2, r3, ip, lr} /* Restore saved registers */
bx ip /* Return to callee */
#endif
.size __gnu_mcount_nc, .-__gnu_mcount_nc
.end