arch/arm/src/stm32h5: Add support for USB host

Added stm32_usbdrdhost.c which adds USB FS host mode support using the
embedded PHY. Added Kconfig to select Device or Host.

Example config nucleo-h563zi:usbmsc added to test functionality

Signed-off-by: daniellizewski <daniellizewski@geotab.com>

Documentation/platforms/arm/stm32h5/index.rst

@@ -49,7 +49,7 @@ OCTOSPI     Yes      Implemented as QSPI.
 PWR         Yes      Partial.
 SPI         Yes
 TIM         Yes
-USB_FS      Yes      USB Device Support.
+USB_FS      Yes      USB Device and Host Support.
 
 AES         No
 CEC         No
@@ -86,6 +86,26 @@ WWDG        No
 
 ==========  =======  =====
 
+USB FS Host
+-----------
+
+STM32 USB FS Host Driver Support. The STM32H5 is equipped with a Dual Role USB device
+capable of operating as a device or host. 
+
+Pre-requisites:
+
+- CONFIG_USBHOST         - Enable USB host support
+- CONFIG_STM32H5_USBFS_HOST  - Enable the STM32 USB OTG FS block in host mode
+
+USB host requires a stable 48MHz clock. This should come from a PLL driven by the HSE.
+HSI48 cannot be reliably used in host mode due to drift. It can only be used in device mode.
+
+Options:
+
+- STM32H5_USBDRD_NCHANNELS - Number of host channels. Default 8
+
+- STM32H5_USBDRD_DESCSIZE - Maximum size of a descriptor.  Default: 128
+
 References
 =================
 [RM0481] Reference Manual: STM32H523/33xx, STM32H562/63xx, and STM32H573xx Arm® -based 32-bit MCUs

arch/arm/src/stm32h5/CMakeLists.txt

@@ -96,6 +96,10 @@ if(CONFIG_STM32H5_USBFS)
   list(APPEND SRCS stm32_usbfs.c)
 endif()
 
+if(CONFIG_STM32H5_USBFS_HOST)
+  list(APPEND SRCS stm32_usbdrdhost.c)
+endif()
+
 if(CONFIG_STM32H5_ETHMAC)
   list(APPEND SRCS stm32_ethernet.c)
 endif()

arch/arm/src/stm32h5/Kconfig

@@ -651,12 +651,30 @@ config STM32H5_TIM17
 
 endmenu # STM32H5 Timer Selection
 
+choice STM32H5_USBFS_MODE
+	prompt "USB FS Mode"
+	depends on STM32H5_HAVE_USBFS
+	default STM32H5_USBFS_NONE
+	---help---
+	  Select the operating mode for the USB_DRD_FS peripheral.
+	  The hardware supports Device or Host, but not simultaneously.
+
+config STM32H5_USBFS_NONE
+	bool "Disabled"
+
 config STM32H5_USBFS
 	bool "USB Device"
-	default n
-	depends on STM32H5_HAVE_USBFS
 	select USBDEV
 
+config STM32H5_USBFS_HOST
+	bool "USB Host"
+	select USBHOST_HAVE_ASYNCH
+	select USBHOST
+	---help---
+	  Enable USB host mode for USB_DRD_FS peripheral.
+
+endchoice
+
 endmenu # STM32H5 Peripheral Selection
 
 menu "DTS Configuration"
@@ -4473,7 +4491,7 @@ endmenu # Timer Configuration
 
 comment "USB Device Configuration"
 
-menu "USB Full Speed Debug Configuration"
+menu "USB Full Speed Device Configuration"
 	depends on STM32H5_USBFS
 
 config STM32H5_USBFS_REGDEBUG
@@ -4485,6 +4503,28 @@ config STM32H5_USBFS_REGDEBUG
 
 endmenu
 
+comment "USB Host Configuration"
+
+menu "USB Full Speed Host Configuration"
+	depends on STM32H5_USBFS_HOST
+
+config STM32H5_USBDRD_NCHANNELS
+	int "Number of host channels"
+	default 8
+	range 1 8
+	depends on STM32H5_USBFS_HOST
+	---help---
+		Number of USB host channels to use.
+
+config STM32H5_USBDRD_DESCSIZE
+	int "Descriptor buffer size"
+	default 128
+	depends on STM32H5_USBFS_HOST
+	---help---
+		Size of descriptor/request buffers.
+
+endmenu
+
 config STM32H5_SERIALDRIVER
 	bool
 

arch/arm/src/stm32h5/Make.defs

@@ -92,6 +92,10 @@ ifeq ($(CONFIG_STM32H5_USBFS),y)
 CHIP_CSRCS += stm32_usbfs.c
 endif
 
+ifeq ($(CONFIG_STM32H5_USBFS_HOST),y)
+CHIP_CSRCS += stm32_usbdrdhost.c
+endif
+
 ifeq ($(CONFIG_STM32H5_ETHMAC),y)
 CHIP_CSRCS += stm32_ethernet.c
 endif

arch/arm/src/stm32h5/hardware/stm32_usbfs.h

@@ -151,6 +151,9 @@
 #define USB_CNTR_ERRM                  (1 << 13) /* Bit 13: Error Interrupt Mask */
 #define USB_CNTR_PMAOVRN               (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */
 #define USB_CNTR_CTRM                  (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */
+#define USB_CNTR_THR512M               (1 << 16) /* Bit 16: 512byte Threshold interrupt mask */
+#define USB_CNTR_DDISCM                (1 << 17) /* Bit 17: Device disconnection mask */
+#define USB_CNTR_HOST                  (1 << 31) /* Bit 31: Host Mode */
 
 #define USB_CNTR_ALLINTS               (USB_CNTR_L1REQ|USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|\
                                         USB_CNTR_SUSPM|USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_PMAOVRN|\
@@ -164,12 +167,16 @@
 #define USB_ISTR_L1REQ                 (1 << 7)  /* Bit 7:  LPM L1 state request */
 #define USB_ISTR_ESOF                  (1 << 8)  /* Bit 8:  Expected Start Of Frame */
 #define USB_ISTR_SOF                   (1 << 9)  /* Bit 9:  Start Of Frame */
-#define USB_ISTR_RESET                 (1 << 10) /* Bit 10: USB RESET request */
+#define USB_ISTR_RESET                 (1 << 10) /* Bit 10: USB RESET request. Device connection in Host mode */
 #define USB_ISTR_SUSP                  (1 << 11) /* Bit 11: Suspend mode request */
 #define USB_ISTR_WKUP                  (1 << 12) /* Bit 12: Wake up */
 #define USB_ISTR_ERR                   (1 << 13) /* Bit 13: Error */
 #define USB_ISTR_PMAOVRN               (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */
 #define USB_ISTR_CTR                   (1 << 15) /* Bit 15: Correct Transfer */
+#define USB_ISTR_THR512                (1 << 16) /* Bit 16: 512byte threshold interrupt */
+#define USB_ISTR_DDISC                 (1 << 17) /* Bit 17: Device disconnection */
+#define USB_ISTR_DCON_STAT             (1 << 29) /* Bit 29: Device connection status */
+#define USB_ISTR_LS_DCONN              (1 << 30) /* Bit 30: Low-speed device connected */
 
 #define USB_ISTR_ALLINTS               (USB_ISTR_L1REQ|USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|\
                                         USB_ISTR_SUSP|USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_PMAOVRN|\
@@ -210,18 +217,118 @@
 #define USB_BCDR_SDET                  (1 << 6)  /* Bit 6:  Secondary detection (SD) status */
 #define USB_BCDR_PS2DET                (1 << 7)  /* Bit 7:  DM pull-up detection status */
 #define USB_BCDR_DPPU                  (1 << 15) /* Bit 15: DP pull-up control */
+#define USB_BCDR_DPPD                  (1 << 15) /* Bit 15: DP pull-down control (host mode) */
+
+/****************************************************************************
+ * USB DRD Host Mode Register Definitions
+ ****************************************************************************/
+
+/* Channel/Endpoint register */
+
+#define USB_CHEP_ADDR_SHIFT            (0)       /* Bits 3-0: Endpoint address */
+#define USB_CHEP_ADDR_MASK             (0xf << USB_CHEP_ADDR_SHIFT)
+#define USB_CHEP_TX_STTX_SHIFT         (4)       /* Bits 5-4: Status TX */
+#define USB_CHEP_TX_STTX_MASK          (3 << USB_CHEP_TX_STTX_SHIFT)
+#  define USB_CHEP_TX_STTX_DIS         (0 << USB_CHEP_TX_STTX_SHIFT) /* Channel TX disabled */
+#  define USB_CHEP_TX_STTX_STALL       (1 << USB_CHEP_TX_STTX_SHIFT) /* Channel TX stalled */
+#  define USB_CHEP_TX_STTX_NAK         (2 << USB_CHEP_TX_STTX_SHIFT) /* Channel TX NAK */
+#  define USB_CHEP_TX_STTX_VALID       (3 << USB_CHEP_TX_STTX_SHIFT) /* Channel TX valid */
+#  define USB_CHEP_TX_DTOG1            (1 << USB_CHEP_TX_STTX_SHIFT) /* TX Data Toggle bit 1 */
+#  define USB_CHEP_TX_DTOG2            (2 << USB_CHEP_TX_STTX_SHIFT) /* TX Data Toggle bit 2 */
+
+#define USB_CHEP_DTOG_TX               (1 << 6)  /* Bit 6: Data Toggle TX */
+#define USB_CHEP_VTTX                  (1 << 7)  /* Bit 7: Valid transaction transmitted */
+#define USB_CHEP_KIND                  (1 << 8)  /* Bit 8: Endpoint/Channel KIND */
+#define USB_CHEP_UTYPE_SHIFT           (9)       /* Bits 10-9: USB type of transaction */
+#define USB_CHEP_UTYPE_MASK            (3 << USB_CHEP_UTYPE_SHIFT)
+#  define USB_CHEP_UTYPE_BULK          (0 << USB_CHEP_UTYPE_SHIFT) /* Bulk transfer */
+#  define USB_CHEP_UTYPE_CTRL          (1 << USB_CHEP_UTYPE_SHIFT) /* Control transfer */
+#  define USB_CHEP_UTYPE_ISOC          (2 << USB_CHEP_UTYPE_SHIFT) /* Isochronous transfer */
+#  define USB_CHEP_UTYPE_INTR          (3 << USB_CHEP_UTYPE_SHIFT) /* Interrupt transfer */
+
+#define USB_CHEP_SETUP                 (1 << 11) /* Bit 11: Setup transaction completed */
+#define USB_CHEP_RX_STRX_SHIFT         (12)      /* Bits 13-12: Status RX */
+#define USB_CHEP_RX_STRX_MASK          (3 << USB_CHEP_RX_STRX_SHIFT)
+#  define USB_CHEP_RX_STRX_DIS         (0 << USB_CHEP_RX_STRX_SHIFT) /* Channel RX disabled */
+#  define USB_CHEP_RX_STRX_STALL       (1 << USB_CHEP_RX_STRX_SHIFT) /* Channel RX stalled */
+#  define USB_CHEP_RX_STRX_NAK         (2 << USB_CHEP_RX_STRX_SHIFT) /* Channel RX NAK */
+#  define USB_CHEP_RX_STRX_VALID       (3 << USB_CHEP_RX_STRX_SHIFT) /* Channel RX valid */
+#  define USB_CHEP_RX_DTOG1            (1 << USB_CHEP_RX_STRX_SHIFT) /* RX Data Toggle bit 1 */
+#  define USB_CHEP_RX_DTOG2            (2 << USB_CHEP_RX_STRX_SHIFT) /* RX Data Toggle bit 2 */
+
+#define USB_CHEP_DTOG_RX               (1 << 14) /* Bit 14: Data Toggle RX */
+#define USB_CHEP_VTRX                  (1 << 15) /* Bit 15: Valid transaction received */
+#define USB_CHEP_DEVADDR_SHIFT         (16)      /* Bits 22-16: Target device address */
+#define USB_CHEP_DEVADDR_MASK          (0x7f << USB_CHEP_DEVADDR_SHIFT)
+#define USB_CHEP_NAK                   (1 << 23) /* Bit 23: Previous NAK detected */
+#define USB_CHEP_LSEP                  (1 << 24) /* Bit 24: Low Speed Endpoint */
+#define USB_CHEP_ERRTX                 (1 << 25) /* Bit 25: Transmit error */
+#define USB_CHEP_ERRRX                 (1 << 26) /* Bit 26: Receive error */
+
+/* Register mask for preserving r/w bits when modifying toggle bits */
+
+#define USB_CHEP_REG_MASK              (USB_CHEP_ERRRX | USB_CHEP_ERRTX | \
+                                        USB_CHEP_LSEP | USB_CHEP_DEVADDR_MASK | \
+                                        USB_CHEP_VTRX | USB_CHEP_SETUP | \
+                                        USB_CHEP_UTYPE_MASK | USB_CHEP_KIND | \
+                                        USB_CHEP_VTTX | USB_CHEP_ADDR_MASK | \
+                                        USB_CHEP_NAK)
+
+#define USB_CHEP_TX_DTOGMASK           (USB_CHEP_TX_STTX_MASK | USB_CHEP_REG_MASK)
+#define USB_CHEP_RX_DTOGMASK           (USB_CHEP_RX_STRX_MASK | USB_CHEP_REG_MASK)
+#define USB_CH_T_MASK                  ((~USB_CHEP_UTYPE_MASK) & USB_CHEP_REG_MASK)
+#define USB_CHEP_DB_MSK                (0xffff0f0f)
+
+/* PMA (Packet Memory Area) definitions for host mode */
+
+#define USB_DRD_PMA_SIZE               (2048)     /* 2KB PMA */
+#define USB_DRD_NCHANNELS              (8)        /* 8 host channels */
+
+/* PMA buffer descriptor structure address calculation
+ * Each channel has TX and RX buffer descriptors (8 bytes total per channel)
+ */
+
+#define USB_PMA_TXBD_OFFSET(ch)        ((ch) * 8)
+#define USB_PMA_RXBD_OFFSET(ch)        ((ch) * 8 + 4)
+
+/* PMA TX buffer descriptor bit definitions */
+
+#define USB_PMA_TXBD_ADDR_SHIFT        (2)        /* Bits 15:2: TX buffer address */
+#define USB_PMA_TXBD_ADDR_MASK         (0x3fff << USB_PMA_TXBD_ADDR_SHIFT)
+#define USB_PMA_TXBD_COUNT_SHIFT       (16)       /* Bits 25:16: TX byte count */
+#define USB_PMA_TXBD_COUNT_MASK        (0x3ff << USB_PMA_TXBD_COUNT_SHIFT)
+#define USB_PMA_TXBD_ADDMSK            (0xffff0000)
+#define USB_PMA_TXBD_COUNTMSK          (0x0000ffff)
+
+/* PMA RX buffer descriptor bit definitions */
+
+#define USB_PMA_RXBD_ADDR_SHIFT        (2)        /* Bits 15-2: RX buffer address */
+#define USB_PMA_RXBD_ADDR_MASK         (0x3fff << USB_PMA_RXBD_ADDR_SHIFT)
+#define USB_PMA_RXBD_COUNT_SHIFT       (16)       /* Bits 25-16: RX byte count */
+#define USB_PMA_RXBD_COUNT_MASK        (0x3ff << USB_PMA_RXBD_COUNT_SHIFT)
+#define USB_PMA_RXBD_NUM_BLOCK_SHIFT   (26)      /* Bits 30-26: Number of blocks */
+#define USB_PMA_RXBD_NUM_BLOCK_MASK    (0x1f << USB_PMA_RXBD_NUM_BLOCK_SHIFT)
+#define USB_PMA_RXBD_BLSIZE            (1 << 31) /* Bit 31: Block size: 0=2bytes, 1=32bytes */
+#define USB_PMA_RXBD_ADDMSK            (0xffff0000)
+
+/* PMA start address (after buffer descriptor table)
+ * BDT size = 8 channels * 8 bytes = 64 bytes, aligned to 64
+ */
+
+#define USB_DRD_PMA_BDT_SIZE           (USB_DRD_NCHANNELS * 8)
+#define USB_DRD_PMA_START_ADDR         (USB_DRD_PMA_BDT_SIZE)
 
 /* Reception buffer address */
 
-#define USB_ADDR_RX_SHIFT              (2)       /* Bits 15:2 ADDRn_RX[15:2]: Reception Buffer Address */
+#define USB_ADDR_RX_SHIFT              (2)       /* Bits 15-2: Reception Buffer Address */
 #define USB_ADDR_RX_MASK               (0x3fff << USB_ADDR_RX_SHIFT)
 
 /* Reception byte count */
 
-#define USB_COUNT_RX_BL_SIZE           (1 << 31) /* Bit 15: BLock SIZE. */
+#define USB_COUNT_RX_BL_SIZE           (1 << 31) /* Bit 31: Block size: 0=2bytes, 1=32bytes */
-#define USB_COUNT_RX_NUM_BLOCK_SHIFT   (26)      /* Bits 14-10: Number of blocks */
+#define USB_COUNT_RX_NUM_BLOCK_SHIFT   (26)      /* Bits 30-26: Number of blocks */
 #define USB_COUNT_RX_NUM_BLOCK_MASK    (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT)
-#define USB_COUNT_RX_SHIFT             (16)       /* Bits 9-0: Reception Byte Count */
+#define USB_COUNT_RX_SHIFT             (16)      /* Bits 25-16: Reception Byte Count */
 #define USB_COUNT_RX_MASK              (0x3ff << USB_COUNT_RX_SHIFT)
 
 #endif /* CONFIG_STM32H5_HAVE_USBFS */

arch/arm/src/stm32h5/stm32_usbdrdhost.h

@@ -0,0 +1,144 @@
+/****************************************************************************
+ * arch/arm/src/stm32h5/stm32_usbdrdhost.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H5_STM32_USBDRDHOST_H
+#define __ARCH_ARM_SRC_STM32H5_STM32_USBDRDHOST_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/usb/usbhost.h>
+#include <stdint.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* Pre-requisites */
+
+#if !defined(CONFIG_STM32H5_USBFS_HOST)
+#  error "CONFIG_STM32H5_USBFS_HOST is required"
+#endif
+
+/* USB DRD Host Driver Configuration */
+
+#ifndef CONFIG_STM32H5_USBDRD_NCHANNELS
+#  define CONFIG_STM32H5_USBDRD_NCHANNELS 8
+#endif
+
+/* Default descriptor buffer size */
+
+#ifndef CONFIG_STM32H5_USBDRD_DESCSIZE
+#  define CONFIG_STM32H5_USBDRD_DESCSIZE 128
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* This structure defines the interface provided by the USB host controller
+ * to the board-level USB host logic.
+ */
+
+struct stm32h5_usbhost_connection_s
+{
+  /* Wait for device connection/disconnection */
+
+  struct usbhost_connection_s *conn;
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32h5_usbhost_initialize
+ *
+ * Description:
+ *   Initialize USB host controller hardware.
+ *
+ *   This function is called very early during system initialization to
+ *   initialize the USB host controller. The USB host controller is then
+ *   made available for use by the USB host driver.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   On success, a pointer to the usbhost_connection_s interface is returned.
+ *   On failure, NULL is returned.
+ *
+ ****************************************************************************/
+
+struct usbhost_connection_s *stm32h5_usbhost_initialize(void);
+
+/****************************************************************************
+ * Name: stm32h5_usbhost_vbusdrive
+ *
+ * Description:
+ *   Enable/disable VBUS power to the connected USB device.
+ *
+ *   The USB host driver calls this function during enumeration to control
+ *   VBUS power delivery to the device. This function should be implemented
+ *   by board-specific code since VBUS control is typically board-specific.
+ *
+ * Input Parameters:
+ *   port   - USB host port number (0-based)
+ *   enable - true: Enable VBUS power
+ *            false: Disable VBUS power
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Called from the USB host driver during enumeration.
+ *
+ ****************************************************************************/
+
+void stm32h5_usbhost_vbusdrive(int port, bool enable);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_STM32H5_STM32_USBDRDHOST_H */

arch/arm/src/stm32h5/stm32h5xx_rcc.c

@@ -580,7 +580,7 @@ static inline void rcc_enableapb2(void)
   regval |= RCC_APB2ENR_SAI2EN;
 #endif
 
-#ifdef CONFIG_STM32H5_USBFS
+#if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_USBFS_HOST)
   /* USB clock enable */
 
   regval |= RCC_APB2ENR_USBEN;

boards/arm/stm32h5/nucleo-h563zi/configs/usbmsc/defconfig

@@ -0,0 +1,57 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="nucleo-h563zi"
+CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CHIP="stm32h5"
+CONFIG_ARCH_CHIP_STM32H563ZI=y
+CONFIG_ARCH_CHIP_STM32H5=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV8M_STACKCHECK_NONE=y
+CONFIG_BOARD_LOOPSPERMSEC=9251
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_ASSERTIONS=y
+CONFIG_DEBUG_FEATURES=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEBUG_USB=y
+CONFIG_DEBUG_USB_ERROR=y
+CONFIG_DEBUG_USB_WARN=y
+CONFIG_FS_FAT=y
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_LINE_MAX=64
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=655360
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_READLINE_CMD_HISTORY=y
+CONFIG_READLINE_TABCOMPLETION=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_LPWORK=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_STACK_COLORATION=y
+CONFIG_STM32H5_USART3=y
+CONFIG_STM32H5_USBFS_HOST=y
+CONFIG_STM32H5_USE_HSE=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_USART3_SERIAL_CONSOLE=y
+CONFIG_USBHOST_MSC=y

boards/arm/stm32h5/nucleo-h563zi/include/board.h

@@ -36,6 +36,13 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+#if defined(CONFIG_STM32H5_USBFS_HOST) && !defined(CONFIG_STM32H5_USE_HSE)
+    #error "This board config requires HSE to use the USB HOST."
+    "HSI48 is not stable enough to use as a host."
+    "To use HSE on the nucleo-H563ZI,"
+    "you need to connect SB3/SB4 and disconnect SB49"
+#endif
+
 /* Clocking *****************************************************************/
 
 /* The Nucleo-H563ZI-Q supports using a HSE crystal (X3). It is shipped with
@@ -82,7 +89,7 @@
                                    STM32_PLLCFG_PLL1Q | \
                                    STM32_PLLCFG_PLL1R)
 
-#define STM32_VC01_FRQ            ((STM32_HSE_FREQUENCY / 5) * 100)
+#define STM32_VCO1_FRQ            ((STM32_HSE_FREQUENCY / 5) * 100)
 #define STM32_PLL1P_FREQUENCY     (STM32_VCO1_FRQ / 2)
 #define STM32_PLL1Q_FREQUENCY     (STM32_VCO1_FRQ / 4)
 #define STM32_PLL1R_FREQUENCY     (STM32_VCO1_FRQ / 2)
@@ -101,6 +108,34 @@
 #define STM32_VCO2_FRQ            ((STM32_HSE_FREQUENCY / 5) * 60)
 #define STM32_PLL2R_FREQUENCY     (STM32_VCO2_FRQ / 4)
 
+#if defined(CONFIG_STM32H5_USBFS_HOST)
+/* PLL3 config: Generate 48 MHz for USB from 25 MHz HSE.
+ * VCO input = 25 MHz / 5 = 5 MHz
+ * VCO output = 5 MHz * 96 = 480 MHz
+ * PLL3Q = 480 MHz / 10 = 48 MHz
+ */
+
+#define STM32_PLLCFG_PLL3CFG      (RCC_PLL3CFGR_PLL3SRC_HSE | \
+                                   RCC_PLL3CFGR_PLL3RGE_4_8M | \
+                                   RCC_PLL3CFGR_PLL3M(5) | \
+                                   RCC_PLL3CFGR_PLL3QEN)
+#define STM32_PLLCFG_PLL3N         RCC_PLL3DIVR_PLL3N(96)  /* VCO 480 MHz */
+#define STM32_PLLCFG_PLL3P         RCC_PLL3DIVR_PLL3P(2)   /* Not used */
+#define STM32_PLLCFG_PLL3Q         RCC_PLL3DIVR_PLL3Q(10)  /* 3Q 48 MHz */
+#define STM32_PLLCFG_PLL3R         RCC_PLL3DIVR_PLL3R(2)   /* Not used */
+#define STM32_PLLCFG_PLL3DIVR     (STM32_PLLCFG_PLL3N | \
+                                   STM32_PLLCFG_PLL3P | \
+                                   STM32_PLLCFG_PLL3Q | \
+                                   STM32_PLLCFG_PLL3R)
+
+#define STM32_VCO3_FRQ            ((STM32_HSE_FREQUENCY / 5) * 96)  /* 480 MHz */
+#define STM32_PLL3Q_FREQUENCY     (STM32_VCO3_FRQ / 10)             /* 48 MHz */
+
+/* Use PLL3Q (48 MHz) for USB - more stable than HSI48 */
+#define STM32H5_CLKUSB_SEL      RCC_CCIPR4_USBSEL_PLL3QCK
+
+#endif /* CONFIG_STM32H5_USBFS_HOST */
+
 #else
 
 #define STM32_BOARD_USEHSI       1

boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt

@@ -48,6 +48,10 @@ if(CONFIG_STM32H5_FDCAN)
   list(APPEND SRCS stm32_can.c)
 endif()
 
+if(CONFIG_STM32H5_USBFS_HOST)
+  list(APPEND SRCS stm32_usb.c)
+endif()
+
 target_sources(board PRIVATE ${SRCS})
 
 set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld")

boards/arm/stm32h5/nucleo-h563zi/src/Makefile

@@ -55,4 +55,8 @@ ifeq ($(CONFIG_STM32H5_PWM),y)
 CSRCS += stm32_pwm.c
 endif
 
+ifeq ($(CONFIG_STM32H5_USBFS_HOST),y)
+CSRCS += stm32_usb.c
+endif
+
 include $(TOPDIR)/boards/Board.mk

boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h

@@ -157,5 +157,9 @@ int stm32_can_setup(uint8_t port);
 int stm32_pwm_setup(void);
 #endif
 
+#ifdef CONFIG_USBHOST
+int stm32_usbhost_initialize(void);
+#endif
+
 #endif /* __ASSEMBLY__ */
 #endif /* __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H */

boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c

@@ -149,6 +149,15 @@ int stm32_bringup(void)
     }
 #endif
 
+#ifdef CONFIG_USBHOST
+  ret = stm32_usbhost_initialize();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret);
+      return ret;
+    }
+#endif
+
   UNUSED(ret);
   return OK;
 }

boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c

@@ -0,0 +1,226 @@
+/****************************************************************************
+ * boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <sched.h>
+#include <errno.h>
+#include <assert.h>
+#include <nuttx/debug.h>
+
+#include <nuttx/kthread.h>
+#include <nuttx/usb/usbhost.h>
+#include <nuttx/usb/usbdev_trace.h>
+
+#include "arm_internal.h"
+#include "stm32.h"
+#include "stm32_usbdrdhost.h"
+
+#ifdef CONFIG_STM32H5_USBFS_HOST
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if !defined(CONFIG_USBHOST)
+#  warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST"
+#endif
+
+#ifndef CONFIG_USBHOST_DEFPRIO
+#  define CONFIG_USBHOST_DEFPRIO 100
+#endif
+
+#ifndef CONFIG_USBHOST_STACKSIZE
+#  define CONFIG_USBHOST_STACKSIZE 2048
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+static struct usbhost_connection_s *g_usbconn;
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: usbhost_waiter
+ *
+ * Description:
+ *   Wait for USB devices to be connected.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+static int usbhost_waiter(int argc, char *argv[])
+{
+  struct usbhost_hubport_s *hport;
+
+  uinfo("Running\n");
+  for (; ; )
+    {
+      /* Wait for the device to change state */
+
+      DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport));
+      uinfo("%s\n", hport->connected ? "connected" : "disconnected");
+
+      /* Did we just become connected? */
+
+      if (hport->connected)
+        {
+          /* Yes.. enumerate the newly connected device */
+
+          CONN_ENUMERATE(g_usbconn, hport);
+        }
+    }
+
+  /* Keep the compiler from complaining */
+
+  return 0;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_usbinitialize
+ *
+ * Description:
+ *   Called from stm32_usbinitialize very early in initialization to setup
+ *   USB-related GPIO pins for the STM32F411 board.
+ *
+ ****************************************************************************/
+
+void stm32_usbinitialize(void)
+{
+  /* The OTG FS has an internal soft pull-up.
+   * No GPIO configuration is required
+   */
+}
+
+/****************************************************************************
+ * Name: stm32_usbhost_initialize
+ *
+ * Description:
+ *   Called at application startup time to initialize the USB host
+ *   functionality.
+ *   This function will start a thread that will monitor for device
+ *   connection/disconnection events.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+int stm32_usbhost_initialize(void)
+{
+  int ret;
+
+  /* First, register all of the class drivers needed to support the drivers
+   * that we care about:
+   */
+
+  uinfo("Register class drivers\n");
+
+#ifdef CONFIG_USBHOST_MSC
+  /* Register the USB mass storage class class */
+
+  ret = usbhost_msc_initialize();
+  if (ret != OK)
+    {
+      uerr("ERROR: Failed to register the mass storage class: %d\n", ret);
+    }
+#endif
+
+  /* Then get an instance of the USB host interface */
+
+  uinfo("Initialize USB host\n");
+  g_usbconn = stm32h5_usbhost_initialize();
+  if (g_usbconn)
+    {
+      /* Start a thread to handle device connection. */
+
+      uinfo("Start usbhost_waiter\n");
+
+      ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO,
+                           CONFIG_USBHOST_STACKSIZE,
+                           usbhost_waiter, NULL);
+      return ret < 0 ? -ENOEXEC : OK;
+    }
+
+  return -ENODEV;
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_usbhost_vbusdrive
+ *
+ * Description:
+ *   Enable/disable driving of VBUS 5V output.  This function must be
+ *   provided be each platform that implements the STM32 OTG FS host
+ *   interface
+ *
+ *   "On-chip 5 V VBUS generation is not supported. For this reason, a
+ *    charge pump or, if 5 V are available on the application board, a
+ *    basic power switch, must be added externally to drive the 5 V VBUS
+ *    line. The external charge pump can be driven by any GPIO output.
+ *    When the application decides to power on VBUS using the chosen GPIO,
+ *    it must also set the port power bit in the host port control and
+ *    status register (PPWR bit in OTG_FS_HPRT).
+ *
+ *   "The application uses this field to control power to this port,
+ *    and the core clears this bit on an overcurrent condition."
+ *
+ * Input Parameters:
+ *   iface - For future growth to handle multiple USB host interface.
+ *           Should be zero.
+ *   enable - true: enable VBUS power; false: disable VBUS power
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+void stm32h5_usbhost_vbusdrive(int port, bool enable)
+{
+  /* The Nucleo-h563zi doesn't have hardware for a vbus drive.
+   * Instead to get host working, you need to put an extra jumper
+   * on the "PWR SEL" to jump "STLK" and "USB USER".
+   * This effectively supplies 5V power form the STLink to the USB device.
+   * The power output is limited so only relatively low power
+   * devices can work.
+   */
+}
+#endif
+
+#endif /* CONFIG_STM32H5_USBFS_HOST */