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arch/intel64: add cache support
Add dcache and icache support for intel64 Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
This commit is contained in:
p-szafonimateusz
committed by
Petro Karashchenko
Petro Karashchenko
parent
30226901c0
commit
530f5cd324
@@ -30,6 +30,8 @@ config ARCH_INTEL64
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select ARCH_HAVE_SSE41
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select ARCH_HAVE_SSE42
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select ARCH_HAVE_SSE4A
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select ARCH_ICACHE
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select ARCH_DCACHE
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---help---
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Intel x86_64 architecture
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@@ -135,14 +135,31 @@
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/* CPUID Leaf Definitions */
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#define X86_64_CPUID_CAP 0x01
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# define X86_64_CPUID_01_SSE3 (1 << 0)
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# define X86_64_CPUID_01_PCID (1 << 17)
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# define X86_64_CPUID_01_X2APIC (1 << 21)
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# define X86_64_CPUID_01_TSCDEA (1 << 24)
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# define X86_64_CPUID_01_XSAVE (1 << 26)
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# define X86_64_CPUID_01_RDRAND (1 << 30)
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#define X86_64_CPUID_TSC 0x15
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#define X86_64_CPUID_VENDOR 0x00
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#define X86_64_CPUID_CAP 0x01
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# define X86_64_CPUID_01_SSE3 (1 << 0)
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# define X86_64_CPUID_01_SSSE3 (1 << 9)
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# define X86_64_CPUID_01_PCID (1 << 17)
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# define X86_64_CPUID_01_SSE41 (1 << 19)
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# define X86_64_CPUID_01_SSE42 (1 << 20)
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# define X86_64_CPUID_01_X2APIC (1 << 21)
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# define X86_64_CPUID_01_TSCDEA (1 << 24)
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# define X86_64_CPUID_01_XSAVE (1 << 26)
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# define X86_64_CPUID_01_RDRAND (1 << 30)
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# define X86_64_CPUID_01_APICID(ebx) ((ebx) >> 24)
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#define X86_64_CPUID_EXTCAP 0x07
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# define X86_64_CPUID_07_AVX2 (1 << 5)
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# define X86_64_CPUID_07_AVX512F (1 << 16)
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# define X86_64_CPUID_07_AVX512DQ (1 << 17)
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# define X86_64_CPUID_07_SMAP (1 << 20)
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# define X86_64_CPUID_07_AVX512IFMA (1 << 21)
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# define X86_64_CPUID_07_CLWB (1 << 24)
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# define X86_64_CPUID_07_AVX512PF (1 << 26)
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# define X86_64_CPUID_07_AVX512ER (1 << 27)
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# define X86_64_CPUID_07_AVX512CD (1 << 28)
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# define X86_64_CPUID_07_AVX512BW (1 << 30)
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# define X86_64_CPUID_07_AVX512VL (1 << 31)
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#define X86_64_CPUID_TSC 0x15
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/* MSR Definitions */
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@@ -38,6 +38,7 @@ set(SRCS
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intel64_usestack.c
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intel64_systemreset.c
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intel64_freq.c
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intel64_cache.c
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intel64_start.c
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intel64_handlers.c
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intel64_idle.c
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@@ -21,6 +21,34 @@ endchoice # "Intel64 Chip Selection"
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config ARCH_INTEL64_HAVE_TSC
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bool
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config ARCH_INTEL64_CACHE_LINESIZE
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int "Cache line size (hardcoded)"
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depends on ARCH_DCACHE || ARCH_ICACHE
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default 64
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---help---
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Cache line size. If set to 0, we read the value from CPUID,
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(Probably) all new Intel CPUs have this value equal to 64.
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config ARCH_INTEL64_DCACHE_SIZE
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int "Data cache line size (L1d)"
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depends on ARCH_DCACHE
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default 0
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---help---
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Data cache line size (L1d). If set to 0, we read the value from CPUID.
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config ARCH_INTEL64_ICACHE_SIZE
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int "Instruction cache line size (L1i)"
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depends on ARCH_ICACHE
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default 0
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---help---
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Instruction cache line size (L1i). If set to 0, we read the value from CPUID.
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config ARCH_INTEL64_HAVE_CLWB
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bool "CLWB support"
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default n
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---help---
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Select to enable the use of CLWB to write back cache line
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choice
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prompt "System Timer Source"
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default ARCH_INTEL64_TSC_DEADLINE
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@@ -25,7 +25,7 @@ CMN_CSRCS += intel64_map_region.c intel64_regdump.c intel64_releasestack.c
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CMN_CSRCS += intel64_rtc.c intel64_restore_auxstate.c intel64_savestate.c
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CMN_CSRCS += intel64_stackframe.c intel64_schedulesigaction.c
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CMN_CSRCS += intel64_sigdeliver.c intel64_usestack.c x86_64_tcbinfo.c
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CMN_CSRCS += intel64_systemreset.c intel64_freq.c
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CMN_CSRCS += intel64_systemreset.c intel64_freq.c intel64_cache.c
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# Required Intel64 files
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File diff suppressed because it is too large
Load Diff
@@ -56,6 +56,7 @@
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void x86_64_check_and_enable_capability(void)
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{
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unsigned long ebx;
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unsigned long ecx;
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unsigned long require;
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@@ -80,15 +81,33 @@ void x86_64_check_and_enable_capability(void)
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#endif
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asm volatile("cpuid" : "=c" (ecx) : "a" (X86_64_CPUID_CAP)
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: "rbx", "rdx", "memory");
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: "rdx", "memory");
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/* Check x2APIC availability */
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/* Check features availability from ECX */
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if ((ecx & require) != require)
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{
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goto err;
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}
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/* Extended features */
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require = 0;
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#ifdef CONFIG_ARCH_INTEL64_HAVE_CLWB
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require |= X86_64_CPUID_07_CLWB;
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#endif
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asm volatile("cpuid" : "=b" (ebx) : "a" (X86_64_CPUID_EXTCAP), "c" (0)
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: "rdx", "memory");
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/* Check features availability */
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if ((ebx & require) != require)
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{
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goto err;
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}
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#ifdef CONFIG_ARCH_INTEL64_HAVE_XSAVE
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__enable_sse_avx();
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#endif
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@@ -97,6 +116,11 @@ void x86_64_check_and_enable_capability(void)
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__enable_pcid();
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#endif
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/* Enable I- and D-Caches */
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up_enable_icache();
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up_enable_dcache();
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return;
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err:
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