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Added Support for more TI Tiva Microcontrollers:

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* TM4C123GH6PZ (100 pin version of TM4C123GH6PM)
* TM4C123GH6PGE (144 pin version of TM4C123GH6PM)
* TM4C129ENCPDT (TM4C1294 with Crypto hardware added, TQFP package)
* TM4C129ENCZAD (TM4C1294 with Crypto hardware added, BGA package)
This commit is contained in:
Frank-Christian Kruegel
2020-10-29 15:22:04 +01:00
committed by Xiang Xiao
parent c90697f193
commit 52097a4345
6 changed files with 1967 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/include/tiva/chip.h
+53 -7
View File
@@ -200,9 +200,7 @@
# define TIVA_NAES 0 /* No AES module */
# define TIVA_NDES 0 /* No DES module */
# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PGE) || \
defined(CONFIG_ARCH_CHIP_TM4C123GH6PZ) || \
defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
# undef LM3S /* Not LM3S family */
# undef LM4F /* Not LM4F family */
# define TM4C 1 /* TM4C family */
@@ -250,6 +248,54 @@
# define TIVA_NAES 0 /* No AES module */
# define TIVA_NDES 0 /* No DES module */
# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PZ)
# undef LM3S /* Not LM3S family */
# undef LM4F /* Not LM4F family */
# define TM4C 1 /* TM4C family */
# undef SIMPLELINK /* Not SimpleLink family */
# define TIVA_NTIMERS 6 /* Six 16/32-bit timers */
# define TIVA_NWIDETIMERS 6 /* Six 32/64-bit timers */
# define TIVA_NWDT 2 /* Two watchdog timers */
# define TIVA_NETHCONTROLLERS 0 /* No Ethernet controller */
# define TIVA_NLCD 0 /* No LCD controller */
# define TIVA_NSSI 4 /* Four SSI module */
# define TIVA_NUARTS 8 /* Eight UART modules */
# define TIVA_NI2C 6 /* Six I2C modules */
# define TIVA_NADC 2 /* Two ADC modules */
# define TIVA_NPWM 2 /* Two PWM generator modules */
# define TIVA_NQEI 2 /* Two quadrature encoders */
# define TIVA_NPORTS 10 /* Ten Ports (GPIOA-K) */
# define TIVA_NCANCONTROLLER 2 /* Two CAN controllers */
# define TIVA_NUSBOTGFS 1 /* One USB 2.0 OTG FS */
# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
# define TIVA_NCRC 0 /* No CRC module */
# define TIVA_NAES 0 /* No AES module */
# define TIVA_NDES 0 /* No DES module */
# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PGE)
# undef LM3S /* Not LM3S family */
# undef LM4F /* Not LM4F family */
# define TM4C 1 /* TM4C family */
# undef SIMPLELINK /* Not SimpleLink family */
# define TIVA_NTIMERS 6 /* Six 16/32-bit timers */
# define TIVA_NWIDETIMERS 6 /* Six 32/64-bit timers */
# define TIVA_NWDT 2 /* Two watchdog timers */
# define TIVA_NETHCONTROLLERS 0 /* No Ethernet controller */
# define TIVA_NLCD 0 /* No LCD controller */
# define TIVA_NSSI 4 /* Four SSI module */
# define TIVA_NUARTS 8 /* Eight UART modules */
# define TIVA_NI2C 6 /* Six I2C modules */
# define TIVA_NADC 2 /* Two ADC modules */
# define TIVA_NPWM 2 /* Two PWM generator modules */
# define TIVA_NQEI 2 /* Two quadrature encoders */
# define TIVA_NPORTS 14 /* Fourteen Ports (GPIOA-P) */
# define TIVA_NCANCONTROLLER 2 /* Two CAN controllers */
# define TIVA_NUSBOTGFS 1 /* One USB 2.0 OTG FS */
# define TIVA_NUSBOTGHS 0 /* No USB 2.0 OTG HS */
# define TIVA_NCRC 0 /* No CRC module */
# define TIVA_NAES 0 /* No AES module */
# define TIVA_NDES 0 /* No DES module */
# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_TM4C123AH6PM)
# undef LM3S /* Not LM3S family */
# undef LM4F /* Not LM4F family */
@@ -319,10 +365,10 @@
# define TIVA_NUSBOTGFS 0 /* No USB 2.0 OTG FS */
# define TIVA_NUSBOTGHS 1 /* One USB 2.0 OTG HS */
# define TIVA_NCRC 1 /* One CRC module */
# define TIVA_NAES 0 /* No AES module */
# define TIVA_NDES 0 /* No DES module */
# define TIVA_NHASH 0 /* No SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_TM4C129XNCZAD)
# define TIVA_NAES 1 /* One AES module */
# define TIVA_NDES 1 /* One DES module */
# define TIVA_NHASH 1 /* One SHA1/MD5 hash module */
#elif defined(CONFIG_ARCH_CHIP_TM4C129XNCZAD) || defined(CONFIG_ARCH_CHIP_TM4C129ENCZAD)
# undef LM3S /* Not LM3S family */
# undef LM4F /* Not LM4F family */
# define TM4C 1 /* TM4C family */
arch/arm/include/tiva/tm4c_irq.h
+443
View File
@@ -395,6 +395,320 @@
# define NR_IRQS (155) /* (Really fewer because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PZ)
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define TIVA_IRQ_PWM0_FAULT (25) /* Vector 25: PWM0 Fault */
# define TIVA_IRQ_PWM0_GEN0 (26) /* Vector 26: PWM0 Generator 0 */
# define TIVA_IRQ_PWM0_GEN1 (27) /* Vector 27: PWM0 Generator 1 */
# define TIVA_IRQ_PWM0_GEN2 (28) /* Vector 28: PWM0 Generator 2 */
# define TIVA_IRQ_QEI0 (29) /* Vector 29: QEI0 */
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timers 0 and 1 */
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: 16/32-Bit Timer 0 A */
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: 16/32-Bit Timer 0 B */
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: 16/32-Bit Timer 1 A */
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: 16/32-Bit Timer 1 B */
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: 16/32-Bit Timer 2 A */
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: 16/32-Bit Timer 2 B */
# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define TIVA_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define TIVA_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 2 */
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH and EEPROM Control */
# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define TIVA_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define TIVA_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */
# define TIVA_IRQ_UART2 (49) /* Vector 49: UART 2 */
# define TIVA_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
# define TIVA_IRQ_TIMER3A (51) /* Vector 51: 16/32-Bit Timer 3 A */
# define TIVA_IRQ_TIMER3B (52) /* Vector 52: 16/32-Bit Timer 3 B */
# define TIVA_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define TIVA_IRQ_QEI1 (54) /* Vector 54: QEI1 */
# define TIVA_IRQ_CAN0 (55) /* Vector 55: CAN 0 */
# define TIVA_IRQ_CAN1 (56) /* Vector 56: CAN 1 */
# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
# define TIVA_RESERVED_58 (58) /* Vector 58: Reserved */
# define TIVA_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
# define TIVA_IRQ_USB (60) /* Vector 60: USB */
# define TIVA_IRQ_PWM0_GEN3 (61) /* Vector 61: PWM0 Generator 3 */
# define TIVA_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */
# define TIVA_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
# define TIVA_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */
# define TIVA_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */
# define TIVA_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */
# define TIVA_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */
# define TIVA_RESERVED_68 (68) /* Vector 68: Reserved */
# define TIVA_RESERVED_69 (69) /* Vector 69: Reserved */
# define TIVA_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */
# define TIVA_IRQ_GPIOK (71) /* Vector 71: GPIO Port K */
# define TIVA_RESERVED_72 (72) /* Vector 72: Reserved */
# define TIVA_IRQ_SSI2 (73) /* Vector 73: SSI 2 */
# define TIVA_IRQ_SSI3 (74) /* Vector 74: SSI 3 */
# define TIVA_IRQ_UART3 (75) /* Vector 75: UART 3 */
# define TIVA_IRQ_UART4 (76) /* Vector 76: UART 4 */
# define TIVA_IRQ_UART5 (77) /* Vector 77: UART 5 */
# define TIVA_IRQ_UART6 (78) /* Vector 78: UART 6 */
# define TIVA_IRQ_UART7 (79) /* Vector 79: UART 7 */
# define TIVA_RESERVED_80 (80) /* Vector 80: Reserved */
# define TIVA_RESERVED_81 (81) /* Vector 81: Reserved */
# define TIVA_RESERVED_82 (82) /* Vector 82: Reserved */
# define TIVA_RESERVED_83 (83) /* Vector 83: Reserved */
# define TIVA_IRQ_I2C2 (84) /* Vector 84: I2C 2 */
# define TIVA_IRQ_I2C3 (85) /* Vector 85: I2C 3 */
# define TIVA_IRQ_TIMER4A (86) /* Vector 86: 16/32-Bit Timer 4 A */
# define TIVA_IRQ_TIMER4B (87) /* Vector 87: 16/32-Bit Timer 4 B */
# define TIVA_RESERVED_88 (88) /* Vector 88: Reserved */
# define TIVA_RESERVED_89 (89) /* Vector 89: Reserved */
# define TIVA_RESERVED_90 (90) /* Vector 90: Reserved */
# define TIVA_RESERVED_91 (91) /* Vector 91: Reserved */
# define TIVA_RESERVED_92 (92) /* Vector 92: Reserved */
# define TIVA_RESERVED_93 (93) /* Vector 93: Reserved */
# define TIVA_RESERVED_94 (94) /* Vector 94: Reserved */
# define TIVA_RESERVED_95 (95) /* Vector 95: Reserved */
# define TIVA_RESERVED_96 (96) /* Vector 96: Reserved */
# define TIVA_RESERVED_97 (97) /* Vector 97: Reserved */
# define TIVA_RESERVED_98 (98) /* Vector 98: Reserved */
# define TIVA_RESERVED_99 (99) /* Vector 99: Reserved */
# define TIVA_RESERVED_100 (100) /* Vector 100: Reserved */
# define TIVA_RESERVED_101 (101) /* Vector 101: Reserved */
# define TIVA_RESERVED_102 (102) /* Vector 102: Reserved */
# define TIVA_RESERVED_103 (103) /* Vector 103: Reserved */
# define TIVA_RESERVED_104 (104) /* Vector 104: Reserved */
# define TIVA_RESERVED_105 (105) /* Vector 105: Reserved */
# define TIVA_RESERVED_106 (106) /* Vector 106: Reserved */
# define TIVA_RESERVED_107 (107) /* Vector 107: Reserved */
# define TIVA_IRQ_TIMER5A (108) /* Vector 108: 16/32-Bit Timer 5 A */
# define TIVA_IRQ_TIMER5B (109) /* Vector 109: 16/32-Bit Timer 5 B */
# define TIVA_IRQ_WTIMER0A (110) /* Vector 110: 32/64-Bit Timer 0 A */
# define TIVA_IRQ_WTIMER0B (111) /* Vector 111: 32/64-Bit Timer 0 B */
# define TIVA_IRQ_WTIMER1A (112) /* Vector 112: 32/64-Bit Timer 1 A */
# define TIVA_IRQ_WTIMER1B (113) /* Vector 113: 32/64-Bit Timer 1 B */
# define TIVA_IRQ_WTIMER2A (114) /* Vector 114: 32/64-Bit Timer 2 A */
# define TIVA_IRQ_WTIMER2B (115) /* Vector 115: 32/64-Bit Timer 2 B */
# define TIVA_IRQ_WTIMER3A (116) /* Vector 116: 32/64-Bit Timer 3 A */
# define TIVA_IRQ_WTIMER3B (117) /* Vector 117: 32/64-Bit Timer 3 B */
# define TIVA_IRQ_WTIMER4A (118) /* Vector 118: 32/64-Bit Timer 4 A */
# define TIVA_IRQ_WTIMER4B (119) /* Vector 119: 32/64-Bit Timer 4 B */
# define TIVA_IRQ_WTIMER5A (120) /* Vector 120: 32/64-Bit Timer 5 A */
# define TIVA_IRQ_WTIMER5B (121) /* Vector 121: 32/64-Bit Timer 5 B */
# define TIVA_IRQ_SYSTEM (122) /* Vector 122: System Exception (imprecise) */
# define TIVA_RESERVED_123 (123) /* Vector 123: Reserved */
# define TIVA_RESERVED_124 (124) /* Vector 124: Reserved */
# define TIVA_IRQ_I2C4 (125) /* Vector 125: I2C 4 */
# define TIVA_IRQ_I2C5 (126) /* Vector 126: I2C 5 */
# define TIVA_RESERVED_127 (127) /* Vector 127: Reserved */
# define TIVA_RESERVED_128 (128) /* Vector 128: Reserved */
# define TIVA_RESERVED_129 (129) /* Vector 129: Reserved */
# define TIVA_RESERVED_130 (130) /* Vector 130: Reserved */
# define TIVA_RESERVED_131 (131) /* Vector 131: Reserved */
# define TIVA_RESERVED_132 (132) /* Vector 132: Reserved */
# define TIVA_RESERVED_133 (133) /* Vector 133: Reserved */
# define TIVA_RESERVED_134 (134) /* Vector 134: Reserved */
# define TIVA_RESERVED_135 (135) /* Vector 135: Reserved */
# define TIVA_RESERVED_136 (136) /* Vector 136: Reserved */
# define TIVA_RESERVED_137 (137) /* Vector 137: Reserved */
# define TIVA_RESERVED_138 (138) /* Vector 138: Reserved */
# define TIVA_RESERVED_139 (139) /* Vector 139: Reserved */
# define TIVA_RESERVED_140 (140) /* Vector 140: Reserved */
# define TIVA_RESERVED_141 (141) /* Vector 141: Reserved */
# define TIVA_RESERVED_142 (142) /* Vector 142: Reserved */
# define TIVA_RESERVED_143 (143) /* Vector 143: Reserved */
# define TIVA_RESERVED_144 (144) /* Vector 144: Reserved */
# define TIVA_RESERVED_145 (145) /* Vector 145: Reserved */
# define TIVA_RESERVED_146 (146) /* Vector 146: Reserved */
# define TIVA_RESERVED_147 (147) /* Vector 147: Reserved */
# define TIVA_RESERVED_148 (148) /* Vector 148: Reserved */
# define TIVA_RESERVED_149 (149) /* Vector 149: Reserved */
# define TIVA_IRQ_PWM1_GEN0 (150) /* Vector 150: PWM1 Generator 0 */
# define TIVA_IRQ_PWM1_GEN1 (151) /* Vector 151: PWM1 Generator 1 */
# define TIVA_IRQ_PWM1_GEN2 (152) /* Vector 152: PWM1 Generator 2 */
# define TIVA_IRQ_PWM1_GEN3 (153) /* Vector 153: PWM1 Generator 3 */
# define TIVA_IRQ_PWM1_FAULT (154) /* Vector 154: PWM1 Fault */
# define NR_IRQS (155) /* (Really fewer because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PGE)
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define TIVA_IRQ_PWM0_FAULT (25) /* Vector 25: PWM0 Fault */
# define TIVA_IRQ_PWM0_GEN0 (26) /* Vector 26: PWM0 Generator 0 */
# define TIVA_IRQ_PWM0_GEN1 (27) /* Vector 27: PWM0 Generator 1 */
# define TIVA_IRQ_PWM0_GEN2 (28) /* Vector 28: PWM0 Generator 2 */
# define TIVA_IRQ_QEI0 (29) /* Vector 29: QEI0 */
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timers 0 and 1 */
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: 16/32-Bit Timer 0 A */
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: 16/32-Bit Timer 0 B */
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: 16/32-Bit Timer 1 A */
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: 16/32-Bit Timer 1 B */
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: 16/32-Bit Timer 2 A */
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: 16/32-Bit Timer 2 B */
# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define TIVA_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define TIVA_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 2 */
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH and EEPROM Control */
# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define TIVA_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define TIVA_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */
# define TIVA_IRQ_UART2 (49) /* Vector 49: UART 2 */
# define TIVA_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
# define TIVA_IRQ_TIMER3A (51) /* Vector 51: 16/32-Bit Timer 3 A */
# define TIVA_IRQ_TIMER3B (52) /* Vector 52: 16/32-Bit Timer 3 B */
# define TIVA_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define TIVA_IRQ_QEI1 (54) /* Vector 54: QEI1 */
# define TIVA_IRQ_CAN0 (55) /* Vector 55: CAN 0 */
# define TIVA_IRQ_CAN1 (56) /* Vector 56: CAN 1 */
# define TIVA_RESERVED_57 (57) /* Vector 57: Reserved */
# define TIVA_RESERVED_58 (58) /* Vector 58: Reserved */
# define TIVA_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
# define TIVA_IRQ_USB (60) /* Vector 60: USB */
# define TIVA_IRQ_PWM0_GEN3 (61) /* Vector 61: PWM0 Generator 3 */
# define TIVA_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */
# define TIVA_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
# define TIVA_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */
# define TIVA_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */
# define TIVA_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */
# define TIVA_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */
# define TIVA_RESERVED_68 (68) /* Vector 68: Reserved */
# define TIVA_RESERVED_69 (69) /* Vector 69: Reserved */
# define TIVA_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */
# define TIVA_IRQ_GPIOK (71) /* Vector 71: GPIO Port K */
# define TIVA_IRQ_GPIOL (72) /* Vector 72: GPIO Port L */
# define TIVA_IRQ_SSI2 (73) /* Vector 73: SSI 2 */
# define TIVA_IRQ_SSI3 (74) /* Vector 74: SSI 3 */
# define TIVA_IRQ_UART3 (75) /* Vector 75: UART 3 */
# define TIVA_IRQ_UART4 (76) /* Vector 76: UART 4 */
# define TIVA_IRQ_UART5 (77) /* Vector 77: UART 5 */
# define TIVA_IRQ_UART6 (78) /* Vector 78: UART 6 */
# define TIVA_IRQ_UART7 (79) /* Vector 79: UART 7 */
# define TIVA_RESERVED_80 (80) /* Vector 80: Reserved */
# define TIVA_RESERVED_81 (81) /* Vector 81: Reserved */
# define TIVA_RESERVED_82 (82) /* Vector 82: Reserved */
# define TIVA_RESERVED_83 (83) /* Vector 83: Reserved */
# define TIVA_IRQ_I2C2 (84) /* Vector 84: I2C 2 */
# define TIVA_IRQ_I2C3 (85) /* Vector 85: I2C 3 */
# define TIVA_IRQ_TIMER4A (86) /* Vector 86: 16/32-Bit Timer 4 A */
# define TIVA_IRQ_TIMER4B (87) /* Vector 87: 16/32-Bit Timer 4 B */
# define TIVA_RESERVED_88 (88) /* Vector 88: Reserved */
# define TIVA_RESERVED_89 (89) /* Vector 89: Reserved */
# define TIVA_RESERVED_90 (90) /* Vector 90: Reserved */
# define TIVA_RESERVED_91 (91) /* Vector 91: Reserved */
# define TIVA_RESERVED_92 (92) /* Vector 92: Reserved */
# define TIVA_RESERVED_93 (93) /* Vector 93: Reserved */
# define TIVA_RESERVED_94 (94) /* Vector 94: Reserved */
# define TIVA_RESERVED_95 (95) /* Vector 95: Reserved */
# define TIVA_RESERVED_96 (96) /* Vector 96: Reserved */
# define TIVA_RESERVED_97 (97) /* Vector 97: Reserved */
# define TIVA_RESERVED_98 (98) /* Vector 98: Reserved */
# define TIVA_RESERVED_99 (99) /* Vector 99: Reserved */
# define TIVA_RESERVED_100 (100) /* Vector 100: Reserved */
# define TIVA_RESERVED_101 (101) /* Vector 101: Reserved */
# define TIVA_RESERVED_102 (102) /* Vector 102: Reserved */
# define TIVA_RESERVED_103 (103) /* Vector 103: Reserved */
# define TIVA_RESERVED_104 (104) /* Vector 104: Reserved */
# define TIVA_RESERVED_105 (105) /* Vector 105: Reserved */
# define TIVA_RESERVED_106 (106) /* Vector 106: Reserved */
# define TIVA_RESERVED_107 (107) /* Vector 107: Reserved */
# define TIVA_IRQ_TIMER5A (108) /* Vector 108: 16/32-Bit Timer 5 A */
# define TIVA_IRQ_TIMER5B (109) /* Vector 109: 16/32-Bit Timer 5 B */
# define TIVA_IRQ_WTIMER0A (110) /* Vector 110: 32/64-Bit Timer 0 A */
# define TIVA_IRQ_WTIMER0B (111) /* Vector 111: 32/64-Bit Timer 0 B */
# define TIVA_IRQ_WTIMER1A (112) /* Vector 112: 32/64-Bit Timer 1 A */
# define TIVA_IRQ_WTIMER1B (113) /* Vector 113: 32/64-Bit Timer 1 B */
# define TIVA_IRQ_WTIMER2A (114) /* Vector 114: 32/64-Bit Timer 2 A */
# define TIVA_IRQ_WTIMER2B (115) /* Vector 115: 32/64-Bit Timer 2 B */
# define TIVA_IRQ_WTIMER3A (116) /* Vector 116: 32/64-Bit Timer 3 A */
# define TIVA_IRQ_WTIMER3B (117) /* Vector 117: 32/64-Bit Timer 3 B */
# define TIVA_IRQ_WTIMER4A (118) /* Vector 118: 32/64-Bit Timer 4 A */
# define TIVA_IRQ_WTIMER4B (119) /* Vector 119: 32/64-Bit Timer 4 B */
# define TIVA_IRQ_WTIMER5A (120) /* Vector 120: 32/64-Bit Timer 5 A */
# define TIVA_IRQ_WTIMER5B (121) /* Vector 121: 32/64-Bit Timer 5 B */
# define TIVA_IRQ_SYSTEM (122) /* Vector 122: System Exception (imprecise) */
# define TIVA_RESERVED_123 (123) /* Vector 123: Reserved */
# define TIVA_RESERVED_124 (124) /* Vector 124: Reserved */
# define TIVA_IRQ_I2C4 (125) /* Vector 125: I2C 4 */
# define TIVA_IRQ_I2C5 (126) /* Vector 126: I2C 5 */
# define TIVA_IRQ_GPIOM (127) /* Vector 127: GPIO Port M */
# define TIVA_IRQ_GPION (128) /* Vector 128: GPIO Port N */
# define TIVA_RESERVED_129 (129) /* Vector 129: Reserved */
# define TIVA_RESERVED_130 (130) /* Vector 130: Reserved */
# define TIVA_RESERVED_131 (131) /* Vector 131: Reserved */
# define TIVA_IRQ_GPIOP (132) /* Vector 132: GPIO Port P (Summary or P0) */
# define TIVA_IRQ_GPIOP1 (133) /* Vector 133: GPIO Port P1 */
# define TIVA_IRQ_GPIOP2 (134) /* Vector 134: GPIO Port P2 */
# define TIVA_IRQ_GPIOP3 (135) /* Vector 135: GPIO Port P3 */
# define TIVA_IRQ_GPIOP4 (136) /* Vector 136: GPIO Port P4 */
# define TIVA_IRQ_GPIOP5 (137) /* Vector 137: GPIO Port P5 */
# define TIVA_IRQ_GPIOP6 (138) /* Vector 138: GPIO Port P6 */
# define TIVA_IRQ_GPIOP7 (139) /* Vector 139: GPIO Port P7 */
# define TIVA_RESERVED_140 (140) /* Vector 140: Reserved */
# define TIVA_RESERVED_141 (141) /* Vector 141: Reserved */
# define TIVA_RESERVED_142 (142) /* Vector 142: Reserved */
# define TIVA_RESERVED_143 (143) /* Vector 143: Reserved */
# define TIVA_RESERVED_144 (144) /* Vector 144: Reserved */
# define TIVA_RESERVED_145 (145) /* Vector 145: Reserved */
# define TIVA_RESERVED_146 (146) /* Vector 146: Reserved */
# define TIVA_RESERVED_147 (147) /* Vector 147: Reserved */
# define TIVA_RESERVED_148 (148) /* Vector 148: Reserved */
# define TIVA_RESERVED_149 (149) /* Vector 149: Reserved */
# define TIVA_IRQ_PWM1_GEN0 (150) /* Vector 150: PWM1 Generator 0 */
# define TIVA_IRQ_PWM1_GEN1 (151) /* Vector 151: PWM1 Generator 1 */
# define TIVA_IRQ_PWM1_GEN2 (152) /* Vector 152: PWM1 Generator 2 */
# define TIVA_IRQ_PWM1_GEN3 (153) /* Vector 153: PWM1 Generator 3 */
# define TIVA_IRQ_PWM1_FAULT (154) /* Vector 154: PWM1 Fault */
# define NR_IRQS (155) /* (Really fewer because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_TM4C123AH6PM)
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
@@ -939,6 +1253,135 @@
# define NR_IRQS (130) /* (Really fewer because of reserved vectors) */
#elif defined(CONFIG_ARCH_CHIP_TM4C129ENCZAD)
# define TIVA_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
# define TIVA_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
# define TIVA_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
# define TIVA_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
# define TIVA_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
# define TIVA_IRQ_UART0 (21) /* Vector 21: UART 0 */
# define TIVA_IRQ_UART1 (22) /* Vector 22: UART 1 */
# define TIVA_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
# define TIVA_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
# define TIVA_IRQ_PWM0_FAULT (25) /* Vector 25: PWM0 Fault */
# define TIVA_IRQ_PWM0_GEN0 (26) /* Vector 26: PWM0 Generator 0 */
# define TIVA_IRQ_PWM0_GEN1 (27) /* Vector 27: PWM0 Generator 1 */
# define TIVA_IRQ_PWM0_GEN2 (28) /* Vector 28: PWM0 Generator 2 */
# define TIVA_IRQ_QEI0 (29) /* Vector 29: QEI0 */
# define TIVA_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
# define TIVA_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
# define TIVA_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
# define TIVA_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
# define TIVA_IRQ_WDOG (34) /* Vector 34: Watchdog Timers 0 and 1 */
# define TIVA_IRQ_TIMER0A (35) /* Vector 35: 16/32-Bit Timer 0 A */
# define TIVA_IRQ_TIMER0B (36) /* Vector 36: 16/32-Bit Timer 0 B */
# define TIVA_IRQ_TIMER1A (37) /* Vector 37: 16/32-Bit Timer 1 A */
# define TIVA_IRQ_TIMER1B (38) /* Vector 38: 16/32-Bit Timer 1 B */
# define TIVA_IRQ_TIMER2A (39) /* Vector 39: 16/32-Bit Timer 2 A */
# define TIVA_IRQ_TIMER2B (40) /* Vector 40: 16/32-Bit Timer 2 B */
# define TIVA_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
# define TIVA_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
# define TIVA_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 2 */
# define TIVA_IRQ_SYSCON (44) /* Vector 44: System Control */
# define TIVA_IRQ_FLASHCON (45) /* Vector 45: FLASH and EEPROM Control */
# define TIVA_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
# define TIVA_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
# define TIVA_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */
# define TIVA_IRQ_UART2 (49) /* Vector 49: UART 2 */
# define TIVA_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
# define TIVA_IRQ_TIMER3A (51) /* Vector 51: 16/32-Bit Timer 3 A */
# define TIVA_IRQ_TIMER3B (52) /* Vector 52: 16/32-Bit Timer 3 B */
# define TIVA_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
# define TIVA_IRQ_CAN0 (54) /* Vector 54: CAN 0 */
# define TIVA_IRQ_CAN1 (55) /* Vector 55: CAN 1 */
# define TIVA_IRQ_ETHCON (56) /* Vector 56: Ethernet MAC */
# define TIVA_IRQ_HIBERNATE (57) /* Vector 57: Hibernation Module */
# define TIVA_IRQ_USB (58) /* Vector 58: USB MAC */
# define TIVA_IRQ_PWM0_GEN3 (59) /* Vector 59: PWM0 Generator 3 */
# define TIVA_IRQ_UDMASOFT (60) /* Vector 60: uDMA Software */
# define TIVA_IRQ_UDMAERROR (61) /* Vector 61: uDMA Error */
# define TIVA_IRQ_ADC1_0 (62) /* Vector 62: ADC1 Sequence 0 */
# define TIVA_IRQ_ADC1_1 (63) /* Vector 63: ADC1 Sequence 1 */
# define TIVA_IRQ_ADC1_2 (64) /* Vector 64: ADC1 Sequence 2 */
# define TIVA_IRQ_ADC1_3 (65) /* Vector 65: ADC1 Sequence 3 */
# define TIVA_IRQ_EPI0 (66) /* Vector 66: EPI 0 */
# define TIVA_IRQ_GPIOJ (67) /* Vector 67: GPIO Port J */
# define TIVA_IRQ_GPIOK (68) /* Vector 68: GPIO Port K */
# define TIVA_IRQ_GPIOL (69) /* Vector 69: GPIO Port L */
# define TIVA_IRQ_SSI2 (70) /* Vector 70: SSI 2 */
# define TIVA_IRQ_SSI3 (71) /* Vector 71: SSI 3 */
# define TIVA_IRQ_UART3 (72) /* Vector 72: UART 3 */
# define TIVA_IRQ_UART4 (73) /* Vector 73: UART 4 */
# define TIVA_IRQ_UART5 (74) /* Vector 74: UART 5 */
# define TIVA_IRQ_UART6 (75) /* Vector 75: UART 6 */
# define TIVA_IRQ_UART7 (76) /* Vector 76: UART 7 */
# define TIVA_IRQ_I2C2 (77) /* Vector 77: I2C 2 */
# define TIVA_IRQ_I2C3 (78) /* Vector 78: I2C 3 */
# define TIVA_IRQ_TIMER4A (79) /* Vector 79: 16/32-Bit Timer 4 A */
# define TIVA_IRQ_TIMER4B (80) /* Vector 80: 16/32-Bit Timer 4 B */
# define TIVA_IRQ_TIMER5A (81) /* Vector 81: 16/32-Bit Timer 5 A */
# define TIVA_IRQ_TIMER5B (82) /* Vector 82: 16/32-Bit Timer 5 B */
# define TIVA_IRQ_FLOAT (83) /* Vector 83: Floating point exception */
# define TIVA_RESERVED_84 (84) /* Vector 84: Reserved */
# define TIVA_RESERVED_85 (85) /* Vector 85: Reserved */
# define TIVA_IRQ_I2C4 (86) /* Vector 86: I2C 4 */
# define TIVA_IRQ_I2C5 (87) /* Vector 87: I2C 5 */
# define TIVA_IRQ_GPIOM (88) /* Vector 88: GPIO Port M */
# define TIVA_IRQ_GPION (89) /* Vector 89: GPIO Port N */
# define TIVA_RESERVED_90 (90) /* Vector 90: Reserved */
# define TIVA_IRQ_TAMPER (91) /* Vector 91: Tamper */
# define TIVA_IRQ_GPIOP (92) /* Vector 92: GPIO Port P (Summary or P0) */
# define TIVA_IRQ_GPIOP1 (93) /* Vector 93: GPIO Port P1 */
# define TIVA_IRQ_GPIOP2 (94) /* Vector 94: GPIO Port P2 */
# define TIVA_IRQ_GPIOP3 (95) /* Vector 95: GPIO Port P3 */
# define TIVA_IRQ_GPIOP4 (96) /* Vector 96: GPIO Port P4 */
# define TIVA_IRQ_GPIOP5 (97) /* Vector 97: GPIO Port P5 */
# define TIVA_IRQ_GPIOP6 (98) /* Vector 98: GPIO Port P6 */
# define TIVA_IRQ_GPIOP7 (99) /* Vector 99: GPIO Port P7 */
# define TIVA_IRQ_GPIOQ (100) /* Vector 100: GPIO Port Q (Summary or Q0) */
# define TIVA_IRQ_GPIOQ1 (101) /* Vector 101: GPIO Port Q1 */
# define TIVA_IRQ_GPIOQ2 (102) /* Vector 102: GPIO Port Q2 */
# define TIVA_IRQ_GPIOQ3 (103) /* Vector 103: GPIO Port Q3 */
# define TIVA_IRQ_GPIOQ4 (104) /* Vector 104: GPIO Port Q4 */
# define TIVA_IRQ_GPIOQ5 (105) /* Vector 105: GPIO Port Q5 */
# define TIVA_IRQ_GPIOQ6 (106) /* Vector 106: GPIO Port Q6 */
# define TIVA_IRQ_GPIOQ7 (107) /* Vector 107: GPIO Port Q7 */
# define TIVA_IRQ_GPIOR (108) /* Vector 108: GPIO Port R */
# define TIVA_IRQ_GPIOS (109) /* Vector 109: GPIO Port S */
# define TIVA_IRQ_SHAMD5 (110) /* Vector 110: SHA/MD5 */
# define TIVA_IRQ_AES (111) /* Vector 111: AES */
# define TIVA_IRQ_DES (112) /* Vector 112: DES */
# define TIVA_IRQ_LCD (113) /* Vector 113: LCD */
# define TIVA_IRQ_TIMER6A (114) /* Vector 114: 16/32-Bit Timer 6 A */
# define TIVA_IRQ_TIMER6B (115) /* Vector 115: 16/32-Bit Timer 6 B */
# define TIVA_IRQ_TIMER7A (116) /* Vector 116: 16/32-Bit Timer 7 A */
# define TIVA_IRQ_TIMER7B (117) /* Vector 117: 16/32-Bit Timer 7 B */
# define TIVA_IRQ_I2C6 (118) /* Vector 118: I2C 6 */
# define TIVA_IRQ_I2C7 (119) /* Vector 119: I2C 7 */
# define TIVA_RESERVED_120 (120) /* Vector 120: Reserved */
# define TIVA_IRQ_1WIRE (121) /* Vector 121: 1-Wire */
# define TIVA_RESERVED_122 (122) /* Vector 122: Reserved */
# define TIVA_RESERVED_123 (123) /* Vector 123: Reserved */
# define TIVA_RESERVED_124 (124) /* Vector 124: Reserved */
# define TIVA_IRQ_I2C8 (125) /* Vector 125: I2C 8 */
# define TIVA_IRQ_I2C9 (126) /* Vector 126: I2C 9 */
# define TIVA_IRQ_GPIOT (127) /* Vector 127: GPIO Port T */
# define TIVA_RESERVED_128 (128) /* Vector 128: Reserved */
# define TIVA_RESERVED_129 (129) /* Vector 129: Reserved */
# define NR_IRQS (130) /* (Really fewer because of reserved vectors) */
#else
# error "IRQ Numbers not known for this Tiva chip"
#endif
arch/arm/src/tiva/Kconfig
+66
View File
@@ -128,6 +128,51 @@ config ARCH_CHIP_TM4C123GH6PM
select TIVA_HAVE_QEI0
select TIVA_HAVE_QEI1
config ARCH_CHIP_TM4C123GH6PZ
bool "TM4C123GH6PZ"
depends on ARCH_CHIP_TIVA
select ARCH_CHIP_TM4C
select ARCH_CHIP_TM4C123
select TIVA_HAVE_GPIOA_IRQS
select TIVA_HAVE_GPIOB_IRQS
select TIVA_HAVE_GPIOC_IRQS
select TIVA_HAVE_GPIOD_IRQS
select TIVA_HAVE_GPIOE_IRQS
select TIVA_HAVE_GPIOF_IRQS
select TIVA_HAVE_GPIOG_IRQS
select TIVA_HAVE_GPIOH_IRQS
select TIVA_HAVE_GPIOJ_IRQS
select TIVA_HAVE_GPIOK_IRQS
select TIVA_HAVE_ADC0
select TIVA_HAVE_ADC1
select TIVA_HAVE_QEI0
select TIVA_HAVE_QEI1
config ARCH_CHIP_TM4C123GH6PGE
bool "TM4C123GH6PGE"
depends on ARCH_CHIP_TIVA
select ARCH_CHIP_TM4C
select ARCH_CHIP_TM4C123
select TIVA_HAVE_GPIOA_IRQS
select TIVA_HAVE_GPIOB_IRQS
select TIVA_HAVE_GPIOC_IRQS
select TIVA_HAVE_GPIOD_IRQS
select TIVA_HAVE_GPIOE_IRQS
select TIVA_HAVE_GPIOF_IRQS
select TIVA_HAVE_GPIOG_IRQS
select TIVA_HAVE_GPIOH_IRQS
select TIVA_HAVE_GPIOJ_IRQS
select TIVA_HAVE_GPIOK_IRQS
select TIVA_HAVE_GPIOL_IRQS
select TIVA_HAVE_GPIOM_IRQS
select TIVA_HAVE_GPION_IRQS
select TIVA_HAVE_GPIOP_IRQS
select TIVA_HAVE_ADC0
select TIVA_HAVE_ADC1
select TIVA_HAVE_QEI0
select TIVA_HAVE_QEI1
config ARCH_CHIP_TM4C123GH6PGE
config ARCH_CHIP_TM4C1294NCPDT
bool "TM4C1294NCPDT"
depends on ARCH_CHIP_TIVA
@@ -164,6 +209,27 @@ config ARCH_CHIP_TM4C129ENCPDT
select TIVA_HAVE_GPIOQ_IRQS
select TIVA_HAVE_QEI0
config ARCH_CHIP_TM4C129ENCZAD
bool "TM4C129ENCZAD"
depends on ARCH_CHIP_TIVA
select ARCH_CHIP_TM4C
select ARCH_CHIP_TM4C129
select TIVA_HAVE_ETHERNET
select TIVA_HAVE_EEPROM
select TIVA_HAVE_GPIOG_IRQS
select TIVA_HAVE_GPIOH_IRQS
select TIVA_HAVE_GPIOJ_IRQS
select TIVA_HAVE_GPIOK_IRQS
select TIVA_HAVE_GPIOL_IRQS
select TIVA_HAVE_GPIOM_IRQS
select TIVA_HAVE_GPION_IRQS
select TIVA_HAVE_GPIOP_IRQS
select TIVA_HAVE_GPIOQ_IRQS
select TIVA_HAVE_GPIOR_IRQS
select TIVA_HAVE_GPIOS_IRQS
select TIVA_HAVE_GPIOT_IRQS
select TIVA_HAVE_QEI0
config ARCH_CHIP_TM4C129XNCZAD
bool "TM4C129XNCZAD"
depends on ARCH_CHIP_TIVA
arch/arm/src/tiva/hardware/tm4c/tm4c_memorymap.h
+290 -2
View File
@@ -49,7 +49,8 @@
/* Memory map ***********************************************************************/
#if defined (CONFIG_ARCH_CHIP_TM4C123AH6PM) || defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
defined(CONFIG_ARCH_CHIP_TM4C123GH6PM)
defined(CONFIG_ARCH_CHIP_TM4C123GH6PM) || defined(CONFIG_ARCH_CHIP_TM4C123GH6PZ) || \
defined(CONFIG_ARCH_CHIP_TM4C123GH6PGE)
# define TIVA_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
/* -0x00ffffff: Reserved */
# define TIVA_ROM_BASE 0x01000000 /* -0x1fffffff: Reserved for ROM */
@@ -72,7 +73,7 @@
/* -0xffffffff: Reserved */
#elif defined(CONFIG_ARCH_CHIP_TM4C129XNCZAD) || defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT) || \
defined(CONFIG_ARCH_CHIP_TM4C129ENCPDT)
defined(CONFIG_ARCH_CHIP_TM4C129ENCPDT) || defined(CONFIG_ARCH_CHIP_TM4C129ENCZAD)
# define TIVA_FLASH_BASE 0x00000000 /* -0x000fffff: On-chip FLASH */
/* -0x01ffffff: Reserved */
# define TIVA_ROM_BASE 0x02000000 /* -0x02ffffff: On-chip ROM (16 MB) */
@@ -218,8 +219,12 @@
# define TIVA_I2C3_BASE (TIVA_PERIPH_BASE + 0x23000) /* -0x23fff: I2C3 */
# define TIVA_GPIOE_BASE (TIVA_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define TIVA_GPIOF_BASE (TIVA_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
/* -0x27fff: Reserved */
# define TIVA_PWM0_BASE (TIVA_PERIPH_BASE + 0x28000) /* -0x28fff: PWM 0 */
# define TIVA_PWM1_BASE (TIVA_PERIPH_BASE + 0x29000) /* -0x29fff: PWM 1 */
/* -0x2bfff: Reserved */
# define TIVA_QEI0_BASE (TIVA_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI 0 */
# define TIVA_QEI1_BASE (TIVA_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI 1 */
/* -0x2ffff: Reserved */
# define TIVA_TIMER0_BASE (TIVA_PERIPH_BASE + 0x30000) /* -0x30fff: 16/32 Timer 0 */
# define TIVA_TIMER1_BASE (TIVA_PERIPH_BASE + 0x31000) /* -0x31fff: 16/32 Timer 1 */
@@ -259,6 +264,178 @@
# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
# define TIVA_UDMA_BASE (TIVA_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PZ)
/* Peripheral Base Addresses */
# define TIVA_WDOG0_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */
# define TIVA_WDOG1_BASE (TIVA_PERIPH_BASE + 0x01000) /* -0x00fff: Watchdog Timer 1 */
/* -0x03fff: Reserved */
# define TIVA_GPIOA_BASE (TIVA_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
# define TIVA_GPIOB_BASE (TIVA_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
# define TIVA_GPIOC_BASE (TIVA_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
# define TIVA_GPIOD_BASE (TIVA_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
# define TIVA_SSI0_BASE (TIVA_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
# define TIVA_SSI1_BASE (TIVA_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
# define TIVA_SSI2_BASE (TIVA_PERIPH_BASE + 0x0a000) /* -0x0afff: SSI2 */
# define TIVA_SSI3_BASE (TIVA_PERIPH_BASE + 0x0b000) /* -0x0bfff: SSI3 */
# define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
# define TIVA_UART2_BASE (TIVA_PERIPH_BASE + 0x0e000) /* -0x0efff: UART2 */
# define TIVA_UART3_BASE (TIVA_PERIPH_BASE + 0x0f000) /* -0x0ffff: UART3 */
# define TIVA_UART4_BASE (TIVA_PERIPH_BASE + 0x10000) /* -0x10fff: UART4 */
# define TIVA_UART5_BASE (TIVA_PERIPH_BASE + 0x11000) /* -0x11fff: UART5 */
# define TIVA_UART6_BASE (TIVA_PERIPH_BASE + 0x12000) /* -0x12fff: UART6 */
# define TIVA_UART7_BASE (TIVA_PERIPH_BASE + 0x13000) /* -0x13fff: UART7 */
/* -0x1ffff: Reserved */
# define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x20fff: I2C0 */
# define TIVA_I2C1_BASE (TIVA_PERIPH_BASE + 0x21000) /* -0x21fff: I2C1 */
# define TIVA_I2C2_BASE (TIVA_PERIPH_BASE + 0x22000) /* -0x22fff: I2C2 */
# define TIVA_I2C3_BASE (TIVA_PERIPH_BASE + 0x23000) /* -0x23fff: I2C3 */
# define TIVA_GPIOE_BASE (TIVA_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define TIVA_GPIOF_BASE (TIVA_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
# define TIVA_GPIOG_BASE (TIVA_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
# define TIVA_GPIOH_BASE (TIVA_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */
# define TIVA_PWM0_BASE (TIVA_PERIPH_BASE + 0x28000) /* -0x28fff: PWM 0 */
# define TIVA_PWM1_BASE (TIVA_PERIPH_BASE + 0x29000) /* -0x29fff: PWM 1 */
/* -0x2bfff: Reserved */
# define TIVA_QEI0_BASE (TIVA_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI 0 */
# define TIVA_QEI1_BASE (TIVA_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI 1 */
/* -0x2ffff: Reserved */
# define TIVA_TIMER0_BASE (TIVA_PERIPH_BASE + 0x30000) /* -0x30fff: 16/32 Timer 0 */
# define TIVA_TIMER1_BASE (TIVA_PERIPH_BASE + 0x31000) /* -0x31fff: 16/32 Timer 1 */
# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: 16/32 Timer 2 */
# define TIVA_TIMER3_BASE (TIVA_PERIPH_BASE + 0x33000) /* -0x33fff: 16/32 Timer 3 */
# define TIVA_TIMER4_BASE (TIVA_PERIPH_BASE + 0x34000) /* -0x34fff: 16/32 Timer 4 */
# define TIVA_TIMER5_BASE (TIVA_PERIPH_BASE + 0x35000) /* -0x35fff: 16/32 Timer 5 */
# define TIVA_WTIMER0_BASE (TIVA_PERIPH_BASE + 0x36000) /* -0x36fff: 32/64 Wide Timer 0 */
# define TIVA_WTIMER1_BASE (TIVA_PERIPH_BASE + 0x37000) /* -0x37fff: 32/64 Wide Timer 1 */
# define TIVA_ADC0_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
# define TIVA_ADC1_BASE (TIVA_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
/* -0x3bfff: Reserved */
# define TIVA_CMP_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
# define TIVA_GPIOJ_BASE (TIVA_PERIPH_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */
/* -0x3ffff: Reserved */
# define TIVA_CAN0_BASE (TIVA_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller 0 */
# define TIVA_CAN1_BASE (TIVA_PERIPH_BASE + 0x41000) /* -0x41fff: CAN Controller 1 */
/* -0x4bfff: Reserved */
# define TIVA_WTIMER2_BASE (TIVA_PERIPH_BASE + 0x4c000) /* -0x4cfff: 32/64 Wide Timer 2 */
# define TIVA_WTIMER3_BASE (TIVA_PERIPH_BASE + 0x4d000) /* -0x4dfff: 32/64 Wide Timer 3 */
# define TIVA_WTIMER4_BASE (TIVA_PERIPH_BASE + 0x4e000) /* -0x4efff: 32/64 Wide Timer 4 */
# define TIVA_WTIMER5_BASE (TIVA_PERIPH_BASE + 0x4f000) /* -0x4ffff: 32/64 Wide Timer 5 */
# define TIVA_USB_BASE (TIVA_PERIPH_BASE + 0x50000) /* -0x50fff: USB */
/* -0x57fff: Reserved */
# define TIVA_GPIOAAHB_BASE (TIVA_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */
# define TIVA_GPIOBAHB_BASE (TIVA_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */
# define TIVA_GPIOCAHB_BASE (TIVA_PERIPH_BASE + 0x5a000) /* -0x5afff: GPIO Port C (AHB aperture) */
# define TIVA_GPIODAHB_BASE (TIVA_PERIPH_BASE + 0x5b000) /* -0x5bfff: GPIO Port D (AHB aperture) */
# define TIVA_GPIOEAHB_BASE (TIVA_PERIPH_BASE + 0x5c000) /* -0x5cfff: GPIO Port E (AHB aperture) */
# define TIVA_GPIOFAHB_BASE (TIVA_PERIPH_BASE + 0x5d000) /* -0x5dfff: GPIO Port F (AHB aperture) */
# define TIVA_GPIOGAHB_BASE (TIVA_PERIPH_BASE + 0x5e000) /* -0x5efff: GPIO Port G (AHB aperture) */
# define TIVA_GPIOHAHB_BASE (TIVA_PERIPH_BASE + 0x5f000) /* -0x5ffff: GPIO Port H (AHB aperture) */
# define TIVA_GPIOJAHB_BASE (TIVA_PERIPH_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */
# define TIVA_GPIOKAHB_BASE (TIVA_PERIPH_BASE + 0x61000) /* -0x61fff: GPIO Port K (AHB aperture) */
/* -0xaefff: Reserved */
# define TIVA_EEPROM_BASE (TIVA_PERIPH_BASE + 0xaf000) /* -0xaffff: EEPROM and Key Locker */
/* -0xbffff: Reserved */
# define TIVA_I2C4_BASE (TIVA_PERIPH_BASE + 0xc0000) /* -0xc0fff: I2C4 */
# define TIVA_I2C5_BASE (TIVA_PERIPH_BASE + 0xc1000) /* -0xc1fff: I2C5 */
/* -0xf8fff: Reserved */
# define TIVA_SYSEXC_BASE (TIVA_PERIPH_BASE + 0xf9000) /* -0xf9fff: System Exception Control */
/* -0xfbfff: Reserved */
# define TIVA_HIBERNATE_BASE (TIVA_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
# define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
# define TIVA_UDMA_BASE (TIVA_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
#elif defined(CONFIG_ARCH_CHIP_TM4C123GH6PGE)
/* Peripheral Base Addresses */
# define TIVA_WDOG0_BASE (TIVA_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */
# define TIVA_WDOG1_BASE (TIVA_PERIPH_BASE + 0x01000) /* -0x00fff: Watchdog Timer 1 */
/* -0x03fff: Reserved */
# define TIVA_GPIOA_BASE (TIVA_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
# define TIVA_GPIOB_BASE (TIVA_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
# define TIVA_GPIOC_BASE (TIVA_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
# define TIVA_GPIOD_BASE (TIVA_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
# define TIVA_SSI0_BASE (TIVA_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
# define TIVA_SSI1_BASE (TIVA_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
# define TIVA_SSI2_BASE (TIVA_PERIPH_BASE + 0x0a000) /* -0x0afff: SSI2 */
# define TIVA_SSI3_BASE (TIVA_PERIPH_BASE + 0x0b000) /* -0x0bfff: SSI3 */
# define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
# define TIVA_UART2_BASE (TIVA_PERIPH_BASE + 0x0e000) /* -0x0efff: UART2 */
# define TIVA_UART3_BASE (TIVA_PERIPH_BASE + 0x0f000) /* -0x0ffff: UART3 */
# define TIVA_UART4_BASE (TIVA_PERIPH_BASE + 0x10000) /* -0x10fff: UART4 */
# define TIVA_UART5_BASE (TIVA_PERIPH_BASE + 0x11000) /* -0x11fff: UART5 */
# define TIVA_UART6_BASE (TIVA_PERIPH_BASE + 0x12000) /* -0x12fff: UART6 */
# define TIVA_UART7_BASE (TIVA_PERIPH_BASE + 0x13000) /* -0x13fff: UART7 */
/* -0x1ffff: Reserved */
# define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x20fff: I2C0 */
# define TIVA_I2C1_BASE (TIVA_PERIPH_BASE + 0x21000) /* -0x21fff: I2C1 */
# define TIVA_I2C2_BASE (TIVA_PERIPH_BASE + 0x22000) /* -0x22fff: I2C2 */
# define TIVA_I2C3_BASE (TIVA_PERIPH_BASE + 0x23000) /* -0x23fff: I2C3 */
# define TIVA_GPIOE_BASE (TIVA_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define TIVA_GPIOF_BASE (TIVA_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
# define TIVA_GPIOG_BASE (TIVA_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
# define TIVA_GPIOH_BASE (TIVA_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */
# define TIVA_PWM0_BASE (TIVA_PERIPH_BASE + 0x28000) /* -0x28fff: PWM 0 */
# define TIVA_PWM1_BASE (TIVA_PERIPH_BASE + 0x29000) /* -0x29fff: PWM 1 */
/* -0x2bfff: Reserved */
# define TIVA_QEI0_BASE (TIVA_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI 0 */
# define TIVA_QEI1_BASE (TIVA_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI 1 */
/* -0x2ffff: Reserved */
# define TIVA_TIMER0_BASE (TIVA_PERIPH_BASE + 0x30000) /* -0x30fff: 16/32 Timer 0 */
# define TIVA_TIMER1_BASE (TIVA_PERIPH_BASE + 0x31000) /* -0x31fff: 16/32 Timer 1 */
# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: 16/32 Timer 2 */
# define TIVA_TIMER3_BASE (TIVA_PERIPH_BASE + 0x33000) /* -0x33fff: 16/32 Timer 3 */
# define TIVA_TIMER4_BASE (TIVA_PERIPH_BASE + 0x34000) /* -0x34fff: 16/32 Timer 4 */
# define TIVA_TIMER5_BASE (TIVA_PERIPH_BASE + 0x35000) /* -0x35fff: 16/32 Timer 5 */
# define TIVA_WTIMER0_BASE (TIVA_PERIPH_BASE + 0x36000) /* -0x36fff: 32/64 Wide Timer 0 */
# define TIVA_WTIMER1_BASE (TIVA_PERIPH_BASE + 0x37000) /* -0x37fff: 32/64 Wide Timer 1 */
# define TIVA_ADC0_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
# define TIVA_ADC1_BASE (TIVA_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
/* -0x3bfff: Reserved */
# define TIVA_CMP_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
# define TIVA_GPIOJ_BASE (TIVA_PERIPH_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */
/* -0x3ffff: Reserved */
# define TIVA_CAN0_BASE (TIVA_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller 0 */
# define TIVA_CAN1_BASE (TIVA_PERIPH_BASE + 0x41000) /* -0x41fff: CAN Controller 1 */
/* -0x4bfff: Reserved */
# define TIVA_WTIMER2_BASE (TIVA_PERIPH_BASE + 0x4c000) /* -0x4cfff: 32/64 Wide Timer 2 */
# define TIVA_WTIMER3_BASE (TIVA_PERIPH_BASE + 0x4d000) /* -0x4dfff: 32/64 Wide Timer 3 */
# define TIVA_WTIMER4_BASE (TIVA_PERIPH_BASE + 0x4e000) /* -0x4efff: 32/64 Wide Timer 4 */
# define TIVA_WTIMER5_BASE (TIVA_PERIPH_BASE + 0x4f000) /* -0x4ffff: 32/64 Wide Timer 5 */
# define TIVA_USB_BASE (TIVA_PERIPH_BASE + 0x50000) /* -0x50fff: USB */
/* -0x57fff: Reserved */
# define TIVA_GPIOAAHB_BASE (TIVA_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */
# define TIVA_GPIOBAHB_BASE (TIVA_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */
# define TIVA_GPIOCAHB_BASE (TIVA_PERIPH_BASE + 0x5a000) /* -0x5afff: GPIO Port C (AHB aperture) */
# define TIVA_GPIODAHB_BASE (TIVA_PERIPH_BASE + 0x5b000) /* -0x5bfff: GPIO Port D (AHB aperture) */
# define TIVA_GPIOEAHB_BASE (TIVA_PERIPH_BASE + 0x5c000) /* -0x5cfff: GPIO Port E (AHB aperture) */
# define TIVA_GPIOFAHB_BASE (TIVA_PERIPH_BASE + 0x5d000) /* -0x5dfff: GPIO Port F (AHB aperture) */
# define TIVA_GPIOGAHB_BASE (TIVA_PERIPH_BASE + 0x5e000) /* -0x5efff: GPIO Port G (AHB aperture) */
# define TIVA_GPIOHAHB_BASE (TIVA_PERIPH_BASE + 0x5f000) /* -0x5ffff: GPIO Port H (AHB aperture) */
# define TIVA_GPIOJAHB_BASE (TIVA_PERIPH_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */
# define TIVA_GPIOKAHB_BASE (TIVA_PERIPH_BASE + 0x61000) /* -0x61fff: GPIO Port K (AHB aperture) */
# define TIVA_GPIOLAHB_BASE (TIVA_PERIPH_BASE + 0x62000) /* -0x62fff: GPIO Port L (AHB aperture) */
# define TIVA_GPIOMAHB_BASE (TIVA_PERIPH_BASE + 0x63000) /* -0x63fff: GPIO Port M (AHB aperture) */
# define TIVA_GPIONAHB_BASE (TIVA_PERIPH_BASE + 0x64000) /* -0x64fff: GPIO Port N (AHB aperture) */
# define TIVA_GPIOPAHB_BASE (TIVA_PERIPH_BASE + 0x65000) /* -0x65fff: GPIO Port P (AHB aperture) */
/* -0xaefff: Reserved */
# define TIVA_EEPROM_BASE (TIVA_PERIPH_BASE + 0xaf000) /* -0xaffff: EEPROM and Key Locker */
/* -0xbffff: Reserved */
# define TIVA_I2C4_BASE (TIVA_PERIPH_BASE + 0xc0000) /* -0xc0fff: I2C4 */
# define TIVA_I2C5_BASE (TIVA_PERIPH_BASE + 0xc1000) /* -0xc1fff: I2C5 */
/* -0xf8fff: Reserved */
# define TIVA_SYSEXC_BASE (TIVA_PERIPH_BASE + 0xf9000) /* -0xf9fff: System Exception Control */
/* -0xfbfff: Reserved */
# define TIVA_HIBERNATE_BASE (TIVA_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
# define TIVA_FLASHCON_BASE (TIVA_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define TIVA_SYSCON_BASE (TIVA_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
# define TIVA_UDMA_BASE (TIVA_PERIPH_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
#elif defined(CONFIG_ARCH_CHIP_TM4C123AH6PM)
/* Peripheral Base Addresses */
@@ -644,6 +821,117 @@
/* -0x53fff: Reserved */
# define TIVA_EPHY_BASE (TIVA_PERIPH2_BASE + 0x54000) /* -0x54fff: EPHY 0 */
/* -0xfffff: Reserved */
#elif defined(CONFIG_ARCH_CHIP_TM4C129ENCZAD)
/* Peripheral region 1 */
# define TIVA_WDOG0_BASE (TIVA_PERIPH1_BASE + 0x00000) /* -0x00fff: Watchdog Timer 0 */
# define TIVA_WDOG1_BASE (TIVA_PERIPH1_BASE + 0x01000) /* -0x00fff: Watchdog Timer 1 */
/* -0x03fff: Reserved */
# define TIVA_GPIOA_BASE (TIVA_PERIPH1_BASE + 0x04000) /* -0x04fff: GPIO Port A */
# define TIVA_GPIOB_BASE (TIVA_PERIPH1_BASE + 0x05000) /* -0x05fff: GPIO Port B */
# define TIVA_GPIOC_BASE (TIVA_PERIPH1_BASE + 0x06000) /* -0x06fff: GPIO Port C */
# define TIVA_GPIOD_BASE (TIVA_PERIPH1_BASE + 0x07000) /* -0x07fff: GPIO Port D */
# define TIVA_SSI0_BASE (TIVA_PERIPH1_BASE + 0x08000) /* -0x08fff: SSI0 */
# define TIVA_SSI1_BASE (TIVA_PERIPH1_BASE + 0x09000) /* -0x09fff: SSI1 */
# define TIVA_SSI2_BASE (TIVA_PERIPH1_BASE + 0x0a000) /* -0x0afff: SSI2 */
# define TIVA_SSI3_BASE (TIVA_PERIPH1_BASE + 0x0b000) /* -0x0bfff: SSI3 */
# define TIVA_UART0_BASE (TIVA_PERIPH1_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define TIVA_UART1_BASE (TIVA_PERIPH1_BASE + 0x0d000) /* -0x0dfff: UART1 */
# define TIVA_UART2_BASE (TIVA_PERIPH1_BASE + 0x0e000) /* -0x0efff: UART2 */
# define TIVA_UART3_BASE (TIVA_PERIPH1_BASE + 0x0f000) /* -0x0ffff: UART3 */
# define TIVA_UART4_BASE (TIVA_PERIPH1_BASE + 0x10000) /* -0x10fff: UART4 */
# define TIVA_UART5_BASE (TIVA_PERIPH1_BASE + 0x11000) /* -0x11fff: UART5 */
# define TIVA_UART6_BASE (TIVA_PERIPH1_BASE + 0x12000) /* -0x12fff: UART6 */
# define TIVA_UART7_BASE (TIVA_PERIPH1_BASE + 0x13000) /* -0x13fff: UART7 */
/* -0x1ffff: Reserved */
# define TIVA_I2C0_BASE (TIVA_PERIPH1_BASE + 0x20000) /* -0x20fff: I2C0 */
# define TIVA_I2C1_BASE (TIVA_PERIPH1_BASE + 0x21000) /* -0x21fff: I2C1 */
# define TIVA_I2C2_BASE (TIVA_PERIPH1_BASE + 0x22000) /* -0x22fff: I2C2 */
# define TIVA_I2C3_BASE (TIVA_PERIPH1_BASE + 0x23000) /* -0x23fff: I2C3 */
# define TIVA_GPIOE_BASE (TIVA_PERIPH1_BASE + 0x24000) /* -0x24fff: GPIO Port E */
# define TIVA_GPIOF_BASE (TIVA_PERIPH1_BASE + 0x25000) /* -0x25fff: GPIO Port F */
# define TIVA_GPIOG_BASE (TIVA_PERIPH1_BASE + 0x26000) /* -0x26fff: GPIO Port G */
# define TIVA_GPIOH_BASE (TIVA_PERIPH1_BASE + 0x27000) /* -0x27fff: GPIO Port H */
# define TIVA_PWM0_BASE (TIVA_PERIPH1_BASE + 0x28000) /* -0x28fff: PWM 0 */
/* -0x2bfff: Reserved */
# define TIVA_QEI0_BASE (TIVA_PERIPH1_BASE + 0x2c000) /* -0x2cfff: QEI 0 */
/* -0x2ffff: Reserved */
# define TIVA_TIMER0_BASE (TIVA_PERIPH1_BASE + 0x30000) /* -0x30fff: 16/32 Timer 0 */
# define TIVA_TIMER1_BASE (TIVA_PERIPH1_BASE + 0x31000) /* -0x31fff: 16/32 Timer 1 */
# define TIVA_TIMER2_BASE (TIVA_PERIPH1_BASE + 0x32000) /* -0x32fff: 16/32 Timer 2 */
# define TIVA_TIMER3_BASE (TIVA_PERIPH1_BASE + 0x33000) /* -0x33fff: 16/32 Timer 3 */
# define TIVA_TIMER4_BASE (TIVA_PERIPH1_BASE + 0x34000) /* -0x34fff: 16/32 Timer 4 */
# define TIVA_TIMER5_BASE (TIVA_PERIPH1_BASE + 0x35000) /* -0x35fff: 16/32 Timer 5 */
/* -0x37fff: Reserved */
# define TIVA_ADC0_BASE (TIVA_PERIPH1_BASE + 0x38000) /* -0x38fff: ADC 0 */
# define TIVA_ADC1_BASE (TIVA_PERIPH1_BASE + 0x39000) /* -0x39fff: ADC 1 */
/* -0x3bfff: Reserved */
# define TIVA_CMP_BASE (TIVA_PERIPH1_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
# define TIVA_GPIOJ_BASE (TIVA_PERIPH1_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */
/* -0x3ffff: Reserved */
# define TIVA_CAN0_BASE (TIVA_PERIPH1_BASE + 0x40000) /* -0x40fff: CAN Controller 0 */
# define TIVA_CAN1_BASE (TIVA_PERIPH1_BASE + 0x41000) /* -0x41fff: CAN Controller 1 */
/* -0x4ffff: Reserved */
# define TIVA_USB_BASE (TIVA_PERIPH1_BASE + 0x50000) /* -0x50fff: USB */
/* -0x57fff: Reserved */
# define TIVA_GPIOAAHB_BASE (TIVA_PERIPH1_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */
# define TIVA_GPIOBAHB_BASE (TIVA_PERIPH1_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */
# define TIVA_GPIOCAHB_BASE (TIVA_PERIPH1_BASE + 0x5a000) /* -0x5afff: GPIO Port C (AHB aperture) */
# define TIVA_GPIODAHB_BASE (TIVA_PERIPH1_BASE + 0x5b000) /* -0x5bfff: GPIO Port D (AHB aperture) */
# define TIVA_GPIOEAHB_BASE (TIVA_PERIPH1_BASE + 0x5c000) /* -0x5cfff: GPIO Port E (AHB aperture) */
# define TIVA_GPIOFAHB_BASE (TIVA_PERIPH1_BASE + 0x5d000) /* -0x5dfff: GPIO Port F (AHB aperture) */
# define TIVA_GPIOGAHB_BASE (TIVA_PERIPH1_BASE + 0x5e000) /* -0x5efff: GPIO Port G (AHB aperture) */
# define TIVA_GPIOHAHB_BASE (TIVA_PERIPH1_BASE + 0x5f000) /* -0x5ffff: GPIO Port H (AHB aperture) */
# define TIVA_GPIOJAHB_BASE (TIVA_PERIPH1_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */
# define TIVA_GPIOKAHB_BASE (TIVA_PERIPH1_BASE + 0x61000) /* -0x61fff: GPIO Port K (AHB aperture) */
# define TIVA_GPIOLAHB_BASE (TIVA_PERIPH1_BASE + 0x62000) /* -0x62fff: GPIO Port L (AHB aperture) */
# define TIVA_GPIOMAHB_BASE (TIVA_PERIPH1_BASE + 0x63000) /* -0x63fff: GPIO Port M (AHB aperture) */
# define TIVA_GPIONAHB_BASE (TIVA_PERIPH1_BASE + 0x64000) /* -0x64fff: GPIO Port N (AHB aperture) */
# define TIVA_GPIOPAHB_BASE (TIVA_PERIPH1_BASE + 0x65000) /* -0x65fff: GPIO Port P (AHB aperture) */
# define TIVA_GPIOQAHB_BASE (TIVA_PERIPH1_BASE + 0x66000) /* -0x66fff: GPIO Port Q (AHB aperture) */
# define TIVA_GPIORAHB_BASE (TIVA_PERIPH1_BASE + 0x67000) /* -0x67fff: GPIO Port R (AHB aperture) */
# define TIVA_GPIOSAHB_BASE (TIVA_PERIPH1_BASE + 0x68000) /* -0x68fff: GPIO Port S (AHB aperture) */
# define TIVA_GPIOTAHB_BASE (TIVA_PERIPH1_BASE + 0x69000) /* -0x69fff: GPIO Port T (AHB aperture) */
/* -0xaefff: Reserved */
# define TIVA_EEPROM_BASE (TIVA_PERIPH1_BASE + 0xaf000) /* -0xaffff: EEPROM and Key Locker */
/* -0xb5fff: Reserved */
# define TIVA_1WIRE_BASE (TIVA_PERIPH1_BASE + 0xb6000) /* -0xb6fff: 1-Wire Master Module */
/* -0xb7fff: Reserved */
# define TIVA_I2C8_BASE (TIVA_PERIPH1_BASE + 0xb8000) /* -0xb8fff: I2C8 */
# define TIVA_I2C9_BASE (TIVA_PERIPH1_BASE + 0xb9000) /* -0xb9fff: I2C9 */
/* -0xbffff: Reserved */
# define TIVA_I2C4_BASE (TIVA_PERIPH1_BASE + 0xc0000) /* -0xc0fff: I2C4 */
# define TIVA_I2C5_BASE (TIVA_PERIPH1_BASE + 0xc1000) /* -0xc1fff: I2C5 */
# define TIVA_I2C6_BASE (TIVA_PERIPH1_BASE + 0xc2000) /* -0xc2fff: I2C6 */
# define TIVA_I2C7_BASE (TIVA_PERIPH1_BASE + 0xc3000) /* -0xc3fff: I2C7 */
/* -0xcffff: Reserved */
# define TIVA_EPI0_BASE (TIVA_PERIPH1_BASE + 0xd0000) /* -0xd0fff: EPI0 */
/* -0xdffff: Reserved */
# define TIVA_TIMER6_BASE (TIVA_PERIPH1_BASE + 0xe0000) /* -0xe0fff: 16/32 Timer 6 */
# define TIVA_TIMER7_BASE (TIVA_PERIPH1_BASE + 0xe1000) /* -0xe1fff: 16/32 Timer 7 */
/* -0xebfff: Reserved */
# define TIVA_ETHCON_BASE (TIVA_PERIPH1_BASE + 0xec000) /* -0xecfff: Ethernet Controller */
/* -0xf8fff: Reserved */
# define TIVA_SYSEXC_BASE (TIVA_PERIPH1_BASE + 0xf9000) /* -0xf9fff: System Exception Control */
/* -0xfbfff: Reserved */
# define TIVA_HIBERNATE_BASE (TIVA_PERIPH1_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
# define TIVA_FLASHCON_BASE (TIVA_PERIPH1_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define TIVA_SYSCON_BASE (TIVA_PERIPH1_BASE + 0xfe000) /* -0xfefff: System Control */
# define TIVA_UDMA_BASE (TIVA_PERIPH1_BASE + 0xff000) /* -0xfffff: Micro Direct Memory Access */
/* Peripheral region 2 */
/* -0x2ffff: Reserved */
# define TIVA_CCM_BASE (TIVA_PERIPH2_BASE + 0x30000) /* -0x30fff: CRC/Cryptographic Control */
/* -0x33fff: Reserved */
# define TIVA_SHAMD5_BASE (TIVA_PERIPH2_BASE + 0x34000) /* -0x35fff: SHA/MD5 */
# define TIVA_AES_BASE (TIVA_PERIPH2_BASE + 0x36000) /* -0x37fff: AES */
# define TIVA_DES_BASE (TIVA_PERIPH2_BASE + 0x38000) /* -0x39fff: DES */
/* -0x4ffff: Reserved */
# define TIVA_LCD_BASE (TIVA_PERIPH2_BASE + 0x50000) /* -0x50fff: LCD */
/* -0x53fff: Reserved */
# define TIVA_EPHY_BASE (TIVA_PERIPH2_BASE + 0x54000) /* -0x54fff: EPHY */
/* -0xfffff: Reserved */
#else
# error "Peripheral base addresses not specified for this Tiva chip"
#endif
arch/arm/src/tiva/hardware/tm4c/tm4c_pinmap.h
+1115 -12
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File diff suppressed because it is too large Load Diff
boards/arm/tiva/tm4c123g-launchpad/include/board.h
-9
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@@ -195,13 +195,4 @@
#define GPIO_UART1_RX GPIO_UART1_RX_1
#define GPIO_UART1_TX GPIO_UART1_TX_1
/* Pin SPI definitions ******************************************************/
/* Needed by: chip/common/tiva_ssi.c ****************************************/
#define GPIO_SSI2_RX GPIO_SSI2_RX_1
#define GPIO_SSI2_TX GPIO_SSI2_TX_1
#define GPIO_SSI2_CLK GPIO_SSI2_CLK_1
#define GPIO_SSI2_FSS GPIO_SSI2_FSS_1
#endif /* __BOARDS_ARM_TMC4C123G_LAUNCHPAD_INCLUDE_BOARD_H */