Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-06-08 01:42:58 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'upstream/master'

Browse Source
This commit is contained in:
pnb
2015-12-20 13:00:17 +01:00
parent 2f78c0c1bc b69c91a8a8
commit 510dc7872d
149 changed files with 17794 additions and 406 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/Kconfig
+80 -5
View File
@@ -68,6 +68,7 @@ config ARCH_CHIP_KINETIS
bool "Freescale Kinetis"
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FPU
select ARCH_HAVE_RAMFUNCS
---help---
@@ -84,6 +85,7 @@ config ARCH_CHIP_LM
bool "TI/Luminary Stellaris"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
---help---
TI/Luminary Stellaris LMS3 and LM4F architectures (ARM Cortex-M3/4)
@@ -91,6 +93,7 @@ config ARCH_CHIP_TIVA
bool "TI Tiva"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FPU
---help---
TI Tiva TM4C architectures (ARM Cortex-M4)
@@ -107,6 +110,7 @@ config ARCH_CHIP_LPC17XX
select ARCH_CORTEXM3
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
---help---
NXP LPC17xx architectures (ARM Cortex-M3)
@@ -137,6 +141,7 @@ config ARCH_CHIP_LPC43XX
select ARCH_HAVE_CMNVECTOR
select ARMV7M_CMNVECTOR
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FPU
---help---
NPX LPC43XX architectures (ARM Cortex-M4).
@@ -178,6 +183,7 @@ config ARCH_CHIP_SAM34
bool "Atmel SAM3/SAM4"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_RAMFUNCS
select ARMV7M_HAVE_STACKCHECK
---help---
@@ -189,6 +195,7 @@ config ARCH_CHIP_SAMV7
select ARMV7M_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_TICKLESS
select ARMV7M_HAVE_STACKCHECK
@@ -199,6 +206,7 @@ config ARCH_CHIP_STM32
bool "STMicro STM32 F1/F2/F3/F4"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARMV7M_HAVE_STACKCHECK
@@ -211,6 +219,7 @@ config ARCH_CHIP_STM32F7
select ARMV7M_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARMV7M_HAVE_STACKCHECK
@@ -224,6 +233,14 @@ config ARCH_CHIP_STR71X
---help---
STMicro STR71x architectures (ARM7TDMI).
config ARCH_CHIP_TMS570
bool "TI TMS570"
select ARCH_HAVE_LOWVECTORS
select ARCH_HAVE_RAMFUNCS
select ARMV7R_MEMINIT
---help---
TI TMS570 family
config ARCH_CHIP_MOXART
bool "MoxART"
select ARCH_ARM7TDMI
@@ -279,6 +296,7 @@ config ARCH_CORTEXM7
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXA5
bool
@@ -286,7 +304,7 @@ config ARCH_CORTEXA5
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MMU
select ARCH_USE_MMU
select ARCH_HAVE_COHERENT_DCACHE if ELF
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXA8
bool
@@ -294,7 +312,52 @@ config ARCH_CORTEXA8
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MMU
select ARCH_USE_MMU
select ARCH_HAVE_COHERENT_DCACHE if ELF
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXR4
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MPU
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXR4F
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MPU
select ARCH_HAVE_FPU
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXR5
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MPU
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEX5F
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MPU
select ARCH_HAVE_FPU
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXR7
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MPU
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXR7F
bool
default n
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_MPU
select ARCH_HAVE_FPU
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_FAMILY
string
@@ -302,6 +365,7 @@ config ARCH_FAMILY
default "armv6-m" if ARCH_CORTEXM0
default "armv7-a" if ARCH_CORTEXA5 || ARCH_CORTEXA8
default "armv7-m" if ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
default "armv7-r" if ARCH_CORTEXR4 || ARCH_CORTEXR4F || ARCH_CORTEXR5 || ARCH_CORTEXR5F || ARCH_CORTEX74 || ARCH_CORTEXR7F
config ARCH_CHIP
string
@@ -328,6 +392,7 @@ config ARCH_CHIP
default "stm32" if ARCH_CHIP_STM32
default "stm32f7" if ARCH_CHIP_STM32F7
default "str71x" if ARCH_CHIP_STR71X
default "tms570" if ARCH_CHIP_TMS570
default "moxart" if ARCH_CHIP_MOXART
config ARMV7M_USEBASEPRI
@@ -415,7 +480,11 @@ config ARCH_DPFPU
Enable toolchain support for double precision (64-bit) floating
point if both the toolchain and the hardware support it.
config ARMV7M_MPU
config ARM_HAVE_MPU_UNIFIED
bool
default n
config ARM_MPU
bool "MPU support"
default n
depends on ARCH_HAVE_MPU
@@ -425,11 +494,11 @@ config ARMV7M_MPU
Check your chip specifications first; not all Cortex-M3/4 chips
support the MPU.
config ARMV7M_MPU_NREGIONS
config ARM_MPU_NREGIONS
int "Number of MPU regions"
default 16 if ARCH_CORTEXM7
default 8 if !ARCH_CORTEXM7
depends on ARMV7M_MPU
depends on ARM_MPU
---help---
This is the number of protection regions supported by the MPU.
@@ -468,6 +537,9 @@ endif
if ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
source arch/arm/src/armv7-m/Kconfig
endif
if ARCH_CORTEXR4 || ARCH_CORTEXR4F || ARCH_CORTEXR5 || ARCH_CORTEXR5F || ARCH_CORTEX74 || ARCH_CORTEXR7F
source arch/arm/src/armv7-r/Kconfig
endif
if ARCH_ARM7TDMI || ARCH_ARM926EJS || ARCH_ARM920T
source arch/arm/src/arm/Kconfig
endif
@@ -540,6 +612,9 @@ endif
if ARCH_CHIP_STR71X
source arch/arm/src/str71x/Kconfig
endif
if ARCH_CHIP_TMS570
source arch/arm/src/tms570/Kconfig
endif
if ARCH_CHIP_MOXART
source arch/arm/src/moxart/Kconfig
endif
arch/arm/include/armv7-a/syscall.h
+1 -1
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/include/armv-7a/syscall.h
* arch/arm/include/armv7-a/syscall.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/include/armv7-r/irq.h
+412
View File
@@ -0,0 +1,412 @@
/****************************************************************************
* arch/arm/include/armv7-r/irq.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_ARMV7_R_IRQ_H
#define __ARCH_ARM_INCLUDE_ARMV7_R_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
# include <arch/arch.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ Stack Frame Format:
*
* Context is always saved/restored in the same way:
*
* (1) stmia rx, {r0-r14}
* (2) then the PC and CPSR
*
* This results in the following set of indices that can be used to access
* individual registers in the xcp.regs array:
*/
#define REG_R0 (0)
#define REG_R1 (1)
#define REG_R2 (2)
#define REG_R3 (3)
#define REG_R4 (4)
#define REG_R5 (5)
#define REG_R6 (6)
#define REG_R7 (7)
#define REG_R8 (8)
#define REG_R9 (9)
#define REG_R10 (10)
#define REG_R11 (11)
#define REG_R12 (12)
#define REG_R13 (13)
#define REG_R14 (14)
#define REG_R15 (15)
#define REG_CPSR (16)
#define ARM_CONTEXT_REGS (17)
/* If the MCU supports a floating point unit, then it will be necessary
* to save the state of the FPU status register and data registers on
* each context switch. These registers are not saved during interrupt
* level processing, however. So, as a consequence, floating point
* operations may NOT be performed in interrupt handlers.
*
* The FPU provides an extension register file containing 32 single-
* precision registers. These can be viewed as:
*
* - Sixteen 64-bit double word registers, D0-D15
* - Thirty-two 32-bit single-word registers, S0-S31
* S<2n> maps to the least significant half of D<n>
* S<2n+1> maps to the most significant half of D<n>.
*/
#ifdef CONFIG_ARCH_FPU
# define REG_D0 (ARM_CONTEXT_REGS+0) /* D0 */
# define REG_S0 (ARM_CONTEXT_REGS+0) /* S0 */
# define REG_S1 (ARM_CONTEXT_REGS+1) /* S1 */
# define REG_D1 (ARM_CONTEXT_REGS+2) /* D1 */
# define REG_S2 (ARM_CONTEXT_REGS+2) /* S2 */
# define REG_S3 (ARM_CONTEXT_REGS+3) /* S3 */
# define REG_D2 (ARM_CONTEXT_REGS+4) /* D2 */
# define REG_S4 (ARM_CONTEXT_REGS+4) /* S4 */
# define REG_S5 (ARM_CONTEXT_REGS+5) /* S5 */
# define REG_D3 (ARM_CONTEXT_REGS+6) /* D3 */
# define REG_S6 (ARM_CONTEXT_REGS+6) /* S6 */
# define REG_S7 (ARM_CONTEXT_REGS+7) /* S7 */
# define REG_D4 (ARM_CONTEXT_REGS+8) /* D4 */
# define REG_S8 (ARM_CONTEXT_REGS+8) /* S8 */
# define REG_S9 (ARM_CONTEXT_REGS+9) /* S9 */
# define REG_D5 (ARM_CONTEXT_REGS+10) /* D5 */
# define REG_S10 (ARM_CONTEXT_REGS+10) /* S10 */
# define REG_S11 (ARM_CONTEXT_REGS+11) /* S11 */
# define REG_D6 (ARM_CONTEXT_REGS+12) /* D6 */
# define REG_S12 (ARM_CONTEXT_REGS+12) /* S12 */
# define REG_S13 (ARM_CONTEXT_REGS+13) /* S13 */
# define REG_D7 (ARM_CONTEXT_REGS+14) /* D7 */
# define REG_S14 (ARM_CONTEXT_REGS+14) /* S14 */
# define REG_S15 (ARM_CONTEXT_REGS+15) /* S15 */
# define REG_D8 (ARM_CONTEXT_REGS+16) /* D8 */
# define REG_S16 (ARM_CONTEXT_REGS+16) /* S16 */
# define REG_S17 (ARM_CONTEXT_REGS+17) /* S17 */
# define REG_D9 (ARM_CONTEXT_REGS+18) /* D9 */
# define REG_S18 (ARM_CONTEXT_REGS+18) /* S18 */
# define REG_S19 (ARM_CONTEXT_REGS+19) /* S19 */
# define REG_D10 (ARM_CONTEXT_REGS+20) /* D10 */
# define REG_S20 (ARM_CONTEXT_REGS+20) /* S20 */
# define REG_S21 (ARM_CONTEXT_REGS+21) /* S21 */
# define REG_D11 (ARM_CONTEXT_REGS+22) /* D11 */
# define REG_S22 (ARM_CONTEXT_REGS+22) /* S22 */
# define REG_S23 (ARM_CONTEXT_REGS+23) /* S23 */
# define REG_D12 (ARM_CONTEXT_REGS+24) /* D12 */
# define REG_S24 (ARM_CONTEXT_REGS+24) /* S24 */
# define REG_S25 (ARM_CONTEXT_REGS+25) /* S25 */
# define REG_D13 (ARM_CONTEXT_REGS+26) /* D13 */
# define REG_S26 (ARM_CONTEXT_REGS+26) /* S26 */
# define REG_S27 (ARM_CONTEXT_REGS+27) /* S27 */
# define REG_D14 (ARM_CONTEXT_REGS+28) /* D14 */
# define REG_S28 (ARM_CONTEXT_REGS+28) /* S28 */
# define REG_S29 (ARM_CONTEXT_REGS+29) /* S29 */
# define REG_D15 (ARM_CONTEXT_REGS+30) /* D15 */
# define REG_S30 (ARM_CONTEXT_REGS+30) /* S30 */
# define REG_S31 (ARM_CONTEXT_REGS+31) /* S31 */
# define REG_FPSCR (ARM_CONTEXT_REGS+32) /* Floating point status and control */
# define FPU_CONTEXT_REGS (33)
#else
# define FPU_CONTEXT_REGS (0)
#endif
/* The total number of registers saved by software */
#define XCPTCONTEXT_REGS (ARM_CONTEXT_REGS + FPU_CONTEXT_REGS)
#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
/* Friendly register names */
#define REG_A1 REG_R0
#define REG_A2 REG_R1
#define REG_A3 REG_R2
#define REG_A4 REG_R3
#define REG_V1 REG_R4
#define REG_V2 REG_R5
#define REG_V3 REG_R6
#define REG_V4 REG_R7
#define REG_V5 REG_R8
#define REG_V6 REG_R9
#define REG_V7 REG_R10
#define REG_SB REG_R9
#define REG_SL REG_R10
#define REG_FP REG_R11
#define REG_IP REG_R12
#define REG_SP REG_R13
#define REG_LR REG_R14
#define REG_PC REG_R15
/* The PIC register is usually R10. It can be R9 is stack checking is enabled
* or if the user changes it with -mpic-register on the GCC command line.
*/
#define REG_PIC REG_R10
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/* This structure represents the return state from a system call */
#ifdef CONFIG_LIB_SYSCALL
struct xcpt_syscall_s
{
#ifdef CONFIG_BUILD_KERNEL
uint32_t cpsr; /* The CPSR value */
#endif
uint32_t sysreturn; /* The return PC */
};
#endif
/* This struct defines the way the registers are stored. We need to save:
*
* 1 CPSR
* 7 Static registers, v1-v7 (aka r4-r10)
* 1 Frame pointer, fp (aka r11)
* 1 Stack pointer, sp (aka r13)
* 1 Return address, lr (aka r14)
* ---
* 11 (XCPTCONTEXT_USER_REG)
*
* On interrupts, we also need to save:
* 4 Volatile registers, a1-a4 (aka r0-r3)
* 1 Scratch Register, ip (aka r12)
*---
* 5 (XCPTCONTEXT_IRQ_REGS)
*
* For a total of 17 (XCPTCONTEXT_REGS)
*/
#ifndef __ASSEMBLY__
struct xcptcontext
{
/* The following function pointer is non-zero if there are pending signals
* to be processed.
*/
#ifndef CONFIG_DISABLE_SIGNALS
void *sigdeliver; /* Actual type is sig_deliver_t */
/* These are saved copies of LR and CPSR used during signal processing. */
uint32_t saved_pc;
uint32_t saved_cpsr;
# ifdef CONFIG_BUILD_KERNEL
/* This is the saved address to use when returning from a user-space
* signal handler.
*/
uint32_t sigreturn;
# endif
#endif
/* Register save area */
uint32_t regs[XCPTCONTEXT_REGS];
/* Extra fault address register saved for common paging logic. In the
* case of the pre-fetch abort, this value is the same as regs[REG_R15];
* For the case of the data abort, this value is the value of the fault
* address register (FAR) at the time of data abort exception.
*/
#ifdef CONFIG_PAGING
uintptr_t far;
#endif
#ifdef CONFIG_LIB_SYSCALL
/* The following array holds the return address and the exc_return value
* needed to return from each nested system call.
*/
uint8_t nsyscalls;
struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
#endif
#ifdef CONFIG_ARCH_ADDRENV
#ifdef CONFIG_ARCH_STACK_DYNAMIC
/* This array holds the physical address of the level 2 page table used
* to map the thread's stack memory. This array will be initially of
* zeroed and would be back-up up with pages during page fault exception
* handling to support dynamically sized stacks for each thread.
*/
FAR uintptr_t *ustack[ARCH_STACK_NSECTS];
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
/* In this configuration, all syscalls execute from an internal kernel
* stack. Why? Because when we instantiate and initialize the address
* environment of the new user process, we will temporarily lose the
* address environment of the old user process, including its stack
* contents. The kernel C logic will crash immediately with no valid
* stack in place.
*/
FAR uint32_t *ustkptr; /* Saved user stack pointer */
FAR uint32_t *kstack; /* Allocate base of the (aligned) kernel stack */
#ifndef CONFIG_DISABLE_SIGNALS
FAR uint32_t *kstkptr; /* Saved kernel stack pointer */
#endif
#endif
#endif
};
#endif
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Inline functions
****************************************************************************/
#ifndef __ASSEMBLY__
/* Return the current IRQ state */
static inline irqstate_t irqstate(void)
{
unsigned int cpsr;
__asm__ __volatile__
(
"\tmrs %0, cpsr\n"
: "=r" (cpsr)
:
: "memory"
);
return cpsr;
}
/* Disable IRQs and return the previous IRQ state */
static inline irqstate_t irqsave(void)
{
unsigned int cpsr;
__asm__ __volatile__
(
"\tmrs %0, cpsr\n"
"\tcpsid i\n"
#if defined(CONFIG_ARMV7A_DECODEFIQ)
"\tcpsid f\n"
#endif
: "=r" (cpsr)
:
: "memory"
);
return cpsr;
}
/* Enable IRQs and return the previous IRQ state */
static inline irqstate_t irqenable(void)
{
unsigned int cpsr;
__asm__ __volatile__
(
"\tmrs %0, cpsr\n"
"\tcpsie i\n"
#if defined(CONFIG_ARMV7A_DECODEFIQ)
"\tcpsie f\n"
#endif
: "=r" (cpsr)
:
: "memory"
);
return cpsr;
}
/* Restore saved IRQ & FIQ state */
static inline void irqrestore(irqstate_t flags)
{
__asm__ __volatile__
(
"msr cpsr_c, %0"
:
: "r" (flags)
: "memory"
);
}
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_ARMV7_R_IRQ_H */
arch/arm/include/armv7-r/syscall.h
+243
View File
@@ -0,0 +1,243 @@
/****************************************************************************
* arch/arm/include/armv7-r/syscall.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through include/syscall.h or include/sys/sycall.h
*/
#ifndef __ARCH_ARM_INCLUDE_ARMV7_R_SYSCALL_H
#define __ARCH_ARM_INCLUDE_ARMV7_R_SYSCALL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define SYS_syscall 0x900001
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Inline functions
****************************************************************************/
#ifndef __ASSEMBLY__
/* SVC with SYS_ call number and no parameters */
static inline uintptr_t sys_call0(unsigned int nbr)
{
register long reg0 __asm__("r0") = (long)(nbr);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0)
: "memory", "r14"
);
return reg0;
}
/* SVC with SYS_ call number and one parameter */
static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1)
: "memory", "r14"
);
return reg0;
}
/* SVC with SYS_ call number and two parameters */
static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2)
: "memory", "r14"
);
return reg0;
}
/* SVC with SYS_ call number and three parameters */
static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3)
: "memory", "r14"
);
return reg0;
}
/* SVC with SYS_ call number and four parameters */
static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3,
uintptr_t parm4)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4)
: "memory", "r14"
);
return reg0;
}
/* SVC with SYS_ call number and five parameters */
static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3,
uintptr_t parm4, uintptr_t parm5)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg5 __asm__("r5") = (long)(parm5);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4), "r"(reg5)
: "memory", "r14"
);
return reg0;
}
/* SVC with SYS_ call number and six parameters */
static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1,
uintptr_t parm2, uintptr_t parm3,
uintptr_t parm4, uintptr_t parm5,
uintptr_t parm6)
{
register long reg0 __asm__("r0") = (long)(nbr);
register long reg6 __asm__("r6") = (long)(parm6);
register long reg5 __asm__("r5") = (long)(parm5);
register long reg4 __asm__("r4") = (long)(parm4);
register long reg3 __asm__("r3") = (long)(parm3);
register long reg2 __asm__("r2") = (long)(parm2);
register long reg1 __asm__("r1") = (long)(parm1);
__asm__ __volatile__
(
"svc %1"
: "=r"(reg0)
: "i"(SYS_syscall), "r"(reg0), "r"(reg1), "r"(reg2),
"r"(reg3), "r"(reg4), "r"(reg5), "r"(reg6)
: "memory", "r14"
);
return reg0;
}
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_ARMV7_R_SYSCALL_H */
arch/arm/include/irq.h
+5 -1
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/include/irq.h
*
* Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2009, 2011, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -58,6 +58,10 @@
#if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8)
# include <arch/armv7-a/irq.h>
#elif defined(CONFIG_ARCH_CORTEXR4) || defined(CONFIG_ARCH_CORTEXR4F) || \
defined(CONFIG_ARCH_CORTEXR5) || defined(CONFIG_ARCH_CORTEXR5F) || \
defined(CONFIG_ARCH_CORTEXR7) || defined(CONFIG_ARCH_CORTEXR7F)
# include <arch/armv7-r/irq.h>
#elif defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) || \
defined(CONFIG_ARCH_CORTEXM7)
# include <arch/armv7-m/irq.h>
arch/arm/include/tms570/chip.h
+361
View File
@@ -0,0 +1,361 @@
/****************************************************************************************************
* arch/arm/include/tms570/chip.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_TMS570_CHIP_H
#define __ARCH_ARM_INCLUDE_TMS570_CHIP_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* TMS570LS0432PZ TMS570LS0332PZ TMS570LS0232PZ
* Package 100 QFP 100 QFP 100 QFP
* CPU ARM Cortex-R4 ARM Cortex-R4 ARM Cortex-R4
* Frequency (MHz) 80 80 80
* Flash (KB) 384 256 128
* RAM (KB) 32 32 32
* Data Flash (KB) 16 16 16
* EMAC – – –
* FlexRay – – –
* CAN 2 2 2
* MibADC (CH) 1 (16) 1 (16) 1 (16)
* N2HET (Ch) 1 (19) 1 (19) 1 (19)
* ePWM Channels – – –
* eCAP Channels 0 0 0
* eQEP Channels 1 1 1
* MibSPI (CS) 1 (4) 1 (4) 1 (4)
* SPI (CS) 2 2 2
* SCI (LIN) 1 (1) 1 (1) 1 (1)
* I2C – – –
* GPIO (INT) 45 (8) 45 (9) 45 (8)
* EMIF – – –
* ETM (Trace) – – –
* RTP/DMM – – –
*/
#if defined(CONFIG_ARCH_CHIP_TMS570LS0232PZ)
# define TMS570_CORTEX_R4 1 /* Cortex-R4 family */
# undef TMS570_CORTEX_R4F /* Not Cortex-R4F family */
# undef TMS570_CORTEX_R5 /* Not Cortex-R5 family */
# undef TMS570_CORTEX_R5F /* Not Cortex-R5F family */
# undef TMS570_CORTEX_R7 /* Not Cortex-R7 family */
# undef TMS570_CORTEX_R7F /* Not Cortex-R7F family */
# define TMS570_PFLASH (128*2014) /* 128 KB Program FLASH */
# define TMS570_SRAM (32*1024) /* 32 KB SRAM */
# define TMS570_DFLASH (16*1024) /* 16 KB Data FLASH (EEPROM) */
# define TMS570_NEMAC 0 /* No 10/100 Mbit EMAC */
# define TMS570_FLEXRAY_NCH 0 /* No Flexray channels */
# define TMS570_NCAN 2 /* Two CAN */
# define TMS570_NMIBADC 1 /* One MiBADC */
# define TMS570_MIBADC_NCH 16 /* 16 MibADC channels */
# define TMS570_NN2HET 1 /* One N2HET */
# define TMS570_N2HET_NCH 19 /* 19 N2HET channels */
# define TMS570_EPWM_NCH 0 /* No ePWM channels */
# define TMS570_ECAP_NCH 0 /* No eCAP channels */
# define TMS570_EQEP_NCH 1 /* One eQEP channel */
# define TMS570_NMIBSPI 1 /* One MibSPI */
# define TMS570_MIBSPI1_NCS 4 /* MibSPI1: 4 chip selects */
# define TMS570_MIBSPI2_NCS 0 /* MibSPI2: No chip selects */
# define TMS570_MIBSPI3_NCS 0 /* MibSPI3: No chip selects */
# define TMS570_NSPI 2 /* Two SPI */
# define TMS570_SPI1_NCS 0 /* SPI1: No chip selects */
# define TMS570_SPI2_NCS 0 /* SPI2: No chip selects */
# define TMS570_NSCI 1 /* One SCI */
# define TMS570_SCI1_LIN 1 /* SCI1: LIN supported */
# undef TMS570_SCI2_LIN /* SCI2: LIN not supported */
# define TMS570_NI2C 0 /* No I2C */
# define TMS570_NGPIOINT 8 /* 8 GPIO interrupts */
# define TMS570_NEMIF16 0 /* No EMIF 16-bit data */
# undef TMS570_ETM /* No ETM (trace) */
# undef TMS570_RTP /* No RAM trace port (RTP) */
# undef TMS570_DMM /* No DMM */
#elif defined(CONFIG_ARCH_CHIP_TMS570LS0332PZ)
# define TMS570_CORTEX_R4 1 /* Cortex-R4 family */
# undef TMS570_CORTEX_R4F /* Not Cortex-R4F family */
# undef TMS570_CORTEX_R5 /* Not Cortex-R5 family */
# undef TMS570_CORTEX_R5F /* Not Cortex-R5F family */
# undef TMS570_CORTEX_R7 /* Not Cortex-R7 family */
# undef TMS570_CORTEX_R7F /* Not Cortex-R7F family */
# define TMS570_PFLASH (256*2014) /* 256 KB Program FLASH */
# define TMS570_SRAM (32*1024) /* 32 KB SRAM */
# define TMS570_DFLASH (16*1024) /* 16 KB Data FLASH (EEPROM) */
# define TMS570_NEMAC 0 /* No 10/100 Mbit EMAC */
# define TMS570_FLEXRAY_NCH 0 /* No Flexray channels */
# define TMS570_NCAN 2 /* Two CAN */
# define TMS570_NMIBADC 1 /* One MiBADC */
# define TMS570_MIBADC_NCH 16 /* 16 MibADC channels */
# define TMS570_NN2HET 1 /* One N2HET */
# define TMS570_N2HET_NCH 19 /* 19 N2HET channels */
# define TMS570_EPWM_NCH 0 /* No ePWM channels */
# define TMS570_ECAP_NCH 0 /* No eCAP channels */
# define TMS570_EQEP_NCH 1 /* One eQEP channel */
# define TMS570_NMIBSPI 1 /* One MibSPI */
# define TMS570_MIBSPI1_NCS 4 /* MibSPI1: 4 chip selects */
# define TMS570_MIBSPI2_NCS 0 /* MibSPI2: No chip selects */
# define TMS570_MIBSPI3_NCS 0 /* MibSPI3: No chip selects */
# define TMS570_NSPI 2 /* Two SPI */
# define TMS570_SPI1_NCS 0 /* SPI1: No chip selects */
# define TMS570_SPI2_NCS 0 /* SPI2: No chip selects */
# define TMS570_NSCI 1 /* One SCI */
# define TMS570_SCI1_LIN 1 /* SCI1: LIN supported */
# undef TMS570_SCI2_LIN /* SCI2: LIN not supported */
# define TMS570_NI2C 0 /* No I2C */
# define TMS570_NGPIOINT 9 /* 9 GPIO interrupts */
# define TMS570_NEMIF16 0 /* No EMIF 16-bit data */
# undef TMS570_ETM /* No ETM (trace) */
# undef TMS570_RTP /* No RAM trace port (RTP) */
# undef TMS570_DMM /* No DMM */
#elif defined(CONFIG_ARCH_CHIP_TMS570LS0432PZ)
# define TMS570_CORTEX_R4 1 /* Cortex-R4 family */
# undef TMS570_CORTEX_R4F /* Not Cortex-R4F family */
# undef TMS570_CORTEX_R5 /* Not Cortex-R5 family */
# undef TMS570_CORTEX_R5F /* Not Cortex-R5F family */
# undef TMS570_CORTEX_R7 /* Not Cortex-R7 family */
# undef TMS570_CORTEX_R7F /* Not Cortex-R7F family */
# define TMS570_PFLASH (384*2014) /* 384 KB Program FLASH */
# define TMS570_SRAM (32*1024) /* 32 KB SRAM */
# define TMS570_DFLASH (16*1024) /* 16 KB Data FLASH (EEPROM) */
# define TMS570_NEMAC 0 /* No 10/100 Mbit EMAC */
# define TMS570_FLEXRAY_NCH 0 /* No Flexray channels */
# define TMS570_NCAN 2 /* Two CAN */
# define TMS570_NMIBADC 1 /* One MiBADC */
# define TMS570_MIBADC_NCH 16 /* 16 MibADC channels */
# define TMS570_NN2HET 1 /* One N2HET */
# define TMS570_N2HET_NCH 19 /* 19 N2HET channels */
# define TMS570_EPWM_NCH 0 /* No ePWM channels */
# define TMS570_ECAP_NCH 0 /* No eCAP channels */
# define TMS570_EQEP_NCH 1 /* One eQEP channel */
# define TMS570_NMIBSPI 1 /* One MibSPI */
# define TMS570_MIBSPI1_NCS 4 /* MibSPI1: 4 chip selects */
# define TMS570_MIBSPI2_NCS 0 /* MibSPI2: No chip selects */
# define TMS570_MIBSPI3_NCS 0 /* MibSPI3: No chip selects */
# define TMS570_NSPI 2 /* Two SPI */
# define TMS570_SPI1_NCS 0 /* SPI1: No chip selects */
# define TMS570_SPI2_NCS 0 /* SPI2: No chip selects */
# define TMS570_NSCI 1 /* One SCI */
# define TMS570_SCI1_LIN 1 /* SCI1: LIN supported */
# undef TMS570_SCI2_LIN /* SCI2: LIN not supported */
# define TMS570_NI2C 0 /* No I2C */
# define TMS570_NGPIOINT 8 /* 8 GPIO interrupts */
# define TMS570_NEMIF16 0 /* No EMIF 16-bit data */
# undef TMS570_ETM /* No ETM (trace) */
# undef TMS570_RTP /* No RAM trace port (RTP) */
# undef TMS570_DMM /* No DMM */
/* TMS570LS1227ZWT TMS570LS0714ZWT TMS570LS0714PGE TMS570LS0714PZ
* Package 337 BGA 337 BGA 144 QFP 100 QFP
* CPU ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F
* Frequency (MHz) 180 180 160 100
* Flash (KB) 1280 768 768 768
* RAM (KB) 192 128 128 128
* Data Flash (KB) 64 64 64 64
* EMAC 10/100 – – –
* FlexRay 2-ch – – –
* CAN 3 3 3 2
* MibADC (CH) 2 (24) 2 (24) 2 (24) 2 (16)
* N2HET (Ch) 2 (44) 2 (44) 2 (40) 2 (21)
* ePWM Channels 14 14 14 8
* eCAP Channels 6 6 6 4
* eQEP Channels 2 2 2 1
* MibSPI (CS) 3 (6+6+4) 3 (6+6+4) 3 (5+6+4) 2 (5+1)
* SPI (CS) 2 (2+1) 2 (2+1) 1 (1) 1 (1)
* SCI (LIN) 2 (1) 2 (1) 2 (1) 1 (1)
* I2C 1 1 1 –
* GPIO (INT) 101 (16) 101 (16) 64 (10) 45 (9)
* EMIF 16-bit data – – –
* ETM (Trace) – – – –
* RTP/DMM – – – –
*/
#elif defined(CONFIG_ARCH_CHIP_TMS570LS0714PZ)
# undef TMS570_CORTEX_R4 /* Not Cortex-R4 family */
# define TMS570_CORTEX_R4F 1 /* Cortex-R4F family */
# undef TMS570_CORTEX_R5 /* Not Cortex-R5 family */
# undef TMS570_CORTEX_R5F /* Not Cortex-R5F family */
# undef TMS570_CORTEX_R7 /* Not Cortex-R7 family */
# undef TMS570_CORTEX_R7F /* Not Cortex-R7F family */
# define TMS570_PFLASH (768*2014) /* 768 KB Program FLASH */
# define TMS570_SRAM (128*1024) /* 128 KB SRAM */
# define TMS570_DFLASH (64*1024) /* 64 KB Data FLASH (EEPROM) */
# define TMS570_NEMAC 0 /* No 10/100 Mbit EMAC */
# define TMS570_FLEXRAY_NCH 0 /* No Flexray channels */
# define TMS570_NCAN 3 /* Three CAN */
# define TMS570_NMIBADC 2 /* Two MiBADC */
# define TMS570_MIBADC_NCH 16 /* 16 MibADC channels */
# define TMS570_NN2HET 2 /* Two N2HET */
# define TMS570_N2HET_NCH 21 /* 21 N2HET channels */
# define TMS570_EPWM_NCH 8 /* 8 ePWM channels */
# define TMS570_ECAP_NCH 4 /* 4 eCAP channels */
# define TMS570_EQEP_NCH 1 /* 1 eQEP channels */
# define TMS570_NMIBSPI 2 /* 2 MibSPI */
# define TMS570_MIBSPI1_NCS 5 /* MibSPI1: 5 chip selects */
# define TMS570_MIBSPI2_NCS 1 /* MibSPI2: 1 chip selects */
# define TMS570_MIBSPI3_NCS 0 /* MibSPI3: No chip selects */
# define TMS570_NSPI 1 /* One SPI */
# define TMS570_SPI1_NCS 1 /* SPI1: One chip selects */
# define TMS570_SPI2_NCS 0 /* SPI2: No chip selects */
# define TMS570_NSCI 1 /* One SCI */
# define TMS570_SCI1_LIN 1 /* SCI1: LIN supported */
# undef TMS570_SCI2_LIN /* SCI2: LIN not supported */
# define TMS570_NI2C 0 /* No I2C */
# define TMS570_NGPIOINT 9 /* 9 GPIO interrupts */
# define TMS570_NEMIF16 0 /* No EMIF 16-bit data */
# undef TMS570_ETM /* No ETM (trace) */
# undef TMS570_RTP /* No RAM trace port (RTP) */
# undef TMS570_DMM /* No DMM */
#elif defined(CONFIG_ARCH_CHIP_TMS570LS0714PGE)
# undef TMS570_CORTEX_R4 /* Not Cortex-R4 family */
# define TMS570_CORTEX_R4F 1 /* Cortex-R4F family */
# undef TMS570_CORTEX_R5 /* Not Cortex-R5 family */
# undef TMS570_CORTEX_R5F /* Not Cortex-R5F family */
# undef TMS570_CORTEX_R7 /* Not Cortex-R7 family */
# undef TMS570_CORTEX_R7F /* Not Cortex-R7F family */
# define TMS570_PFLASH (768*2014) /* 768 KB Program FLASH */
# define TMS570_SRAM (128*1024) /* 128 KB SRAM */
# define TMS570_DFLASH (64*1024) /* 64 KB Data FLASH (EEPROM) */
# define TMS570_NEMAC 0 /* No 10/100 Mbit EMAC */
# define TMS570_FLEXRAY_NCH 0 /* No Flexray channels */
# define TMS570_NCAN 3 /* Three CAN */
# define TMS570_NMIBADC 2 /* Two MiBADC */
# define TMS570_MIBADC_NCH 24 /* 24 MibADC channels */
# define TMS570_NN2HET 2 /* Two N2HET */
# define TMS570_N2HET_NCH 40 /* 40 N2HET channels */
# define TMS570_EPWM_NCH 14 /* 14 ePWM channels */
# define TMS570_ECAP_NCH 6 /* 6 eCAP channels */
# define TMS570_EQEP_NCH 2 /* 2 eQEP channels */
# define TMS570_NMIBSPI 3 /* 3 MibSPI */
# define TMS570_MIBSPI1_NCS 5 /* MibSPI1: 5 chip selects */
# define TMS570_MIBSPI2_NCS 6 /* MibSPI2: 6 chip selects */
# define TMS570_MIBSPI3_NCS 4 /* MibSPI3: 4 chip selects */
# define TMS570_NSPI 1 /* One SPI */
# define TMS570_SPI1_NCS 1 /* SPI1: One chip selects */
# define TMS570_SPI2_NCS 0 /* SPI2: No chip selects */
# define TMS570_NSCI 2 /* Two SCI */
# define TMS570_SCI1_LIN 1 /* SCI1: LIN supported */
# undef TMS570_SCI2_LIN /* SCI2: LIN not supported */
# define TMS570_NI2C 1 /* One I2C */
# define TMS570_NGPIOINT 10 /* 16 GPIO interrupts */
# define TMS570_NEMIF16 0 /* No EMIF 16-bit data */
# undef TMS570_ETM /* No ETM (trace) */
# undef TMS570_RTP /* No RAM trace port (RTP) */
# undef TMS570_DMM /* No DMM */
#elif defined(CONFIG_ARCH_CHIP_TMS570LS0714ZWT)
# undef TMS570_CORTEX_R4 /* Not Cortex-R4 family */
# define TMS570_CORTEX_R4F 1 /* Cortex-R4F family */
# undef TMS570_CORTEX_R5 /* Not Cortex-R5 family */
# undef TMS570_CORTEX_R5F /* Not Cortex-R5F family */
# undef TMS570_CORTEX_R7 /* Not Cortex-R7 family */
# undef TMS570_CORTEX_R7F /* Not Cortex-R7F family */
# define TMS570_PFLASH (768*2014) /* 768 KB Program FLASH */
# define TMS570_SRAM (128*1024) /* 128 KB SRAM */
# define TMS570_DFLASH (64*1024) /* 64 KB Data FLASH (EEPROM) */
# define TMS570_NEMAC 0 /* No 10/100 Mbit EMAC */
# define TMS570_FLEXRAY_NCH 0 /* No Flexray channels */
# define TMS570_NCAN 3 /* Three CAN */
# define TMS570_NMIBADC 2 /* Two MiBADC */
# define TMS570_MIBADC_NCH 24 /* 24 MibADC channels */
# define TMS570_NN2HET 2 /* Two N2HET */
# define TMS570_N2HET_NCH 44 /* 44 N2HET channels */
# define TMS570_EPWM_NCH 14 /* 14 ePWM channels */
# define TMS570_ECAP_NCH 6 /* 6 eCAP channels */
# define TMS570_EQEP_NCH 2 /* 2 eQEP channels */
# define TMS570_NMIBSPI 3 /* 3 MibSPI */
# define TMS570_MIBSPI1_NCS 6 /* MibSPI1: 6 chip selects */
# define TMS570_MIBSPI2_NCS 6 /* MibSPI2: 6 chip selects */
# define TMS570_MIBSPI3_NCS 4 /* MibSPI3: 4 chip selects */
# define TMS570_NSPI 2 /* Two SPI */
# define TMS570_SPI1_NCS 2 /* SPI1: Two chip selects */
# define TMS570_SPI2_NCS 1 /* SPI2: One chip selects */
# define TMS570_NSCI 2 /* Two SCI */
# define TMS570_SCI1_LIN 1 /* SCI1: LIN supported */
# undef TMS570_SCI2_LIN /* SCI2: LIN not supported */
# define TMS570_NI2C 1 /* One I2C */
# define TMS570_NGPIOINT 16 /* 16 GPIO interrupts */
# define TMS570_NEMIF16 0 /* No EMIF 16-bit data */
# undef TMS570_ETM /* No ETM (trace) */
# undef TMS570_RTP /* No RAM trace port (RTP) */
# undef TMS570_DMM /* No DMM */
#elif defined(CONFIG_ARCH_CHIP_TMS570LS1227ZWT)
# undef TMS570_CORTEX_R4 /* Not Cortex-R4 family */
# define TMS570_CORTEX_R4F 1 /* Cortex-R4F family */
# undef TMS570_CORTEX_R5 /* Not Cortex-R5 family */
# undef TMS570_CORTEX_R5F /* Not Cortex-R5F family */
# undef TMS570_CORTEX_R7 /* Not Cortex-R7 family */
# undef TMS570_CORTEX_R7F /* Not Cortex-R7F family */
# define TMS570_PFLASH (1280*2014) /* 1,280 KB Program FLASH */
# define TMS570_SRAM (192*1024) /* 192 KB SRAM */
# define TMS570_DFLASH (64*1024) /* 64 KB Data FLASH (EEPROM) */
# define TMS570_NEMAC 1 /* One 10/100 Mbit EMAC */
# define TMS570_FLEXRAY_NCH 2 /* Two Flexray channels */
# define TMS570_NCAN 3 /* Three CAN */
# define TMS570_NMIBADC 2 /* Two MiBADC */
# define TMS570_MIBADC_NCH 24 /* 24 MibADC channels */
# define TMS570_NN2HET 2 /* Two N2HET */
# define TMS570_N2HET_NCH 44 /* 44 N2HET channels */
# define TMS570_EPWM_NCH 14 /* 14 ePWM channels */
# define TMS570_ECAP_NCH 6 /* 6 eCAP channels */
# define TMS570_EQEP_NCH 2 /* 2 eQEP channels */
# define TMS570_NMIBSPI 3 /* 3 MibSPI */
# define TMS570_MIBSPI1_NCS 6 /* MibSPI1: 6 chip selects */
# define TMS570_MIBSPI2_NCS 6 /* MibSPI2: 6 chip selects */
# define TMS570_MIBSPI3_NCS 4 /* MibSPI3: 4 chip selects */
# define TMS570_NSPI 2 /* Two SPI */
# define TMS570_SPI1_NCS 2 /* SPI1: Two chip selects */
# define TMS570_SPI2_NCS 1 /* SPI2: One chip selects */
# define TMS570_NSCI 2 /* Two SCI */
# define TMS570_SCI1_LIN 1 /* SCI1: LIN supported */
# undef TMS570_SCI2_LIN /* SCI2: LIN not supported */
# define TMS570_NI2C 1 /* One I2C */
# define TMS570_NGPIOINT 16 /* 16 GPIO interrupts */
# define TMS570_NEMIF16 1 /* One EMIF 16-bit data */
# undef TMS570_ETM /* No ETM (trace) */
# undef TMS570_RTP /* No RAM trace port (RTP) */
# undef TMS570_DMM /* No DMM */
#else
# error Unrecognized TMS570 chip
#endif
#endif /* __ARCH_ARM_INCLUDE_TMS570_CHIP_H */
arch/arm/include/tms570/irq.h
+94
View File
@@ -0,0 +1,94 @@
/****************************************************************************************
* arch/arm/include/tms570/irq.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through
* nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_TMS570_IRQ_H
#define __ARCH_ARM_INCLUDE_TMS570_IRQ_H
/****************************************************************************************
* Included Files
****************************************************************************************/
#include <nuttx/config.h>
#include <arch/tms570/chip.h>
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* The interrupt vector table only has 96 entries, one phantom vector and 95 interrupt
* channels. Channel 95 does not have a dedicated vector and shall not be used.
*/
#define TMS570_IRQ_PHANTOM 0 /* The first is the "phantom" interrupt */
#define TMS570_IRQ_NCHANNELS 95 /* The "phantom" vector is followed by 95 real
* interrupt channels */
/* Total number of IRQ numbers */
#define NR_IRQS (95) /* Zero corresponds to channel 0, vector 1 */
/****************************************************************************************
* Public Types
****************************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************************
* Public Data
****************************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************************
* Public Function Prototypes
****************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_TMS570_IRQ_H */
arch/arm/src/Makefile
+12
View File
@@ -40,6 +40,18 @@ ifeq ($(CONFIG_ARCH_CORTEXA5),y) # Cortex-A5 is ARMv7-A
ARCH_SUBDIR = armv7-a
else ifeq ($(CONFIG_ARCH_CORTEXA8),y) # Cortex-A8 is ARMv7-A
ARCH_SUBDIR = armv7-a
else ifeq ($(CONFIG_ARCH_CORTEXR4),y) # Cortex-R4 is ARMv7-R
ARCH_SUBDIR = armv7-r
else ifeq ($(CONFIG_ARCH_CORTEXR4F),y) # Cortex-R4F is ARMv7-R
ARCH_SUBDIR = armv7-r
else ifeq ($(CONFIG_ARCH_CORTEXR5),y) # Cortex-R5 is ARMv7-R
ARCH_SUBDIR = armv7-r
else ifeq ($(CONFIG_ARCH_CORTEXR5F),y) # Cortex-R5F is ARMv7-R
ARCH_SUBDIR = armv7-r
else ifeq ($(CONFIG_ARCH_CORTEXR7),y) # Cortex-R7 is ARMv7-R
ARCH_SUBDIR = armv7-r
else ifeq ($(CONFIG_ARCH_CORTEXR7F),y) # Cortex-R7F is ARMv7-R
ARCH_SUBDIR = armv7-r
else ifeq ($(CONFIG_ARCH_CORTEXM3),y) # Cortex-M3 is ARMv7-M
ARCH_SUBDIR = armv7-m
else ifeq ($(CONFIG_ARCH_CORTEXM4),y) # Cortex-M4 is ARMv7E-M
arch/arm/src/a1x/Make.defs
+2
View File
@@ -112,6 +112,8 @@ endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += arm_elf.c arm_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += arm_elf.c arm_coherent_dcache.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
arch/arm/src/armv7-a/arm_coherent_dcache.c
+2 -2
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/armv7/up_coherent_dcache.c
* arch/arm/src/armv7-a/up_coherent_dcache.c
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -44,7 +44,7 @@
#include "cp15_cacheops.h"
#include <nuttx/binfmt/elf.h>
#include <nuttx/arch.h>
/****************************************************************************
* Pre-processor Definitions
arch/arm/src/armv7-a/arm_copyarmstate.c
+1 -13
View File
@@ -47,18 +47,6 @@
#ifdef CONFIG_ARCH_FPU
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -76,7 +64,7 @@ void up_copyarmstate(uint32_t *dest, uint32_t *src)
{
int i;
/* In the Cortex-M model, the state is copied from the stack to the TCB,
/* In the Cortex-A model, the state is copied from the stack to the TCB,
* but only a reference is passed to get the state from the TCB. So the
* following check avoids copying the TCB save area onto itself:
*/
arch/arm/src/armv7-a/arm_head.S
+7 -4
View File
@@ -54,10 +54,13 @@
* Configuration
**********************************************************************************/
#undef ALIGNMENT_TRAP
/* Hard-coded options */
#undef CPU_ALIGNMENT_TRAP
#undef CPU_CACHE_ROUND_ROBIN
#undef CPU_DCACHE_DISABLE
#undef CPU_ICACHE_DISABLE
#undef CPU_AFE_ENABLE
/* There are three operational memory configurations:
*
@@ -465,7 +468,7 @@ __start:
orr r0, r0, #(SCTLR_I)
#endif
#ifdef ALIGNMENT_TRAP
#ifdef CPU_ALIGNMENT_TRAP
/* Alignment abort enable
*
* SCTLR_A Bit 1: Strict alignment enabled
@@ -474,7 +477,7 @@ __start:
orr r0, r0, #(SCTLR_A)
#endif
#ifdef CONFIG_AFE_ENABLE
#ifdef CPU_AFE_ENABLE
/* AP[0:2] Permissions model
*
* SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value).
@@ -613,7 +616,7 @@ __start:
/* Set up the stack pointer and clear the frame pointer */
ldr sp, .Lstackpointer
mov fp, #0
mov fp, #0
#ifndef CONFIG_BOOT_SDRAM_DATA
/* Initialize .bss and .data ONLY if .bss and .data lie in SRAM that is
arch/arm/src/armv7-a/arm_memcpy.S
-3
View File
@@ -60,7 +60,6 @@
.global memcpy
.syntax unified
.thumb
.file "arm_memcpy.S"
@@ -149,7 +148,6 @@ MEM_LongCopyTable:
************************************************************************************/
.align 4
.thumb_func
memcpy:
push {r14}
@@ -160,7 +158,6 @@ memcpy:
.align 4
.thumb_func
_do_memcpy:
push {r14}
arch/arm/src/armv7-a/arm_pghead.S
+1 -1
View File
@@ -461,7 +461,7 @@ __start:
orr r0, r0, #(SCTLR_A)
#endif
#ifdef CONFIG_AFE_ENABLE
#ifdef CPU_AFE_ENABLE
/* AP[0:2] Permissions model
*
* SCTLR_AFE Bit 29: Full, legacy access permissions behavior (reset value).
arch/arm/src/armv7-a/arm_undefinedinsn.c
+1 -1
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/armv7/arm_undefinedinsn.c
* arch/arm/src/armv7-a/arm_undefinedinsn.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/armv7-a/cp15.h
+4 -4
View File
@@ -74,7 +74,7 @@
#define _CP15(op1,rd,crn,crm,op2) p15, op1, rd, crn, crm, op2
#define CP15_MIDR(r) _CP15(0, r, c0, c0, 0) /* Main ID Register */
#define CP15_TR(r) _CP15(0, r, c0, c0, 1) /* Cache Type Register */
#define CP15_CTR(r) _CP15(0, r, c0, c0, 1) /* Cache Type Register */
#define CP15_TCMTR(r) _CP15(0, r, c0, c0, 2) /* TCM Type Register */
#define CP15_TLBTR(r) _CP15(0, r, c0, c0, 3) /* TLB Type Register */
#define CP15_MPIDR(r) _CP15(0, r, c0, c0, 5) /* Multiprocessor Affinity Register */
@@ -158,10 +158,10 @@
#define CP15_TLBIASID(r,c) _CP15(0, r, c8, c, 2) /* Invalidate data TLB by ASID match. CRm = c5, c6, or c7 */
#define CP15_TLBIMVAA(r,c) _CP15(0, r, c8, c, 3) /* Invalidate unified TLB entry by MVA and ASID. CRm = c5, c6, or c7 */
#define CP15_MCR(r) _CP15(0, r, c9, c12, 0) /* Performance Monitor Control Register */
#define CP15_PMCR(r) _CP15(0, r, c9, c12, 0) /* Performance Monitor Control Register */
#define CP15_PMCNTENSET(r) _CP15(0, r, c9, c12, 1) /* Count Enable Set Register */
#define CP15_PMCNTENCLR(r) _CP15(0, r, c9, c12, 2) /* Count Enable Clear Register */
#define CP15_MOVSR(r) _CP15(0, r, c9, c12, 3) /* Overflow Flag Status Register */
#define CP15_PMOVSR(r) _CP15(0, r, c9, c12, 3) /* Overflow Flag Status Register */
#define CP15_PMSWINC(r) _CP15(0, r, c9, c12, 4) /* Software Increment Register */
#define CP15_PMSELR(r) _CP15(0, r, c9, c12, 5) /* Event Counter Selection Register */
#define CP15_PMCEID0(r) _CP15(0, r, c9, c12, 6) /* Common Event Identification Registers (Cortex-A5) */
@@ -169,7 +169,7 @@
#define CP15_PMCCNTR(r) _CP15(0, r, c9, c13, 0) /* Cycle Count Register */
#define CP15_PMXEVTYPER(r) _CP15(0, r, c9, c13, 1) /* Event Type Select Register */
#define CP15_PMCCFILTR(r) _CP15(0, r, c9, c13, 1) /* Cycle Count Filter Control Register */
#define CP15_MXEVCNTR(r) _CP15(0, r, c9, c13, 2) /* Event Count Registers (Cortex-A5) */
#define CP15_PMXEVCNTR(r) _CP15(0, r, c9, c13, 2) /* Event Count Registers (Cortex-A5) */
#define CP15_PMUSERENR(r) _CP15(0, r, c9, c14, 0) /* User Enable Register */
#define CP15_PMINTENSET(r) _CP15(0, r, c9, c14, 1) /* Interrupt Enable Set Register */
#define CP15_PMINTENCLR(r) _CP15(0, r, c9, c14, 2) /* Interrupt Enable Clear Register */
arch/arm/src/armv7-a/cp15_clean_dcache.S
+1 -1
View File
@@ -92,7 +92,7 @@
cp15_clean_dcache:
mrc CP15_TR(r3) /* Read the Cache Type Register */
mrc CP15_CTR(r3) /* Read the Cache Type Register */
lsr r3, r3, #16 /* Isolate the DMinLine field */
and r3, r3, #0xf
mov r2, #4
arch/arm/src/armv7-a/cp15_coherent_dcache.S
+2 -2
View File
@@ -93,7 +93,7 @@
.type cp15_coherent_dcache, function
cp15_coherent_dcache:
mrc CP15_TR(r3) /* Read the Cache Type Register */
mrc CP15_CTR(r3) /* Read the Cache Type Register */
lsr r3, r3, #16 /* Isolate the DMinLine field */
and r3, r3, #0xf
mov r2, #4
@@ -111,7 +111,7 @@ cp15_coherent_dcache:
dsb
mrc CP15_TR(r3) /* Read the Cache Type Register */
mrc CP15_CTR(r3) /* Read the Cache Type Register */
and r3, r3, #0xf /* Isolate the IminLine field */
mov r2, #4
mov r2, r2, lsl r3 /* Get the cache line size in bytes */
arch/arm/src/armv7-a/cp15_flush_dcache.S
+1 -1
View File
@@ -92,7 +92,7 @@
cp15_flush_dcache:
mrc CP15_TR(r3) /* Read the Cache Type Register */
mrc CP15_CTR(r3) /* Read the Cache Type Register */
lsr r3, r3, #16 /* Isolate the DMinLine field */
and r3, r3, #0xf
mov r2, #4
arch/arm/src/armv7-a/cp15_invalidate_dcache.S
+1 -1
View File
@@ -93,7 +93,7 @@
cp15_invalidate_dcache:
mrc CP15_TR(r3) /* Read the Cache Type Register */
mrc CP15_CTR(r3) /* Read the Cache Type Register */
lsr r3, r3, #16 /* Isolate the DMinLine field */
and r3, r3, #0xf
mov r2, #4
arch/arm/src/armv7-a/l2cc.h
-1
View File
@@ -1,6 +1,5 @@
/****************************************************************************
* arch/arm/src/armv7-a/l2cc.h
* Non-CP15 Registers
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/armv7-a/mmu.h
+1 -1
View File
@@ -342,7 +342,7 @@
* PL2 - Software executing in Hyp mode
*/
#ifdef CONFIG_AFE_ENABLE
#ifdef CPU_AFE_ENABLE
/* AP[2:1] access permissions model. AP[0] is used as an access flag:
*
* AP[2] AP[1] PL1 PL0 Description
arch/arm/src/armv7-a/svcall.h
+1 -1
View File
@@ -72,7 +72,7 @@
# endif
#endif
/* Cortex M3 system calls ***********************************************************/
/* Cortex-A system calls ************************************************************/
/* SYS call 0:
*
arch/arm/src/armv7-m/mpu.h
+12 -4
View File
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_CORTEXM_MPU_H
#define __ARCH_ARM_SRC_COMMON_CORTEXM_MPU_H
#ifndef __ARCH_ARM_SRC_ARMV7M_MPU_H
#define __ARCH_ARM_SRC_ARMV7M_MPU_H
/************************************************************************************
* Included Files
@@ -86,7 +86,15 @@
/* MPU Region Number Register Bit Definitions */
#define MPU_RNR_MASK (0xff)
#ifdef CONFIG_ARM_MPU_NREGIONS <= 8
# define MPU_RNR_MASK (0x00000007)
#elif CONFIG_ARM_MPU_NREGIONS <= 16
# define MPU_RNR_MASK (0x0000000f)
#elif CONFIG_ARM_MPU_NREGIONS <= 32
# define MPU_RNR_MASK (0x0000001f)
#else
# error "FIXME: Unsupported number of MPU regions"
#endif
/* MPU Region Base Address Register Bit Definitions */
@@ -570,5 +578,5 @@ static inline void mpu_peripheral(uintptr_t base, size_t size)
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_COMMON_CORTEXM_MPU_H */
#endif /* __ARCH_ARM_SRC_ARMV7M_MPU_H */
arch/arm/src/armv7-m/svcall.h
+1 -1
View File
@@ -72,7 +72,7 @@
# endif
#endif
/* Cortex M3 system calls ***********************************************************/
/* Cortex-M system calls ************************************************************/
/* SYS call 0:
*
arch/arm/src/armv7-m/up_coherent_dcache.c
+99
View File
@@ -0,0 +1,99 @@
/****************************************************************************
* arch/arm/src/armv7-m/up_coherent_dcache.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include "cache.h"
#include <nuttx/arch.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_coherent_dcache
*
* Description:
* Ensure that the I and D caches are coherent within specified region
* by cleaning the D cache (i.e., flushing the D cache contents to memory
* and invalidating the I cache. This is typically used when code has been
* written to a memory region, and will be executed.
*
* Input Parameters:
* addr - virtual start address of region
* len - Size of the address region in bytes
*
* Returned Value:
* None
*
****************************************************************************/
void up_coherent_dcache(uintptr_t addr, size_t len)
{
uintptr_t end;
if (len > 0)
{
/* Flush any dirtcy D-Cache lines to memory */
end = addr + len;
arch_clean_dcache(addr, end);
UNUSED(end);
/* Invalidate the entire I-Cache */
arch_invalidate_icache_all();
}
}
arch/arm/src/armv7-m/up_elf.c
-15
View File
@@ -48,20 +48,6 @@
#include <nuttx/arch.h>
#include <nuttx/binfmt/elf.h>
#ifdef CONFIG_ELF
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
@@ -498,4 +484,3 @@ int up_init_exidx(Elf32_Addr address, Elf32_Word size)
}
#endif
#endif /* CONFIG_ELF */
arch/arm/src/armv7-m/up_mpu.c
+3 -3
View File
@@ -50,8 +50,8 @@
****************************************************************************/
/* Configuration ************************************************************/
#ifndef CONFIG_ARMV7M_MPU_NREGIONS
# define CONFIG_ARMV7M_MPU_NREGIONS 8
#ifndef CONFIG_ARM_MPU_NREGIONS
# define CONFIG_ARM_MPU_NREGIONS 8
#endif
/****************************************************************************
@@ -210,7 +210,7 @@ static inline uint32_t mpu_subregion_ls(size_t offset, uint8_t l2size)
unsigned int mpu_allocregion(void)
{
DEBUGASSERT(g_region < CONFIG_ARMV7M_MPU_NREGIONS);
DEBUGASSERT(g_region < CONFIG_ARM_MPU_NREGIONS);
return (unsigned int)g_region++;
}
arch/arm/src/armv7-r/Kconfig
+180
View File
@@ -0,0 +1,180 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
comment "ARMv7-A Configuration Options"
config ARMV7R_MEMINIT
bool
default y if BOOT_SDRAM_DATA
default n if !BOOT_SDRAM_DATA
---help---
If this configuration *not* selected, then it is assumed that all
memory resources are initialized via arm_data_initialize() and
available at power-up reset time. Other memories, such as SDRAM or
some ECC SRAM memories, require some platform-specific
initialization first. In that case, this option should be selected
and the platform-specific implementation of arm_boot() must perform
the memory initialization first, then explicitly call
arm_data_initialize().
config ARMV7R_HAVE_L2CC
bool
default n
---help---
Selected by the configuration tool if the architecutre supports any
kind of L2 cache.
config ARMV7R_HAVE_L2CC_PL310
bool
default n
select ARMV7R_HAVE_L2CC
---help---
Set by architecture-specific code if the hardware supports a PL310
r3p2 L2 cache (only version r3p2 is supported).
if ARMV7R_HAVE_L2CC
menu "L2 Cache Configuration"
config ARMV7R_L2CC_PL310
bool "ARMv7-A L2CC P310 Support"
default n
depends on ARMV7R_HAVE_L2CC_PL310 && EXPERIMENTAL
select ARCH_L2CACHE
---help---
Enable the 2 Cache Controller (L2CC) is based on the L2CC-PL310 ARM
multi-way cache macrocell, version r3p2. The addition of an on-chip
secondary cache, also referred to as a Level 2 or L2 cache, is a
method of improving the system performance when significant memory
traffic is generated by the processor.
if ARCH_L2CACHE
if ARMV7R_L2CC_PL310
config PL310_LOCKDOWN_BY_MASTER
bool "PL310 Lockdown by Master"
default n
config PL310_LOCKDOWN_BY_LINE
bool "PL310 Lockdown by Line"
default n
config PL310_ADDRESS_FILTERING
bool "PL310 Address Filtering by Line"
default n
endif # ARMV7R_L2CC_PL310
choice
prompt "L2 Cache Associativity"
default ARMV7R_ASSOCIATIVITY_8WAY
depends on ARCH_L2CACHE
---help---
This choice specifies the associativity of L2 cache in terms of the
number of ways. This value could be obtained by querying cache
configuration registers. However, by defining a configuration
setting instead, we can avoid using RAM memory to hold information
about properties of the memory.
config ARMV7R_ASSOCIATIVITY_8WAY
bool "8-Way Associativity"
config ARMV7R_ASSOCIATIVITY_16WAY
bool "16-Way Associativity"
endchoice # L2 Cache Associativity
choice
prompt "L2 Cache Way Size"
default ARMV7R_WAYSIZE_16KB
depends on ARCH_L2CACHE
---help---
This choice specifies size of each way. This value can be obtained
by querying cache configuration registers. However, by defining a
configuration setting instead, we can avoid using RAM memory to hold
information
config ARMV7R_WAYSIZE_16KB
bool "16 KiB"
config ARMV7R_WAYSIZE_32KB
bool "32 KiB"
config ARMV7R_WAYSIZE_64KB
bool "64 KiB"
config ARMV7R_WAYSIZE_128KB
bool "128 KiB"
config ARMV7R_WAYSIZE_256KB
bool "256 KiB"
config ARMV7R_WAYSIZE_512KB
bool "512 KiB"
endchoice # L2 Cache Associativity
endif # ARCH_L2CACHE
endmenu # L2 Cache Configuration
endif # ARMV7R_HAVE_L2CC
choice
prompt "Toolchain Selection"
default ARMV7R_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS
default ARMV7R_TOOLCHAIN_GNU_EABIL if !HOST_WINDOWS
config ARMV7R_TOOLCHAIN_BUILDROOT
bool "Buildroot (Cygwin or Linux)"
depends on !WINDOWS_NATIVE
config ARMV7R_TOOLCHAIN_CODESOURCERYL
bool "CodeSourcery GNU toolchain under Linux"
depends on HOST_LINUX
---help---
For use with the GNU toolchain built with the NuttX buildroot package.
This tools may be arm-nuttx-eabi- or, if ARMV7R_OABI_TOOLCHAIN is set,
arm-nuttx-elf-.
config ARMV7R_TOOLCHAIN_CODESOURCERYW
bool "CodeSourcery GNU toolchain under Windows"
depends on HOST_WINDOWS
config ARMV7R_TOOLCHAIN_DEVKITARM
bool "devkitARM GNU toolchain"
depends on HOST_WINDOWS
config ARMV7R_TOOLCHAIN_GNU_EABIL
bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)"
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi-.
config ARMV7R_TOOLCHAIN_GNU_EABIW
bool "Generic GNU EABI toolchain under Windows"
depends on HOST_WINDOWS
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi-.
config ARMV7R_TOOLCHAIN_GNU_OABI
bool "Generic GNU OABI toolchain"
---help---
This option should work for any GNU toolchain configured for arm-elf-.
endchoice # ARMV7R_HAVE_L2CC
config ARMV7R_OABI_TOOLCHAIN
bool "OABI (vs EABI)"
default n
depends on ARMV7R_TOOLCHAIN_BUILDROOT
---help---
Most of the older buildroot toolchains are OABI and are named
arm-nuttx-elf- vs. arm-nuttx-eabi-
config ARMV7R_DECODEFIQ
bool "FIQ Handler"
default n
---help---
Select this option if your platform supports the function
arm_decodefiq().
arch/arm/src/armv7-r/Toolchain.defs
+156
View File
@@ -0,0 +1,156 @@
############################################################################
# arch/arm/src/armv7-r/Toolchain.defs
#
# Copyright (C) 2015 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in
# the documentation and/or other materials provided with the
# distribution.
# 3. Neither the name NuttX nor the names of its contributors may be
# used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
############################################################################
# Setup for the selected toolchain
#
# Select and allow the selected toolchain to be overridden by a command-line
#selection.
#
ifeq ($(filter y, \
$(CONFIG_ARMV7R_TOOLCHAIN_BUILDROOT) \
),y)
CONFIG_ARMV7R_TOOLCHAIN ?= BUILDROOT
endif
ifeq ($(filter y, \
$(CONFIG_ARMV7R_TOOLCHAIN_CODESOURCERYL) \
),y)
CONFIG_ARMV7R_TOOLCHAIN ?= CODESOURCERYL
endif
ifeq ($(filter y, \
$(CONFIG_ARMV7R_TOOLCHAIN_CODESOURCERYW) \
),y)
CONFIG_ARMV7R_TOOLCHAIN ?= CODESOURCERYW
endif
ifeq ($(filter y, \
$(CONFIG_ARMV7R_TOOLCHAIN_DEVKITARM) \
),y)
CONFIG_ARMV7R_TOOLCHAIN ?= DEVKITARM
endif
ifeq ($(filter y, \
$(CONFIG_ARMV7R_TOOLCHAIN_GNU_EABIL) \
),y)
CONFIG_ARMV7R_TOOLCHAIN ?= GNU_EABIL
endif
ifeq ($(filter y, \
$(CONFIG_ARMV7R_TOOLCHAIN_GNU_EABIW) \
),y)
CONFIG_ARMV7R_TOOLCHAIN ?= GNU_EABIW
endif
#
# Supported toolchains
#
# Each toolchain definition should set:
#
# CROSSDEV The GNU toolchain triple (command prefix)
# ARCROSSDEV If required, an alternative prefix used when
# invoking ar and nm.
# ARCHCPUFLAGS CPU-specific flags selecting the instruction set
# FPU options, etc.
# MAXOPTIMIZATION The maximum optimization level that results in
# reliable code generation.
#
ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y)
MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL)
endif
# NuttX buildroot under Linux or Cygwin
ifeq ($(CONFIG_ARMV7R_TOOLCHAIN),BUILDROOT)
ifeq ($(CONFIG_ARMV7R_OABI_TOOLCHAIN),y)
CROSSDEV ?= arm-nuttx-elf-
ARCROSSDEV ?= arm-nuttx-elf-
else
CROSSDEV ?= arm-nuttx-eabi-
ARCROSSDEV ?= arm-nuttx-eabi-
endif
MAXOPTIMIZATION ?= -Os
endif
# CodeSourcery under Linux
ifeq ($(CONFIG_ARMV7R_TOOLCHAIN),CODESOURCERYL)
CROSSDEV ?= arm-none-eabi-
ARCROSSDEV ?= arm-none-eabi-
MAXOPTIMIZATION ?= -O2
endif
# CodeSourcery under Windows
ifeq ($(CONFIG_ARMV7R_TOOLCHAIN),CODESOURCERYW)
CROSSDEV ?= arm-none-eabi-
ARCROSSDEV ?= arm-none-eabi-
MAXOPTIMIZATION ?= -O2
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
WINTOOL = y
endif
endif
# devkitARM under Windows
ifeq ($(CONFIG_ARMV7R_TOOLCHAIN),DEVKITARM)
CROSSDEV ?= arm-eabi-
ARCROSSDEV ?= arm-eabi-
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
WINTOOL = y
endif
endif
# Generic GNU EABI toolchain on OS X, Linux or any typical Posix system
ifeq ($(CONFIG_ARMV7R_TOOLCHAIN),GNU_EABIL)
CROSSDEV ?= arm-none-eabi-
ARCROSSDEV ?= arm-none-eabi-
MAXOPTIMIZATION ?= -Os
endif
# Generic GNU EABI toolchain under Windows
ifeq ($(CONFIG_ARMV7R_TOOLCHAIN),GNU_EABIW)
CROSSDEV ?= arm-none-eabi-
ARCROSSDEV ?= arm-none-eabi-
MAXOPTIMIZATION ?= -Os
ifneq ($(CONFIG_WINDOWS_NATIVE),y)
WINTOOL = y
endif
endif
arch/arm/src/armv7-r/arm.h
+139
View File
@@ -0,0 +1,139 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm.h
* Non-CP15 Registers
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* References:
*
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright
* 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.c (ID051414)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_ARMV7_R_CPSR_H
#define __ARCH_ARM_SRC_ARMV7_R_CPSR_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* ARMv7-R ******************************************************************/
/* PSR bits */
#define PSR_MODE_SHIFT (0) /* Bits 0-4: Mode fields */
#define PSR_MODE_MASK (31 << PSR_MODE_SHIFT)
# define PSR_MODE_USR (16 << PSR_MODE_SHIFT) /* User mode */
# define PSR_MODE_FIQ (17 << PSR_MODE_SHIFT) /* FIQ mode */
# define PSR_MODE_IRQ (18 << PSR_MODE_SHIFT) /* IRQ mode */
# define PSR_MODE_SVC (19 << PSR_MODE_SHIFT) /* Supervisor mode */
# define PSR_MODE_ABT (23 << PSR_MODE_SHIFT) /* Abort mode */
# define PSR_MODE_UND (27 << PSR_MODE_SHIFT) /* Undefined mode */
# define PSR_MODE_SYS (31 << PSR_MODE_SHIFT) /* System mode */
#define PSR_T_BIT (1 << 5) /* Bit 5: Thumb execution state bit */
#define PSR_MASK_SHIFT (6) /* Bits 6-8: Mask Bits */
#define PSR_MASK_MASK (7 << PSR_GE_SHIFT)
# define PSR_F_BIT (1 << 6) /* Bit 6: FIQ mask bit */
# define PSR_I_BIT (1 << 7) /* Bit 7: IRQ mask bit */
# define PSR_A_BIT (1 << 8) /* Bit 8: Asynchronous abort mask */
#define PSR_E_BIT (1 << 9) /* Bit 9: Endianness execution state bit */
#define PSR_IT27_SHIFT (10) /* Bits 10-15: If-Then execution state bits IT[2:7] */
#define PSR_IT27_MASK (0x3f << PSR_IT27_SHIFT)
#define PSR_GE_SHIFT (16) /* Bits 16-19: Greater than or Equal flags */
#define PSR_GE_MASK (15 << PSR_GE_SHIFT)
/* Bits 20-23: Reserved. RAZ/SBZP */
#define PSR_J_BIT (1 << 24) /* Bit 24: Jazelle state bit */
#define PSR_IT01_SHIFT (25) /* Bits 25-26: If-Then execution state bits IT[0:1] */
#define PSR_IT01_MASK (3 << PSR_IT01_SHIFT)
#define PSR_Q_BIT (1 << 27) /* Bit 27: Cumulative saturation bit */
#define PSR_V_BIT (1 << 28) /* Bit 28: Overflow condition flag */
#define PSR_C_BIT (1 << 29) /* Bit 29: Carry condition flag */
#define PSR_Z_BIT (1 << 30) /* Bit 30: Zero condition flag */
#define PSR_N_BIT (1 << 31) /* Bit 31: Negative condition flag */
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: arm_data_initialize
*
* Description:
* Clear all of .bss to zero; set .data to the correct initial values.
* This function is called automatically from ARMv7-R boot code *UNLESS*
* executing with data in some memory that requires platform-specific
* initialization (such as SDRAM). That latter case is indicated with
* CONFIG_ARMV7R_MEMINIT=y. In that case, early platform-specific logic
* must first initialize then memory then call this function.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void arm_data_initialize(void);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_ARMV7_R_CPSR_H */
arch/arm/src/armv7-r/arm_assert.c
+416
View File
@@ -0,0 +1,416 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_assert.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Output debug info if stack dump is selected -- even if debug is not
* selected.
*/
#ifdef CONFIG_ARCH_STACKDUMP
# undef CONFIG_DEBUG
# undef CONFIG_DEBUG_VERBOSE
# define CONFIG_DEBUG 1
# define CONFIG_DEBUG_VERBOSE 1
#endif
#include <stdint.h>
#include <stdlib.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/usb/usbdev_trace.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "sched/sched.h"
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* USB trace dumping */
#ifndef CONFIG_USBDEV_TRACE
# undef CONFIG_ARCH_USBDUMP
#endif
/* The following is just intended to keep some ugliness out of the mainline
* code. We are going to print the task name if:
*
* CONFIG_TASK_NAME_SIZE > 0 && <-- The task has a name
* (defined(CONFIG_DEBUG) || <-- And the debug is enabled (lldbg used)
* defined(CONFIG_ARCH_STACKDUMP) <-- Or lowsyslog() is used
*/
#undef CONFIG_PRINT_TASKNAME
#if CONFIG_TASK_NAME_SIZE > 0 && (defined(CONFIG_DEBUG) || defined(CONFIG_ARCH_STACKDUMP))
# define CONFIG_PRINT_TASKNAME 1
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_getsp
****************************************************************************/
/* I don't know if the builtin to get SP is enabled */
static inline uint32_t up_getsp(void)
{
uint32_t sp;
__asm__
(
"\tmov %0, sp\n\t"
: "=r"(sp)
);
return sp;
}
/****************************************************************************
* Name: up_stackdump
****************************************************************************/
#ifdef CONFIG_ARCH_STACKDUMP
static void up_stackdump(uint32_t sp, uint32_t stack_base)
{
uint32_t stack ;
for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
{
uint32_t *ptr = (uint32_t *)stack;
lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
}
#else
# define up_stackdump(sp,stack_base)
#endif
/****************************************************************************
* Name: up_taskdump
****************************************************************************/
#ifdef CONFIG_STACK_COLORATION
static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
{
/* Dump interesting properties of this task */
#ifdef CONFIG_PRINT_TASKNAME
lldbg("%s: PID=%d Stack Used=%lu of %lu\n",
tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#else
lldbg("PID: %d Stack Used=%lu of %lu\n",
tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#endif
}
#endif
/****************************************************************************
* Name: up_showtasks
****************************************************************************/
#ifdef CONFIG_STACK_COLORATION
static inline void up_showtasks(void)
{
/* Dump interesting properties of each task in the crash environment */
sched_foreach(up_taskdump, NULL);
}
#else
# define up_showtasks()
#endif
/****************************************************************************
* Name: up_registerdump
****************************************************************************/
#ifdef CONFIG_ARCH_STACKDUMP
static inline void up_registerdump(void)
{
/* Are user registers available from interrupt processing? */
if (current_regs)
{
int regs;
/* Yes.. dump the interrupt registers */
for (regs = REG_R0; regs <= REG_R15; regs += 8)
{
uint32_t *ptr = (uint32_t *)&current_regs[regs];
lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
lldbg("CPSR: %08x\n", current_regs[REG_CPSR]);
}
}
#else
# define up_registerdump()
#endif
/****************************************************************************
* Name: assert_tracecallback
****************************************************************************/
#ifdef CONFIG_ARCH_USBDUMP
static int usbtrace_syslog(FAR const char *fmt, ...)
{
va_list ap;
int ret;
/* Let vsyslog do the real work */
va_start(ap, fmt);
ret = lowvsyslog(LOG_INFO, fmt, ap);
va_end(ap);
return ret;
}
static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg)
{
usbtrace_trprintf(usbtrace_syslog, trace->event, trace->value);
return 0;
}
#endif
/****************************************************************************
* Name: up_dumpstate
****************************************************************************/
#ifdef CONFIG_ARCH_STACKDUMP
static void up_dumpstate(void)
{
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
uint32_t sp = up_getsp();
uint32_t ustackbase;
uint32_t ustacksize;
#if CONFIG_ARCH_INTERRUPTSTACK > 3
uint32_t istackbase;
uint32_t istacksize;
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
uint32_t kstackbase = 0;
#endif
/* Get the limits on the user stack memory */
if (rtcb->pid == 0)
{
ustackbase = g_idle_topstack - 4;
ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
}
else
{
ustackbase = (uint32_t)rtcb->adj_stack_ptr;
ustacksize = (uint32_t)rtcb->adj_stack_size;
}
lldbg("Current sp: %08x\n", sp);
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Get the limits on the interrupt stack memory */
istackbase = (uint32_t)&g_intstackbase;
istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
/* Show interrupt stack info */
lldbg("Interrupt stack:\n");
lldbg(" base: %08x\n", istackbase);
lldbg(" size: %08x\n", istacksize);
#ifdef CONFIG_STACK_COLORATION
lldbg(" used: %08x\n", up_check_intstack());
#endif
#endif
/* Show user stack info */
lldbg("User stack:\n");
lldbg(" base: %08x\n", ustackbase);
lldbg(" size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
lldbg(" used: %08x\n", up_check_tcbstack(rtcb));
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
/* This this thread have a kernel stack allocated? */
if (rtcb->xcp.kstack)
{
kstackbase = (uint32_t)rtcb->xcp.kstack + CONFIG_ARCH_KERNEL_STACKSIZE - 4;
lldbg("Kernel stack:\n");
lldbg(" base: %08x\n", kstackbase);
lldbg(" size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE);
}
#endif
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Does the current stack pointer lie within the interrupt stack? */
if (sp > istackbase - istacksize && sp < istackbase)
{
/* Yes.. dump the interrupt stack */
lldbg("Interrupt Stack\n", sp);
up_stackdump(sp, istackbase);
/* Extract the user stack pointer which should lie
* at the base of the interrupt stack.
*/
sp = g_intstackbase;
lldbg("User sp: %08x\n", sp);
}
#endif
/* Dump the user stack if the stack pointer lies within the allocated user
* stack memory.
*/
if (sp > ustackbase - ustacksize && sp < ustackbase)
{
lldbg("User Stack\n", sp);
up_stackdump(sp, ustackbase);
}
#ifdef CONFIG_ARCH_KERNEL_STACK
/* Dump the user stack if the stack pointer lies within the allocated
* kernel stack memory.
*/
if (sp >= (uint32_t)rtcb->xcp.kstack && sp < kstackbase)
{
lldbg("Kernel Stack\n", sp);
up_stackdump(sp, kstackbase);
}
#endif
/* Then dump the registers (if available) */
up_registerdump();
/* Dump the state of all tasks (if available) */
up_showtasks();
#ifdef CONFIG_ARCH_USBDUMP
/* Dump USB trace data */
(void)usbtrace_enumerate(assert_tracecallback, NULL);
#endif
}
#else
# define up_dumpstate()
#endif
/****************************************************************************
* Name: _up_assert
****************************************************************************/
static void _up_assert(int errorcode) noreturn_function;
static void _up_assert(int errorcode)
{
/* Are we in an interrupt handler or the idle task? */
if (current_regs || ((struct tcb_s *)g_readytorun.head)->pid == 0)
{
(void)irqsave();
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
}
else
{
exit(errorcode);
}
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_assert
****************************************************************************/
void up_assert(const uint8_t *filename, int lineno)
{
#ifdef CONFIG_PRINT_TASKNAME
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
lldbg("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
up_dumpstate();
#ifdef CONFIG_BOARD_CRASHDUMP
board_crashdump(up_getsp(), g_readytorun.head, filename, lineno);
#endif
_up_assert(EXIT_FAILURE);
}
arch/arm/src/armv7-r/arm_blocktask.c
+164
View File
@@ -0,0 +1,164 @@
/****************************************************************************
* arch/arm/src/armv7-r/up_blocktask.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <sched.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/sched.h>
#include "sched/sched.h"
#include "group/group.h"
#include "up_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_block_task
*
* Description:
* The currently executing task at the head of
* the ready to run list must be stopped. Save its context
* and move it to the inactive list specified by task_state.
*
* Inputs:
* tcb: Refers to a task in the ready-to-run list (normally
* the task at the head of the list). It most be
* stopped, its context saved and moved into one of the
* waiting task lists. It it was the task at the head
* of the ready-to-run list, then a context to the new
* ready to run task must be performed.
* task_state: Specifies which waiting task list should be
* hold the blocked task TCB.
*
****************************************************************************/
void up_block_task(struct tcb_s *tcb, tstate_t task_state)
{
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
bool switch_needed;
/* Verify that the context switch can be performed */
ASSERT((tcb->task_state >= FIRST_READY_TO_RUN_STATE) &&
(tcb->task_state <= LAST_READY_TO_RUN_STATE));
/* Remove the tcb task from the ready-to-run list. If we
* are blocking the task at the head of the task list (the
* most likely case), then a context switch to the next
* ready-to-run task is needed. In this case, it should
* also be true that rtcb == tcb.
*/
switch_needed = sched_removereadytorun(tcb);
/* Add the task to the specified blocked task list */
sched_addblocked(tcb, (tstate_t)task_state);
/* If there are any pending tasks, then add them to the g_readytorun
* task list now
*/
if (g_pendingtasks.head)
{
switch_needed |= sched_mergepending();
}
/* Now, perform the context switch if one is needed */
if (switch_needed)
{
/* Update scheduler parameters */
sched_suspend_scheduler(rtcb);
/* Are we in an interrupt handler? */
if (current_regs)
{
/* Yes, then we have to do things differently.
* Just copy the current_regs into the OLD rtcb.
*/
up_savestate(rtcb->xcp.regs);
/* Restore the exception context of the rtcb at the (new) head
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s *)g_readytorun.head;
/* Reset scheduler parameters */
sched_resume_scheduler(rtcb);
/* Then switch contexts. */
up_restorestate(rtcb->xcp.regs);
}
/* Copy the user C context into the TCB at the (old) head of the
* g_readytorun Task list. if up_saveusercontext returns a non-zero
* value, then this is really the previously running task restarting!
*/
else if (!up_saveusercontext(rtcb->xcp.regs))
{
/* Restore the exception context of the rtcb at the (new) head
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s *)g_readytorun.head;
/* Reset scheduler parameters */
sched_resume_scheduler(rtcb);
/* Then switch contexts */
up_fullcontextrestore(rtcb->xcp.regs);
}
}
}
arch/arm/src/armv7-r/arm_coherent_dcache.c
+97
View File
@@ -0,0 +1,97 @@
/****************************************************************************
* arch/arm/src/armv7-r/up_coherent_dcache.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include "cp15_cacheops.h"
#include <nuttx/arch.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_coherent_dcache
*
* Description:
* Ensure that the I and D caches are coherent within specified region
* by cleaning the D cache (i.e., flushing the D cache contents to memory
* and invalidating the I cache. This is typically used when code has been
* written to a memory region, and will be executed.
*
* Input Parameters:
* addr - virtual start address of region
* len - Size of the address region in bytes
*
* Returned Value:
* None
*
****************************************************************************/
void up_coherent_dcache(uintptr_t addr, size_t len)
{
if (len > 0)
{
/* Perform the operation on the L1 cache */
cp15_coherent_dcache(addr, addr + len - 1);
#ifdef CONFIG_ARCH_L2CACHE
/* If we have an L2 cache, then there more things that need to done */
# warning This is insufficient
#endif
}
}
arch/arm/src/armv7-r/arm_copyarmstate.c
+87
View File
@@ -0,0 +1,87 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_copyarmstate.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include "up_internal.h"
#ifdef CONFIG_ARCH_FPU
/****************************************************************************
* Name: up_copyarmstate
*
* Description:
* Copy the ARM portion of the register save area (omitting the floating
* point registers) and save the floating pointer register directly.
*
****************************************************************************/
void up_copyarmstate(uint32_t *dest, uint32_t *src)
{
int i;
/* In the Cortex-R model, the state is copied from the stack to the TCB,
* but only a reference is passed to get the state from the TCB. So the
* following check avoids copying the TCB save area onto itself:
*/
if (src != dest)
{
/* Save the floating point registers: This will initialize the floating
* registers at indices ARM_CONTEXT_REGS through (XCPTCONTEXT_REGS-1)
*/
up_savefpu(dest);
/* Then copy all of the ARM registers (omitting the floating point
* registers). Indices: 0 through (ARM_CONTEXT_REGS-1).
*/
for (i = 0; i < ARM_CONTEXT_REGS; i++)
{
*dest++ = *src++;
}
}
}
#endif /* CONFIG_ARCH_FPU */
arch/arm/src/armv7-r/arm_copyfullstate.c
+85
View File
@@ -0,0 +1,85 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_copyfullstate.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_copyfullstate
*
* Description:
* Copy the entire register save area (including the floating point
* registers if applicable). This is a little faster than most memcpy's
* since it does 32-bit transfers.
*
****************************************************************************/
void up_copyfullstate(uint32_t *dest, uint32_t *src)
{
int i;
/* In the current ARM model, the state is always copied to and from the
* stack and TCB.
*/
for (i = 0; i < XCPTCONTEXT_REGS; i++)
{
*dest++ = *src++;
}
}
arch/arm/src/armv7-r/arm_dataabort.c
+199
View File
@@ -0,0 +1,199 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_dataabort.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Output debug info if stack dump is selected -- even if debug is not
* selected.
*/
#ifdef CONFIG_ARCH_STACKDUMP
# undef CONFIG_DEBUG
# undef CONFIG_DEBUG_VERBOSE
# define CONFIG_DEBUG 1
# define CONFIG_DEBUG_VERBOSE 1
#endif
#include <stdint.h>
#include <debug.h>
#include <nuttx/irq.h>
#include "sched/sched.h"
#include "up_internal.h"
#ifdef CONFIG_PAGING
# include <nuttx/page.h>
# include "arm.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_dataabort
*
* Input parameters:
* regs - The standard, ARM register save array.
*
* If CONFIG_PAGING is selected in the NuttX configuration file, then these
* additional input values are expected:
*
* dfar - Fault address register.
* dfsr - Fault status register.
*
* Description:
* This is the data abort exception handler. The ARM data abort exception
* occurs when a memory fault is detected during a data transfer.
*
****************************************************************************/
#ifdef CONFIG_PAGING
uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
{
DFAR struct tcb_s *tcb = (DFAR struct tcb_s *)g_readytorun.head;
uint32_t *savestate;
/* Save the saved processor context in current_regs where it can be accessed
* for register dumps and possibly context switching.
*/
savestate = (uint32_t *)current_regs;
current_regs = regs;
/* In the NuttX on-demand paging implementation, only the read-only, .text
* section is paged. However, the ARM compiler generated PC-relative data
* fetches from within the .text sections. Also, it is customary to locate
* read-only data (.rodata) within the same section as .text so that it
* does not require copying to RAM. Misses in either of these case should
* cause a data abort.
*
* We are only interested in data aborts due to page translations faults.
* Sections should already be in place and permissions should already be
* be set correctly (to read-only) so any other data abort reason is a
* fatal error.
*/
pglldbg("DFSR: %08x DFAR: %08x\n", dfsr, dfar);
if ((dfsr & FSR_MASK) != FSR_PAGE)
{
goto segfault;
}
/* Check the (virtual) address of data that caused the data abort. When
* the exception occurred, this address was provided in the DFAR register.
* (It has not yet been saved in the register context save area).
*/
pgllvdbg("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
if (dfar < PG_PAGED_VBASE || dfar >= PG_PAGED_VEND)
{
goto segfault;
}
/* Save the offending data address as the fault address in the TCB of
* the currently task. This fault address is also used by the prefetch
* abort handling; this will allow common paging logic for both
* prefetch and data aborts.
*/
tcb->xcp.dfar = regs[REG_R15];
/* Call pg_miss() to schedule the page fill. A consequences of this
* call are:
*
* (1) The currently executing task will be blocked and saved on
* on the g_waitingforfill task list.
* (2) An interrupt-level context switch will occur so that when
* this function returns, it will return to a different task,
* most likely the page fill worker thread.
* (3) The page fill worker task has been signalled and should
* execute immediately when we return from this exception.
*/
pg_miss();
/* Restore the previous value of current_regs. NULL would indicate that
* we are no longer in an interrupt handler. It will be non-NULL if we
* are returning from a nested interrupt.
*/
current_regs = savestate;
return regs;
segfault:
lldbg("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
regs[REG_PC], dfar, dfsr);
PANIC();
return regs; /* To keep the compiler happy */
}
#else /* CONFIG_PAGING */
uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
{
/* Save the saved processor context in current_regs where it can be accessed
* for register dumps and possibly context switching.
*/
current_regs = regs;
/* Crash -- possibly showing diagnostic debug information. */
lldbg("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
regs[REG_PC], dfar, dfsr);
PANIC();
return regs; /* To keep the compiler happy */
}
#endif /* CONFIG_PAGING */
arch/arm/src/armv7-r/arm_doirq.c
+122
View File
@@ -0,0 +1,122 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_doirq.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <assert.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include "up_arch.h"
#include "up_internal.h"
#include "group/group.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
uint32_t *arm_doirq(int irq, uint32_t *regs)
{
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
/* Nested interrupts are not supported */
DEBUGASSERT(current_regs == NULL);
/* Current regs non-zero indicates that we are processing an interrupt;
* current_regs is also used to manage interrupt level context switches.
*/
current_regs = regs;
/* Deliver the IRQ */
irq_dispatch(irq, regs);
#ifdef CONFIG_ARCH_FPU
/* Check for a context switch. If a context switch occurred, then
* current_regs will have a different value than it did on entry. If an
* interrupt level context switch has occurred, then restore the floating
* point state and the establish the correct address environment before
* returning from the interrupt.
*/
if (regs != current_regs)
{
/* Restore floating point registers */
up_restorefpu((uint32_t *)current_regs);
}
#endif
/* Set current_regs to NULL to indicate that we are no longer in an
* interrupt handler.
*/
regs = (uint32_t *)current_regs;
current_regs = NULL;
board_autoled_off(LED_INIRQ);
#endif
return regs;
}
arch/arm/src/armv7-r/arm_elf.c
+273
View File
@@ -0,0 +1,273 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_elf.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdlib.h>
#include <elf32.h>
#include <errno.h>
#include <debug.h>
#include <arch/elf.h>
#include <nuttx/arch.h>
#include <nuttx/binfmt/elf.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_checkarch
*
* Description:
* Given the ELF header in 'hdr', verify that the ELF file is appropriate
* for the current, configured architecture. Every architecture that uses
* the ELF loader must provide this function.
*
* Input Parameters:
* hdr - The ELF header read from the ELF file.
*
* Returned Value:
* True if the architecture supports this ELF file.
*
****************************************************************************/
bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
{
/* Make sure it's an ARM executable */
if (ehdr->e_machine != EM_ARM)
{
bdbg("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
return -ENOEXEC;
}
/* Make sure that 32-bit objects are supported */
if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
{
bdbg("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
return -ENOEXEC;
}
/* Verify endian-ness */
#ifdef CONFIG_ENDIAN_BIG
if (ehdr->e_ident[EI_DATA] != ELFDATA2MSB)
#else
if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
#endif
{
bdbg("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
return -ENOEXEC;
}
/* Make sure the entry point address is properly aligned */
if ((ehdr->e_entry & 3) != 0)
{
bdbg("Entry point is not properly aligned: %08x\n", ehdr->e_entry);
return -ENOEXEC;
}
/* TODO: Check ABI here. */
return OK;
}
/****************************************************************************
* Name: up_relocate and up_relocateadd
*
* Description:
* Perform on architecture-specific ELF relocation. Every architecture
* that uses the ELF loader must provide this function.
*
* Input Parameters:
* rel - The relocation type
* sym - The ELF symbol structure containing the fully resolved value.
* There are a few relocation types for a few architectures that do
* not require symbol information. For those, this value will be
* NULL. Implementations of these functions must be able to handle
* that case.
* addr - The address that requires the relocation.
*
* Returned Value:
* Zero (OK) if the relocation was successful. Otherwise, a negated errno
* value indicating the cause of the relocation failure.
*
****************************************************************************/
int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
uintptr_t addr)
{
int32_t offset;
unsigned int relotype;
/* All relocations except R_ARM_V4BX depend upon having valid symbol
* information.
*/
relotype = ELF32_R_TYPE(rel->r_info);
if (sym == NULL && relotype != R_ARM_NONE && relotype != R_ARM_V4BX)
{
return -EINVAL;
}
/* Handle the relocation by relocation type */
switch (relotype)
{
case R_ARM_NONE:
{
/* No relocation */
}
break;
case R_ARM_PC24:
case R_ARM_CALL:
case R_ARM_JUMP24:
{
bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
offset = (*(uint32_t *)addr & 0x00ffffff) << 2;
if (offset & 0x02000000)
{
offset -= 0x04000000;
}
offset += sym->st_value - addr;
if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000)
{
bdbg(" ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
ELF32_R_TYPE(rel->r_info), offset);
return -EINVAL;
}
offset >>= 2;
*(uint32_t *)addr &= 0xff000000;
*(uint32_t *)addr |= offset & 0x00ffffff;
}
break;
case R_ARM_ABS32:
case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
{
bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t *)addr += sym->st_value;
}
break;
case R_ARM_V4BX:
{
bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
(long)addr, (long)(*(uint32_t *)addr));
/* Preserve only Rm and the condition code */
*(uint32_t *)addr &= 0xf000000f;
/* Change instruction to 'mov pc, Rm' */
*(uint32_t *)addr |= 0x01a0f000;
}
break;
case R_ARM_PREL31:
{
bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
offset = *(uint32_t *)addr + sym->st_value - addr;
*(uint32_t *)addr = offset & 0x7fffffff;
}
break;
case R_ARM_MOVW_ABS_NC:
case R_ARM_MOVT_ABS:
{
bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
offset = *(uint32_t *)addr;
offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff);
offset = (offset ^ 0x8000) - 0x8000;
offset += sym->st_value;
if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS)
{
offset >>= 16;
}
*(uint32_t *)addr &= 0xfff0f000;
*(uint32_t *)addr |= ((offset & 0xf000) << 4) | (offset & 0x0fff);
}
break;
default:
bdbg("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
return -EINVAL;
}
return OK;
}
int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
uintptr_t addr)
{
bdbg("RELA relocation not supported\n");
return -ENOSYS;
}
arch/arm/src/armv7-r/arm_fpuconfig.S
+92
View File
@@ -0,0 +1,92 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_fpuconfig.S
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cp15.h"
/****************************************************************************
* Public Symbols
****************************************************************************/
.globl arm_fpuconfig
#ifdef CONFIG_ARCH_FPU
.cpu cortex-r4
#else
.cpu cortex-r4f
#endif
.syntax unified
.file "arm_fpuconfig.S"
/****************************************************************************
* Public Functions
****************************************************************************/
.text
/****************************************************************************
* Name: sam_fpuconfig
*
* Description:
* Configure the FPU. Enables access to CP10 and CP11
*
****************************************************************************/
.globl arm_fpuconfig
.type arm_fpuconfig, %function
arm_fpuconfig:
/* Enable access to CP10 and CP11 in CP15.CACR */
mrc CP15_CPACR(r0)
orr r0, r0, #0xf00000
mcr CP15_CPACR(r0)
/* Enable access to CP10 and CP11 in CP15.NSACR */
/* REVISIT: Do we need to do this? */
/* Set FPEXC.EN (B30) */
fmrx r0, fpexc
orr r0, r0, #0x40000000
fmxr fpexc, r0
bx lr
.size arm_fpuconfig, . - arm_fpuconfig
.end
arch/arm/src/armv7-r/arm_fullcontextrestore.S
+176
View File
@@ -0,0 +1,176 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_fullcontextrestore.S
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include "up_internal.h"
#include "svcall.h"
.file "arm_fullcontextrestore.S"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Symbols
****************************************************************************/
.globl up_fullcontextrestore
#ifdef CONFIG_ARCH_FPU
.cpu cortex-r4
#else
.cpu cortex-r4f
#endif
.syntax unified
.file "arm_fullcontextrestore.S"
/****************************************************************************
* Public Functions
****************************************************************************/
.text
/****************************************************************************
* Name: up_fullcontextrestore
*
* Description:
* Restore the specified task context. Full prototype is:
*
* void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
*
* Return:
* None
*
****************************************************************************/
.globl up_fullcontextrestore
.type up_fullcontextrestore, function
up_fullcontextrestore:
/* On entry, a1 (r0) holds address of the register save area. All other
* registers are available for use.
*/
#ifdef CONFIG_ARCH_FPU
/* First, restore the floating point registers. Lets do this before we
* restore the ARM registers so that we have plenty of registers to
* work with.
*/
add r1, r0, #(4*REG_S0) /* r1=Address of FP register storage */
/* Load all floating point registers. Registers are loaded in numeric order,
* s0, s1, ... in increasing address order.
*/
vldmia r1!, {s0-s31} /* Restore the full FP context */
/* Load the floating point control and status register. At the end of the
* vstmia, r1 will point to the FPCSR storage location.
*/
ldr r2, [r1], #4 /* Fetch the floating point control and status register */
vmsr fpscr, r2 /* Restore the FPCSR */
#endif
#ifdef CONFIG_BUILD_KERNEL
/* For the kernel build, we need to be able to transition gracefully
* between kernel- and user-mode tasks. Here we do that with a system
* call; the system call will execute in kernel mode and but can return
* to either user or kernel mode.
*/
/* Perform the System call with R0=SYS_context_restore, R1=restoreregs */
mov r1, r0 /* R1: restoreregs */
mov r0, #SYS_context_restore /* R0: SYS_context_restore syscall */
svc #0x900001 /* Perform the system call */
/* This call should not return */
bx lr /* Unnecessary ... will not return */
#else
/* For a flat build, we can do all of this here... Just think of this as
* a longjmp() all on steriods.
*/
/* Recover all registers except for r0, r1, R15, and CPSR */
add r1, r0, #(4*REG_R2) /* Offset to REG_R2 storage */
ldmia r1, {r2-r14} /* Recover registers */
/* Create a stack frame to hold the some registers */
sub sp, sp, #(3*4) /* Frame for three registers */
ldr r1, [r0, #(4*REG_R0)] /* Fetch the stored r0 value */
str r1, [sp] /* Save it at the top of the stack */
ldr r1, [r0, #(4*REG_R1)] /* Fetch the stored r1 value */
str r1, [sp, #4] /* Save it in the stack */
ldr r1, [r0, #(4*REG_PC)] /* Fetch the stored pc value */
str r1, [sp, #8] /* Save it at the bottom of the frame */
/* Now we can restore the CPSR. We wait until we are completely
* finished with the context save data to do this. Restore the CPSR
* may re-enable and interrupts and we could be in a context
* where the save structure is only protected by interrupts being
* disabled.
*/
ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the stored CPSR value */
msr cpsr, r1 /* Set the CPSR */
/* Now recover r0 and r1 */
ldr r0, [sp]
ldr r1, [sp, #4]
add sp, sp, #(2*4)
/* Then return to the address at the stop of the stack,
* destroying the stack frame
*/
ldr pc, [sp], #4
#endif
.size up_fullcontextrestore, . - up_fullcontextrestore
arch/arm/src/armv7-r/arm_head.S
+536
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/armv7-r/arm_initialstate.c
+140
View File
@@ -0,0 +1,140 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_initialstate.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <string.h>
#include <nuttx/arch.h>
#include "arm.h"
#include "up_internal.h"
#include "up_arch.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_initial_state
*
* Description:
* A new thread is being started and a new TCB has been created. This
* function is called to initialize the processor specific portions of
* the new TCB.
*
* This function must setup the initial architecture registers and/or
* stack so that execution will begin at tcb->start on the next context
* switch.
*
****************************************************************************/
void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
uint32_t cpsr;
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
/* Save the initial stack pointer */
xcp->regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr;
/* Save the task entry point */
xcp->regs[REG_PC] = (uint32_t)tcb->start;
/* If this task is running PIC, then set the PIC base register to the
* address of the allocated D-Space region.
*/
#ifdef CONFIG_PIC
if (tcb->dspace != NULL)
{
/* Set the PIC base register (probably R10) to the address of the
* alloacated D-Space region.
*/
xcp->regs[REG_PIC] = (uint32_t)tcb->dspace->region;
}
#endif
/* Set supervisor-mode and disable FIQs, regardless of how NuttX is
* configured and of what kind of thread is being started. That is
* because all threads, even user-mode threads will start in kernel
* trampoline at task_start() or pthread_start(). The thread's
* privileges will be dropped before transitioning to user code.
*/
cpsr = PSR_MODE_SVC;
/* Enable or disable interrupts, based on user configuration */
#ifdef CONFIG_SUPPRESS_INTERRUPTS
/* Disable interrupts (both IRQs and FIQs) */
cpsr |= (PSR_I_BIT | PSR_F_BIT);
#else /* CONFIG_SUPPRESS_INTERRUPTS */
/* Leave IRQs enabled (Also FIQs if CONFIG_ARMV7R_DECODEFIQ is selected) */
#ifndef CONFIG_ARMV7R_DECODEFIQ
cpsr |= PSR_F_BIT;
#endif /* !CONFIG_ARMV7R_DECODEFIQ */
#endif /* CONFIG_SUPPRESS_INTERRUPTS */
xcp->regs[REG_CPSR] = cpsr;
}
arch/arm/src/armv7-r/arm_l2cc_pl310.c
+874
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/armv7-r/arm_memcpy.S
+433
View File
@@ -0,0 +1,433 @@
/************************************************************************************
* nuttx/arch/arm/src/armv7-r/arm_memcpy.S
*
* ARMv7-R optimised memcpy, based on the ARMv7-M version contributed by Mike Smith.
* Apparently in the public domain and is re-released here under the modified BSD
* license:
*
* Obtained via a posting on the Stellaris forum:
* http://e2e.ti.com/support/microcontrollers/\
* stellaris_arm_cortex-m3_microcontroller/f/473/t/44360.aspx
*
* Posted by rocksoft on Jul 24, 2008 10:19 AM
*
* Hi,
*
* I recently finished a "memcpy" replacement and thought it might be useful for
* others...
*
* I've put some instructions and the code here:
*
* http://www.rock-software.net/downloads/memcpy/
*
* Hope it works for you as well as it did for me.
*
* Liam.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Public Symbols
************************************************************************************/
.global memcpy
#ifdef CONFIG_ARCH_FPU
.cpu cortex-r4
#else
.cpu cortex-r4f
#endif
.syntax unified
.file "arm_memcpy.S"
/************************************************************************************
* .text
************************************************************************************/
.text
/************************************************************************************
* Private Constant Data
************************************************************************************/
/* We have 16 possible alignment combinations of src and dst, this jump table
* directs the copy operation
*
* Bits: Src=00, Dst=00 - Long to Long copy
* Bits: Src=00, Dst=01 - Long to Byte before half word
* Bits: Src=00, Dst=10 - Long to Half word
* Bits: Src=00, Dst=11 - Long to Byte before long word
* Bits: Src=01, Dst=00 - Byte before half word to long
* Bits: Src=01, Dst=01 - Byte before half word to byte before half word -
* Same alignment
* Bits: Src=01, Dst=10 - Byte before half word to half word
* Bits: Src=01, Dst=11 - Byte before half word to byte before long word
* Bits: Src=10, Dst=00 - Half word to long word
* Bits: Src=10, Dst=01 - Half word to byte before half word
* Bits: Src=10, Dst=10 - Half word to half word - Same Alignment
* Bits: Src=10, Dst=11 - Half word to byte before long word
* Bits: Src=11, Dst=00 - Byte before long word to long word
* Bits: Src=11, Dst=01 - Byte before long word to byte before half word
* Bits: Src=11, Dst=11 - Byte before long word to half word
* Bits: Src=11, Dst=11 - Byte before long word to Byte before long word -
* Same alignment
*/
MEM_DataCopyTable:
.byte (MEM_DataCopy0 - MEM_DataCopyJump) >> 1
.byte (MEM_DataCopy1 - MEM_DataCopyJump) >> 1
.byte (MEM_DataCopy2 - MEM_DataCopyJump) >> 1
.byte (MEM_DataCopy3 - MEM_DataCopyJump) >> 1
.byte (MEM_DataCopy4 - MEM_DataCopyJump) >> 1
.byte (MEM_DataCopy5 - MEM_DataCopyJump) >> 1
.byte (MEM_DataCopy6 - MEM_DataCopyJump) >> 1
.byte (MEM_DataCopy7 - MEM_DataCopyJump) >> 1
.byte (MEM_DataCopy8 - MEM_DataCopyJump) >> 1
.byte (MEM_DataCopy9 - MEM_DataCopyJump) >> 1
.byte (MEM_DataCopy10 - MEM_DataCopyJump) >> 1
.byte (MEM_DataCopy11 - MEM_DataCopyJump) >> 1
.byte (MEM_DataCopy12 - MEM_DataCopyJump) >> 1
.byte (MEM_DataCopy13 - MEM_DataCopyJump) >> 1
.byte (MEM_DataCopy14 - MEM_DataCopyJump) >> 1
.byte (MEM_DataCopy15 - MEM_DataCopyJump) >> 1
.align 2
MEM_LongCopyTable:
.byte (MEM_LongCopyEnd - MEM_LongCopyJump) >> 1 /* 0 bytes left */
.byte 0 /* 4 bytes left */
.byte (1 * 10) >> 1 /* 8 bytes left */
.byte (2 * 10) >> 1 /* 12 bytes left */
.byte (3 * 10) >> 1 /* 16 bytes left */
.byte (4 * 10) >> 1 /* 20 bytes left */
.byte (5 * 10) >> 1 /* 24 bytes left */
.byte (6 * 10) >> 1 /* 28 bytes left */
.byte (7 * 10) >> 1 /* 32 bytes left */
.byte (8 * 10) >> 1 /* 36 bytes left */
.align 2
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: memcpy
*
* Description:
* Optimised "general" copy routine
*
* Input Parameters:
* r0 = destination, r1 = source, r2 = length
*
* Returned Value:
* r0 = destination r1-r3 burned
*
************************************************************************************/
.align 4
memcpy:
push {r14}
push {r0}
bl _do_memcpy
pop {r0}
pop {pc}
.align 4
_do_memcpy:
push {r14}
/* This allows the inner workings to "assume" a minimum amount of bytes */
/* Quickly check for very short copies */
cmp r2, #4
blt.n MEM_DataCopyBytes
and r14, r0, #3 /* Get destination alignment bits */
bfi r14, r1, #2, #2 /* Get source alignment bits */
ldr r3, =MEM_DataCopyTable /* Jump table base */
tbb [r3, r14] /* Perform jump on src/dst alignment bits */
MEM_DataCopyJump:
.align 4
/* Bits: Src=01, Dst=01 - Byte before half word to byte before half word - Same alignment
* 3 bytes to read for long word aligning
*/
MEM_DataCopy5:
ldrb r3, [r1], #0x01
strb r3, [r0], #0x01
sub r2, r2, #0x01
/* Bits: Src=10, Dst=10 - Half word to half word - Same Alignment
* 2 bytes to read for long word aligning
*/
MEM_DataCopy10:
ldrb r3, [r1], #0x01
strb r3, [r0], #0x01
sub r2, r2, #0x01
/* Bits: Src=11, Dst=11 - Byte before long word to Byte before long word - Same alignment
* 1 bytes to read for long word aligning
*/
MEM_DataCopy15:
ldrb r3, [r1], #0x01
strb r3, [r0], #0x01
sub r2, r2, #0x01
/* Bits: Src=00, Dst=00 - Long to Long copy */
MEM_DataCopy0:
/* Save regs that may be used by memcpy */
push {r4-r12}
/* Check for short word-aligned copy */
cmp r2, #0x28
blt.n MEM_DataCopy0_2
/* Bulk copy loop */
MEM_DataCopy0_1:
ldmia r1!, {r3-r12}
stmia r0!, {r3-r12}
sub r2, r2, #0x28
cmp r2, #0x28
bge.n MEM_DataCopy0_1
/* Copy remaining long words */
MEM_DataCopy0_2:
/* Copy remaining long words */
ldr r14, =MEM_LongCopyTable
lsr r11, r2, #0x02
tbb [r14, r11]
/* longword copy branch table anchor */
MEM_LongCopyJump:
ldr.w r3, [r1], #0x04 /* 4 bytes remain */
str.w r3, [r0], #0x04
b.n MEM_LongCopyEnd
ldmia.w r1!, {r3-r4} /* 8 bytes remain */
stmia.w r0!, {r3-r4}
b.n MEM_LongCopyEnd
ldmia.w r1!, {r3-r5} /* 12 bytes remain */
stmia.w r0!, {r3-r5}
b.n MEM_LongCopyEnd
ldmia.w r1!, {r3-r6} /* 16 bytes remain */
stmia.w r0!, {r3-r6}
b.n MEM_LongCopyEnd
ldmia.w r1!, {r3-r7} /* 20 bytes remain */
stmia.w r0!, {r3-r7}
b.n MEM_LongCopyEnd
ldmia.w r1!, {r3-r8} /* 24 bytes remain */
stmia.w r0!, {r3-r8}
b.n MEM_LongCopyEnd
ldmia.w r1!, {r3-r9} /* 28 bytes remain */
stmia.w r0!, {r3-r9}
b.n MEM_LongCopyEnd
ldmia.w r1!, {r3-r10} /* 32 bytes remain */
stmia.w r0!, {r3-r10}
b.n MEM_LongCopyEnd
ldmia.w r1!, {r3-r11} /* 36 bytes remain */
stmia.w r0!, {r3-r11}
MEM_LongCopyEnd:
pop {r4-r12}
and r2, r2, #0x03 /* All the longs have been copied */
/* Deal with up to 3 remaining bytes */
MEM_DataCopyBytes:
/* Deal with up to 3 remaining bytes */
cmp r2, #0x00
it eq
popeq {pc}
ldrb r3, [r1], #0x01
strb r3, [r0], #0x01
subs r2, r2, #0x01
it eq
popeq {pc}
ldrb r3, [r1], #0x01
strb r3, [r0], #0x01
subs r2, r2, #0x01
it eq
popeq {pc}
ldrb r3, [r1], #0x01
strb r3, [r0], #0x01
pop {pc}
.align 4
/* Bits: Src=01, Dst=11 - Byte before half word to byte before long word
* 3 bytes to read for long word aligning the source
*/
MEM_DataCopy7:
ldrb r3, [r1], #0x01
strb r3, [r0], #0x01
sub r2, r2, #0x01
/* Bits: Src=10, Dst=00 - Half word to long word
* 2 bytes to read for long word aligning the source
*/
MEM_DataCopy8:
ldrb r3, [r1], #0x01
strb r3, [r0], #0x01
sub r2, r2, #0x01
/* Bits: Src=11, Dst=01 - Byte before long word to byte before half word
* 1 byte to read for long word aligning the source
*/
MEM_DataCopy13:
ldrb r3, [r1], #0x01
strb r3, [r0], #0x01
sub r2, r2, #0x01
/* Bits: Src=00, Dst=10 - Long to Half word */
MEM_DataCopy2:
cmp r2, #0x28
blt.n MEM_DataCopy2_1
/* Save regs */
push {r4-r12}
/* Bulk copy loop */
MEM_DataCopy2_2:
ldmia r1!, {r3-r12}
strh r3, [r0], #0x02
lsr r3, r3, #0x10
bfi r3, r4, #0x10, #0x10
lsr r4, r4, #0x10
bfi r4, r5, #0x10, #0x10
lsr r5, r5, #0x10
bfi r5, r6, #0x10, #0x10
lsr r6, r6, #0x10
bfi r6, r7, #0x10, #0x10
lsr r7, r7, #0x10
bfi r7, r8, #0x10, #0x10
lsr r8, r8, #0x10
bfi r8, r9, #0x10, #0x10
lsr r9, r9, #0x10
bfi r9, r10, #0x10, #0x10
lsr r10, r10, #0x10
bfi r10, r11, #0x10, #0x10
lsr r11, r11, #0x10
bfi r11, r12, #0x10, #0x10
stmia r0!, {r3-r11}
lsr r12, r12, #0x10
strh r12, [r0], #0x02
sub r2, r2, #0x28
cmp r2, #0x28
bge.n MEM_DataCopy2_2
pop {r4-r12}
MEM_DataCopy2_1: /* Read longs and write 2 x half words */
cmp r2, #4
blt.n MEM_DataCopyBytes
ldr r3, [r1], #0x04
strh r3, [r0], #0x02
lsr r3, r3, #0x10
strh r3, [r0], #0x02
sub r2, r2, #0x04
b.n MEM_DataCopy2
/* Bits: Src=01, Dst=00 - Byte before half word to long
* Bits: Src=01, Dst=10 - Byte before half word to half word
* 3 bytes to read for long word aligning the source
*/
MEM_DataCopy4:
MEM_DataCopy6:
/* Read B and write B */
ldrb r3, [r1], #0x01
strb r3, [r0], #0x01
sub r2, r2, #0x01
/* Bits: Src=10, Dst=01 - Half word to byte before half word
* Bits: Src=10, Dst=11 - Half word to byte before long word
* 2 bytes to read for long word aligning the source
*/
MEM_DataCopy9:
MEM_DataCopy11:
ldrb r3, [r1], #0x01
strb r3, [r0], #0x01
sub r2, r2, #0x01
/* Bits: Src=11, Dst=00 -chm Byte before long word to long word
* Bits: Src=11, Dst=11 - Byte before long word to half word
* 1 byte to read for long word aligning the source
*/
MEM_DataCopy12:
MEM_DataCopy14:
/* Read B and write B */
ldrb r3, [r1], #0x01
strb r3, [r0], #0x01
sub r2, r2, #0x01
/* Bits: Src=00, Dst=01 - Long to Byte before half word
* Bits: Src=00, Dst=11 - Long to Byte before long word
*/
MEM_DataCopy1: /* Read longs, write B->H->B */
MEM_DataCopy3:
cmp r2, #4
blt MEM_DataCopyBytes
ldr r3, [r1], #0x04
strb r3, [r0], #0x01
lsr r3, r3, #0x08
strh r3, [r0], #0x02
lsr r3, r3, #0x10
strb r3, [r0], #0x01
sub r2, r2, #0x04
b.n MEM_DataCopy3
.size memcpy, .-memcpy
.end
arch/arm/src/armv7-r/arm_mpu.c
+316
View File
@@ -0,0 +1,316 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_mpu.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include "mpu.h"
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifndef CONFIG_ARM_MPU_NREGIONS
# define CONFIG_ARM_MPU_NREGIONS 8
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/* These sets represent the set of disabled memory sub-regions. A bit set
* corresponds to a disabled sub-region; the LS bit corresponds to the first
* region.
*
* The g_ms_regionmask array is indexed by the number of subregions at the
* end of the region: 0 means no sub-regions are available(0xff) and 8 means
* all subregions are available (0x00).
*/
static const uint8_t g_ms_regionmask[9] =
{
0xff, 0xfe, 0xfc, 0xf8, 0xf0, 0xe0, 0xc0, 0x80, 0x00
};
/* The g_ls_regionmask array is indexed by the number of subregions at the
* beginning of the region: 0 means no sub-regions need be disabled (0x00)
* and 8 means all subregions must be disabled (0xff).
*/
static const uint8_t g_ls_regionmask[9] =
{
0x00, 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff
};
/* The next available region number */
static uint8_t g_region;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: mpu_subregion_ms
*
* Description:
* Given (1) the size of the memory to be mapped and (2) the log2 size
* of the mapping to use, determine the minimal sub-region set at the
* to be disabled at the higher end of the region.
*
* Assumption:
* l2size has the same properties as the return value from
* mpu_log2regionceil()
*
****************************************************************************/
static inline uint32_t mpu_subregion_ms(size_t size, uint8_t l2size)
{
unsigned int nsrs;
uint32_t asize;
uint32_t mask;
/* Examples with l2size = 12:
*
* Shifted Adjusted Number Sub-Region
* Size Mask Size Shift Sub-Regions Bitset
* 0x1000 0x01ff 0x1000 9 8 0x00
* 0x0c00 0x01ff 0x0c00 9 6 0xc0
* 0x0c40 0x01ff 0x0e00 9 7 0x80
*/
if (l2size < 32)
{
mask = ((1 << l2size)-1) >> 3; /* Shifted mask */
}
/* The 4Gb region size is a special case */
else
{
/* NOTE: There is no way to represent a 4Gb region size in the 32-bit
* input.
*/
mask = 0x1fffffff; /* Shifted mask */
}
asize = (size + mask) & ~mask; /* Adjusted size */
nsrs = asize >> (l2size-3); /* Number of subregions */
return g_ms_regionmask[nsrs];
}
/****************************************************************************
* Name: mpu_subregion_ls
*
* Description:
* Given (1) the offset to the beginning of data in the region and (2) the
* log2 size of the mapping to use, determine the minimal sub-region set
* to span that memory region sub-region set at the to be disabled at the
* higher end of the region
*
* Assumption:
* l2size has the same properties as the return value from
* mpu_log2regionceil()
*
****************************************************************************/
static inline uint32_t mpu_subregion_ls(size_t offset, uint8_t l2size)
{
unsigned int nsrs;
uint32_t aoffset;
uint32_t mask;
/* Examples with l2size = 12:
*
* Shifted Adjusted Number Sub-Region
* Offset Mask Offset Shift Sub-Regions Bitset
* 0x0000 0x01ff 0x0000 9 8 0x00
* 0x0400 0x01ff 0x0400 9 6 0x03
* 0x02c0 0x01ff 0x0200 9 7 0x01
*/
if (l2size < 32)
{
mask = ((1 << l2size)-1) >> 3; /* Shifted mask */
}
/* The 4Gb region size is a special case */
else
{
/* NOTE: There is no way to represent a 4Gb region size in the 32-bit
* input.
*/
mask = 0x1fffffff; /* Shifted mask */
}
aoffset = offset & ~mask; /* Adjusted offset */
nsrs = aoffset >> (l2size-3); /* Number of subregions */
return g_ls_regionmask[nsrs];
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: mpu_allocregion
*
* Description:
* Allocate the next region
*
* Assumptions:
* - Regions are never deallocated
* - Regions are only allocated early in initialization, so no special
* protection against re-entrancy is required;
*
****************************************************************************/
unsigned int mpu_allocregion(void)
{
DEBUGASSERT(g_region < CONFIG_ARM_MPU_NREGIONS);
return (unsigned int)g_region++;
}
/****************************************************************************
* Name: mpu_log2regionceil
*
* Description:
* Determine the smallest value of l2size (log base 2 size) such that the
* following is true:
*
* size <= (1 << l2size)
*
****************************************************************************/
uint8_t mpu_log2regionceil(size_t size)
{
uint8_t l2size;
/* The minimum permitted region size is 32 bytes (log2(32) = 5. */
for (l2size = 5; l2size < 32 && size > (1 << l2size); l2size++);
return l2size;
}
/****************************************************************************
* Name: mpu_log2regionfloor
*
* Description:
* Determine the largest value of l2size (log base 2 size) such that the
* following is true:
*
* size >= (1 << l2size)
*
****************************************************************************/
uint8_t mpu_log2regionfloor(size_t size)
{
uint8_t l2size = mpu_log2regionceil(size);
if (l2size > 4 && size < (1 << l2size))
{
l2size--;
}
return l2size;
}
/****************************************************************************
* Name: mpu_subregion
*
* Description:
* Given the size of the (1) memory to be mapped and (2) the log2 size
* of the mapping to use, determine the minimal sub-region set to span
* that memory region.
*
* Assumption:
* l2size has the same properties as the return value from
* mpu_log2regionceil()
*
****************************************************************************/
uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size)
{
uint32_t mask;
size_t offset;
uint32_t ret;
/* Eight subregions are supported. The representation is as an 8-bit
* value with the LS bit corresponding to subregion 0. A bit is set
* to disable the sub-region.
*
* l2size: Log2 of the actual region size is <= (1 << l2size);
*/
DEBUGASSERT(l2size > 4 && size <= (1 << l2size));
/* For region sizes of 32, 64, and 128 bytes, the effect of setting
* one or more bits of the SRD field to 1 is UNPREDICTABLE.
*/
if (l2size < 8)
{
return 0;
}
/* Calculate the offset of the base address into the aligned region. */
mask = (1 << l2size) - 1;
offset = base & mask;
/* Calculate the mask need to handle disabled subregions at the end of the
* region
*/
ret = mpu_subregion_ms(size + offset, l2size);
/* Then OR in the mask need to handle disabled subregions at the beginning
* of the region.
*/
ret |= mpu_subregion_ls(offset, l2size);
return ret;
}
arch/arm/src/armv7-r/arm_prefetchabort.c
+175
View File
@@ -0,0 +1,175 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_prefetchabort.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Output debug info if stack dump is selected -- even if debug is not
* selected.
*/
#ifdef CONFIG_ARCH_STACKDUMP
# undef CONFIG_DEBUG
# undef CONFIG_DEBUG_VERBOSE
# define CONFIG_DEBUG 1
# define CONFIG_DEBUG_VERBOSE 1
#endif
#include <stdint.h>
#include <debug.h>
#include <nuttx/irq.h>
#ifdef CONFIG_PAGING
# include <nuttx/page.h>
#endif
#include "sched/sched.h"
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_prefetchabort
*
* Description;
* This is the prefetch abort exception handler. The ARM prefetch abort
* exception occurs when a memory fault is detected during an an
* instruction fetch.
*
****************************************************************************/
#ifdef CONFIG_PAGING
uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
{
uint32_t *savestate;
/* Save the saved processor context in current_regs where it can be accessed
* for register dumps and possibly context switching.
*/
savestate = (uint32_t *)current_regs;
current_regs = regs;
/* Get the (virtual) address of instruction that caused the prefetch abort.
* When the exception occurred, this address was provided in the lr register
* and this value was saved in the context save area as the PC at the
* REG_R15 index.
*
* Check to see if this miss address is within the configured range of
* virtual addresses.
*/
pglldbg("VADDR: %08x VBASE: %08x VEND: %08x\n",
regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND)
{
/* Save the offending PC as the fault address in the TCB of the currently
* executing task. This value is, of course, already known in regs[REG_R15],
* but saving it in this location will allow common paging logic for both
* prefetch and data aborts.
*/
FAR struct tcb_s *tcb = (FAR struct tcb_s *)g_readytorun.head;
tcb->xcp.far = regs[REG_R15];
/* Call pg_miss() to schedule the page fill. A consequences of this
* call are:
*
* (1) The currently executing task will be blocked and saved on
* on the g_waitingforfill task list.
* (2) An interrupt-level context switch will occur so that when
* this function returns, it will return to a different task,
* most likely the page fill worker thread.
* (3) The page fill worker task has been signalled and should
* execute immediately when we return from this exception.
*/
pg_miss();
/* Restore the previous value of current_regs. NULL would indicate that
* we are no longer in an interrupt handler. It will be non-NULL if we
* are returning from a nested interrupt.
*/
current_regs = savestate;
}
else
{
lldbg("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n",
regs[REG_PC], ifar, ifsr);
PANIC();
}
return regs;
}
#else /* CONFIG_PAGING */
uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
{
/* Save the saved processor context in current_regs where it can be accessed
* for register dumps and possibly context switching.
*/
current_regs = regs;
/* Crash -- possibly showing diagnostic debug information. */
lldbg("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n",
regs[REG_PC], ifar, ifsr);
PANIC();
return regs; /* To keep the compiler happy */
}
#endif /* CONFIG_PAGING */
arch/arm/src/armv7-r/arm_releasepending.c
+135
View File
@@ -0,0 +1,135 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_releasepending.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sched.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/sched.h>
#include "sched/sched.h"
#include "group/group.h"
#include "up_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_release_pending
*
* Description:
* Release and ready-to-run tasks that have
* collected in the pending task list. This can call a
* context switch if a new task is placed at the head of
* the ready to run list.
*
****************************************************************************/
void up_release_pending(void)
{
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
slldbg("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the g_readytorun task list */
/* sched_lock(); */
if (sched_mergepending())
{
/* The currently active task has changed! We will need to
* switch contexts.
*/
/* Update scheduler parameters */
sched_suspend_scheduler(rtcb);
/* Are we operating in interrupt context? */
if (current_regs)
{
/* Yes, then we have to do things differently.
* Just copy the current_regs into the OLD rtcb.
*/
up_savestate(rtcb->xcp.regs);
/* Restore the exception context of the rtcb at the (new) head
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s *)g_readytorun.head;
/* Update scheduler parameters */
sched_resume_scheduler(rtcb);
/* Then switch contexts. Any necessary address environment
* changes will be made when the interrupt returns.
*/
up_restorestate(rtcb->xcp.regs);
}
/* Copy the exception context into the TCB of the task that
* was currently active. if up_saveusercontext returns a non-zero
* value, then this is really the previously running task
* restarting!
*/
else if (!up_saveusercontext(rtcb->xcp.regs))
{
/* Restore the exception context of the rtcb at the (new) head
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s *)g_readytorun.head;
/* Update scheduler parameters */
sched_resume_scheduler(rtcb);
/* Then switch contexts */
up_fullcontextrestore(rtcb->xcp.regs);
}
}
}
arch/arm/src/armv7-r/arm_reprioritizertr.c
+189
View File
@@ -0,0 +1,189 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_reprioritizertr.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <sched.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/sched.h>
#include "sched/sched.h"
#include "group/group.h"
#include "up_internal.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_reprioritize_rtr
*
* Description:
* Called when the priority of a running or
* ready-to-run task changes and the reprioritization will
* cause a context switch. Two cases:
*
* 1) The priority of the currently running task drops and the next
* task in the ready to run list has priority.
* 2) An idle, ready to run task's priority has been raised above the
* the priority of the current, running task and it now has the
* priority.
*
* Inputs:
* tcb: The TCB of the task that has been reprioritized
* priority: The new task priority
*
****************************************************************************/
void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
{
/* Verify that the caller is sane */
if (tcb->task_state < FIRST_READY_TO_RUN_STATE ||
tcb->task_state > LAST_READY_TO_RUN_STATE
#if SCHED_PRIORITY_MIN > 0
|| priority < SCHED_PRIORITY_MIN
#endif
#if SCHED_PRIORITY_MAX < UINT8_MAX
|| priority > SCHED_PRIORITY_MAX
#endif
)
{
PANIC();
}
else
{
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
bool switch_needed;
slldbg("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just
* remove the head of the ready to run list.
*/
switch_needed = sched_removereadytorun(tcb);
/* Setup up the new task priority */
tcb->sched_priority = (uint8_t)priority;
/* Return the task to the specified blocked task list.
* sched_addreadytorun will return true if the task was
* added to the new list. We will need to perform a context
* switch only if the EXCLUSIVE or of the two calls is non-zero
* (i.e., one and only one the calls changes the head of the
* ready-to-run list).
*/
switch_needed ^= sched_addreadytorun(tcb);
/* Now, perform the context switch if one is needed */
if (switch_needed)
{
/* If we are going to do a context switch, then now is the right
* time to add any pending tasks back into the ready-to-run list.
* task list now
*/
if (g_pendingtasks.head)
{
sched_mergepending();
}
/* Update scheduler parameters */
sched_suspend_scheduler(rtcb);
/* Are we in an interrupt handler? */
if (current_regs)
{
/* Yes, then we have to do things differently.
* Just copy the current_regs into the OLD rtcb.
*/
up_savestate(rtcb->xcp.regs);
/* Restore the exception context of the rtcb at the (new) head
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s *)g_readytorun.head;
/* Update scheduler parameters */
sched_resume_scheduler(rtcb);
/* Then switch contexts. Any necessary address environment
* changes will be made when the interrupt returns.
*/
up_restorestate(rtcb->xcp.regs);
}
/* Copy the exception context into the TCB at the (old) head of the
* g_readytorun Task list. if up_saveusercontext returns a non-zero
* value, then this is really the previously running task restarting!
*/
else if (!up_saveusercontext(rtcb->xcp.regs))
{
/* Restore the exception context of the rtcb at the (new) head
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s *)g_readytorun.head;
/* Update scheduler parameters */
sched_resume_scheduler(rtcb);
/* Then switch contexts */
up_fullcontextrestore(rtcb->xcp.regs);
}
}
}
}
arch/arm/src/armv7-r/arm_restorefpu.S
+110
View File
@@ -0,0 +1,110 @@
/************************************************************************************
* arch/arm/src/armv7-r/arm_restorefpu.S
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <arch/irq.h>
#ifdef CONFIG_ARCH_FPU
/************************************************************************************
* Public Symbols
************************************************************************************/
.globl up_restorefpu
#ifdef CONFIG_ARCH_FPU
.cpu cortex-r4
#else
.cpu cortex-r4f
#endif
.syntax unified
.file "arm_restorefpu.S"
/************************************************************************************
* Public Functions
************************************************************************************/
.text
/************************************************************************************
* Name: up_restorefpu
*
* Description:
* Given the pointer to a register save area (in R0), restore the state of the
* floating point registers.
*
* C Function Prototype:
* void up_restorefpu(const uint32_t *regs);
*
* Input Parameters:
* regs - A pointer to the register save area containing the floating point
* registers.
*
* Returned Value:
* This function does not return anything explicitly. However, it is called from
* interrupt level assembly logic that assumes that r0 is preserved.
*
************************************************************************************/
.globl up_restorefpu
.type up_restorefpu, function
up_restorefpu:
add r1, r0, #(4*REG_S0) /* R1=Address of FP register storage */
/* Load all floating point registers. Registers are loaded in numeric order,
* s0, s1, ... in increasing address order.
*/
vldmia r1!, {s0-s31} /* Restore the full FP context */
/* Load the floating point control and status register. At the end of the
* vstmia, r1 will point to the FPCSR storage location.
*/
ldr r2, [r1], #4 /* Fetch the floating point control and status register */
vmsr fpscr, r2 /* Restore the FPCSR */
bx lr
.size up_restorefpu, .-up_restorefpu
#endif /* CONFIG_ARCH_FPU */
.end

Some files were not shown because too many files have changed in this diff Show More