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imxrt mpuinit:Set Data and Code Type to Normal

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Strongly-Ordered requires aligned access unless
  caching is enabled.

  Normal memory
  Accesses to normal memory region are idempotent...
  - unaligned accesses can be supported
This commit is contained in:
David Sidrane
2021-10-27 13:04:35 -07:00
committed by Xiang Xiao
parent 34c3efcb91
commit 5022244339
1 changed files with 16 additions and 16 deletions
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arch/arm/src/imxrt/imxrt_mpuinit.c
+16 -16
View File
@@ -143,49 +143,49 @@ void imxrt_mpu_initialize(void)
* Instruction access */
mpu_configure_region(IMXRT_FLEXCIPHER_BASE, 8 * 1024 * 1024,
MPU_RASR_TEX_SO | /* Ordered */
MPU_RASR_C | /* Cacheable */
MPU_RASR_TEX_NOR | /* Normal */
RASR_C_VALUE | /* Cacheable */
MPU_RASR_B | /* Bufferable
* Not Shareable */
MPU_RASR_AP_RORO); /* P:RO U:RO
* Instruction access */
mpu_configure_region(IMXRT_ITCM_BASE, 128 * 1024,
MPU_RASR_TEX_SO | /* Ordered */
MPU_RASR_C | /* Cacheable */
MPU_RASR_B | /* Bufferable
MPU_RASR_TEX_NOR | /* Normal */
RASR_C_VALUE | /* Cacheable */
RASR_B_VALUE | /* Bufferable
* Not Shareable */
MPU_RASR_AP_RWRW); /* P:RW U:RW
* Instruction access */
mpu_configure_region(IMXRT_DTCM_BASE, 128 * 1024,
MPU_RASR_TEX_SO | /* Ordered */
MPU_RASR_C | /* Cacheable */
MPU_RASR_B | /* Bufferable
MPU_RASR_TEX_NOR | /* Normal */
RASR_C_VALUE | /* Cacheable */
RASR_B_VALUE | /* Bufferable
* Not Shareable */
MPU_RASR_AP_RWRW); /* P:RW U:RW
* Instruction access */
mpu_configure_region(IMXRT_OCRAM2_BASE, 512 * 1024,
MPU_RASR_TEX_SO | /* Ordered */
MPU_RASR_C | /* Cacheable */
MPU_RASR_B | /* Bufferable
MPU_RASR_TEX_NOR | /* Normal */
RASR_C_VALUE | /* Cacheable */
RASR_B_VALUE | /* Bufferable
* Not Shareable */
MPU_RASR_AP_RWRW); /* P:RW U:RW
* Instruction access */
mpu_configure_region(IMXRT_OCRAM_BASE, 512 * 1024,
MPU_RASR_TEX_SO | /* Ordered */
MPU_RASR_C | /* Cacheable */
MPU_RASR_B | /* Bufferable
MPU_RASR_TEX_NOR | /* Normal */
RASR_C_VALUE | /* Cacheable */
RASR_B_VALUE | /* Bufferable
* Not Shareable */
MPU_RASR_AP_RWRW); /* P:RW U:RW
* Instruction access */
mpu_configure_region(IMXRT_EXTMEM_BASE, 32 * 1024 * 1024,
MPU_RASR_TEX_SO | /* Ordered */
MPU_RASR_C | /* Cacheable */
MPU_RASR_B | /* Bufferable
RASR_C_VALUE | /* Cacheable */
RASR_B_VALUE | /* Bufferable
* Not Shareable */
MPU_RASR_AP_RWRW); /* P:RW U:RW
* Instruction access */