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Add PHY setup for STM3240G-EVAL Ethernet driver

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4151 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2011-12-09 17:03:16 +00:00
parent 55ec626661
commit 4fee2145bd
8 changed files with 615 additions and 39 deletions
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arch/arm/src/stm32/chip/stm32_eth.h
+11 -3
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@@ -245,10 +245,18 @@
#define ETH_MACMIIAR_MW (1 << 1) /* Bit 1: MII write */
#define ETH_MACMIIAR_CR_SHIFT (2) /* Bits 2-4: Clock range */
#define ETH_MACMIIAR_CR_MASK (7 << ETH_MACMIIAR_CR_SHIFT)
# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHz HCLK/42 */
#if 0 /* Per the reference manual */
# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHzHCLK/42 */
# define ETH_MACMIIAR_CR_100_168 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-168 MHz HCLK/62 */
# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */
# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */
# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */
# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */
#else /* Per the driver example */
# define ETH_MACMIIAR_CR_60_100 (0 << ETH_MACMIIAR_CR_SHIFT) /* 000 60-100 MHz HCLK/42 */
# define ETH_MACMIIAR_CR_100_150 (1 << ETH_MACMIIAR_CR_SHIFT) /* 001 100-150 MHz HCLK/62 */
# define ETH_MACMIIAR_CR_20_35 (2 << ETH_MACMIIAR_CR_SHIFT) /* 010 20-35 MHz HCLK/16 */
# define ETH_MACMIIAR_CR_35_60 (3 << ETH_MACMIIAR_CR_SHIFT) /* 011 35-60 MHz HCLK/26 */
# define ETH_MACMIIAR_CR_150_168 (4 << ETH_MACMIIAR_CR_SHIFT) /* 100 150-168 MHz HCLK/102 */
#endif
#define ETH_MACMIIAR_MR_SHIFT (6) /* Bits 6-10: MII register */
#define ETH_MACMIIAR_MR_MASK (31 << ETH_MACMIIAR_MR_SHIFT)
#define ETH_MACMIIAR_PA_SHIFT (11) /* Bits 11-15: PHY address */
arch/arm/src/stm32/stm32_eth.c
+493 -30
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File diff suppressed because it is too large Load Diff
arch/arm/src/stm32/stm32f40xxx_rcc.c
+8 -2
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@@ -184,8 +184,14 @@ static inline void rcc_enableahb1(void)
#ifdef CONFIG_STM32_ETHMAC
/* Ethernet MAC clocking */
regval |= (RCC_AHB1ENR_ETHMACEN|RCC_AHB1ENR_ETHMACTXEN|
RCC_AHB1ENR_ETHMACRXEN|RCC_AHB1ENR_ETHMACPTPEN);
regval |= (RCC_AHB1ENR_ETHMACEN|RCC_AHB1ENR_ETHMACTXEN|RCC_AHB1ENR_ETHMACRXEN);
#ifdef CONFIG_STM32_ETH_PTP
/* Precision Time Protocol (PTP) */
regval |= RCC_AHB1ENR_ETHMACPTPEN;
#endif
#endif
#ifdef CONFIG_STM32_OTGHS
arch/mips/src/pic32mx/pic32mx-head.S
+3 -1
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@@ -161,7 +161,9 @@ __reset:
* Name: _gen_exception
*
* Description:
* General Exception Vector Handler. Jumps to _exception_handler
* General Exception Vector Handler. Jumps to _exception_handler. NOTE:
* we set the BEV bit in the status register so all interrupt vectors
* should go through the _bev_exception.
*
* Input Parameters:
* None
configs/stm3240g-eval/README.txt
+19
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@@ -374,10 +374,29 @@ STM3240G-EVAL-specific Configuration Options
CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
4-bit transfer mode.
CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
CONFIG_STM32_MII - Support Ethernet MII interface
CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
CONFIG_STM32_RMII - Support Ethernet RMII interface
CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode
CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
may be defined to select full duplex mode. Default: half-duplex
CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
may be defined to select 100 MBps speed. Default: 10 Mbps
CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
defined. The PHY status register address may diff from PHY to PHY. This
configuration sets the address of the PHY status register.
CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
defined. This provides bit mask indicating 10 or 100MBps speed.
CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
defined. This provides the value of the speed bit(s) indicating 100MBps speed.
CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
defined. This provide bit mask indicating full or half duplex modes.
CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
defined. This provides the value of the mode bits indicating full duplex mode.
CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported
but some hooks are indicated with this condition.
STM3240G-EVAL LCD Hardware Configuration
configs/stm3240g-eval/include/board.h
+21 -1
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@@ -172,8 +172,26 @@
# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif
/* LED definitions ******************************************************************/
/* Ethernet *************************************************************************/
/* We need to provide clocking to the MII PHY via MCO1 (PA8) */
#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC)
# if !defined(CONFIG_STM32_MII)
# warning "CONFIG_STM32_MII required for Ethernet"
# elif !defined(CONFIG_STM32_MII_MCO1)
# warning "CONFIG_STM32_MII_MCO1 required for Ethernet MII"
# else
/* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */
# define BOARD_CFGR_MC01_SOURCE RCC_CFGR_MCO1_HSE
# define BOARD_CFGR_MC01_DIVIDER RCC_CFGR_MCO1PRE_NONE
# endif
#endif
/* LED definitions ******************************************************************/
/* The STM3240G-EVAL board has 4 LEDs that we will encode as: */
#define LED_STARTED 0 /* LED1 */
@@ -185,6 +203,7 @@
#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */
#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */
/* Button definitions ***************************************************************/
/* The STM3240G-EVAL supports three buttons: */
#define BUTTON_WAKEUP 0
@@ -200,6 +219,7 @@
/* Alternate function pin selections ************************************************/
/* UART3:
*
* - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open)
* - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX
*/
configs/stm3240g-eval/nsh/defconfig
+30 -1
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@@ -258,15 +258,44 @@ CONFIG_SSI_POLLWAIT=y
#
# STM32F40xxx Ethernet device driver settings
#
# CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
# CONFIG_STM32_MII - Support Ethernet MII interface
# CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
# CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
# CONFIG_STM32_RMII - Support Ethernet RMII interface
# CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode
# CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
# may be defined to select full duplex mode. Default: half-duplex
# CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
# may be defined to select 100 MBps speed. Default: 10 Mbps
# CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
# defined. The PHY status register address may diff from PHY to PHY. This
# configuration sets the address of the PHY status register.
# CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
# defined. This provides bit mask indicating 10 or 100MBps speed.
# CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
# defined. This provides the value of the speed bit(s) indicating 100MBps speed.
# CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
# defined. This provide bit mask indicating full or half duplex modes.
# CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
# defined. This provides the value of the mode bits indicating full duplex mode.
# CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported
# but some hooks are indicated with this condition.
#
CONFIG_STM32_PHYADDR=0x01
CONFIG_STM32_MII=y
CONFIG_STM32_MII_MCO1=y
CONFIG_STM32_MII_MCO2=n
CONFIG_STM32_RMII=n
CONFIG_STM32_AUTONEG=y
#CONFIG_STM32_ETHFD
#CONFIG_STM32_ETH100MB
CONFIG_STM32_PHYSR=16
CONFIG_STM32_PHYSR_SPEED=0x0002
CONFIG_STM32_PHYSR_100MBPS=0x0000
CONFIG_STM32_PHYSR_MODE=0x0004
CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004
CONFIG_STM32_ETH_PTP=n
#
# General build options
@@ -684,7 +713,7 @@ CONFIG_NET=n
CONFIG_NET_IPv6=n
CONFIG_NSOCKET_DESCRIPTORS=10
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_BUFSIZE=420
CONFIG_NET_BUFSIZE=562
CONFIG_NET_TCP=y
CONFIG_NET_TCP_CONNS=40
CONFIG_NET_MAX_LISTENPORTS=40
configs/stm3240g-eval/ostest/defconfig
+30 -1
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@@ -258,15 +258,44 @@ CONFIG_SSI_POLLWAIT=y
#
# STM32F40xxx Ethernet device driver settings
#
# CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
# CONFIG_STM32_MII - Support Ethernet MII interface
# CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
# CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
# CONFIG_STM32_RMII - Support Ethernet RMII interface
# CONFIG_STM32_AUTONEG - Use PHY autonegotion to determine speed and mode
# CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
# may be defined to select full duplex mode. Default: half-duplex
# CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
# may be defined to select 100 MBps speed. Default: 10 Mbps
# CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
# defined. The PHY status register address may diff from PHY to PHY. This
# configuration sets the address of the PHY status register.
# CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
# defined. This provides bit mask indicating 10 or 100MBps speed.
# CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
# defined. This provides the value of the speed bit(s) indicating 100MBps speed.
# CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
# defined. This provide bit mask indicating full or half duplex modes.
# CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
# defined. This provides the value of the mode bits indicating full duplex mode.
# CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported
# but some hooks are indicated with this condition.
#
CONFIG_STM32_PHYADDR=0x01
CONFIG_STM32_MII=y
CONFIG_STM32_MII_MCO1=y
CONFIG_STM32_MII_MCO2=n
CONFIG_STM32_RMII=n
CONFIG_STM32_AUTONEG=y
#CONFIG_STM32_ETHFD
#CONFIG_STM32_ETH100MBPS
CONFIG_STM32_PHYSR=16
CONFIG_STM32_PHYSR_SPEED=0x0002
CONFIG_STM32_PHYSR_100MBPS=0x0000
CONFIG_STM32_PHYSR_MODE=0x0004
CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004
CONFIG_STM32_ETH_PTP=n
#
# General build options
@@ -648,7 +677,7 @@ CONFIG_NET=n
CONFIG_NET_IPv6=n
CONFIG_NSOCKET_DESCRIPTORS=0
CONFIG_NET_SOCKOPTS=y
CONFIG_NET_BUFSIZE=420
CONFIG_NET_BUFSIZE=562
CONFIG_NET_TCP=n
CONFIG_NET_TCP_CONNS=40
CONFIG_NET_MAX_LISTENPORTS=40