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arm/stm32g0: Add USB device controller support
Add the STM32G0 USB interrupt, memory map, register layout, HSI48 clocking, power control, packet memory handling, and device-controller support. Assisted-by: OpenAI Codex Signed-off-by: jsanchez-2g <jsanchez@2g-eng.com>
This commit is contained in:
jsanchez-2g
Xiang Xiao
@@ -90,6 +90,7 @@
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#else
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# define STM32_IRQ_UCPD12 (STM32_IRQ_EXTINT + 8) /* 8: UCPD1_2 */
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# define STM32_IRQ_EXTI32_33 (STM32_IRQ_EXTINT + 8) /* 8: EXTI_32_33 */
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# define STM32_IRQ_USB (STM32_IRQ_EXTINT + 8) /* 8: USB */
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#endif
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#define STM32_IRQ_DMA1CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA1_CH1 */
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@@ -40,39 +40,44 @@
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/* Endpoint Registers */
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#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */
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#define STM32_USB_EPR_OFFSET(n) ((n) << 2)
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#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */
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#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */
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#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */
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#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */
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#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */
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#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */
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#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */
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#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */
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#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register */
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#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register */
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#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register */
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#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register */
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#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register */
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#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register */
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#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register */
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#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register */
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/* Common Registers */
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#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */
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#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */
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#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */
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#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */
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#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */
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#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register (16-bits) */
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#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector (16-bits) */
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#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register */
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#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register */
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#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register */
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#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address */
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#ifndef CONFIG_STM32_STM32G0
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# define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */
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#endif
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#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */
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#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */
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/* Buffer Descriptor Table (Relatative to BTABLE address) */
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/* Buffer Descriptor Table (Relative to BTABLE address) */
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#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */
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#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */
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#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */
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#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */
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#define STM32_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o))
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#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET)
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#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET)
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#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET)
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#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET)
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#ifdef CONFIG_STM32_STM32G0
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# define STM32_USB_TX_WOFFSET (0) /* Transmission descriptor n (32-bits) */
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# define STM32_USB_RX_WOFFSET (4) /* Reception descriptor n (32-bits) */
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# define STM32_USB_BTABLE_RADDR(ep,o) \
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(STM32_USBRAM_BASE + ((ep) << 3) + (o))
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#else
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# define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */
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# define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */
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# define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */
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# define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */
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# define STM32_USB_BTABLE_RADDR(ep,o) \
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((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3) + (o))
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#endif
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/* Register Addresses *******************************************************/
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@@ -94,17 +99,26 @@
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#define STM32_USB_ISTR (STM32_USB_BASE + STM32_USB_ISTR_OFFSET)
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#define STM32_USB_FNR (STM32_USB_BASE + STM32_USB_FNR_OFFSET)
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#define STM32_USB_DADDR (STM32_USB_BASE + STM32_USB_DADDR_OFFSET)
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#define STM32_USB_BTABLE (STM32_USB_BASE + STM32_USB_BTABLE_OFFSET)
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#ifndef CONFIG_STM32_STM32G0
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# define STM32_USB_BTABLE (STM32_USB_BASE + STM32_USB_BTABLE_OFFSET)
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#endif
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#define STM32_USB_LPMCSR (STM32_USB_BASE + STM32_USB_LPMCSR_OFFSET)
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#define STM32_USB_BCDR (STM32_USB_BASE + STM32_USB_BCDR_OFFSET)
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/* Buffer Descriptor Table (Relative to BTABLE address) */
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#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USBRAM_BASE + STM32_USB_BTABLE_RADDR(ep,o))
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#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET)
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#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET)
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#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET)
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#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET)
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#ifdef CONFIG_STM32_STM32G0
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# define STM32_USB_BTABLE_ADDR(ep,o) STM32_USB_BTABLE_RADDR(ep,o)
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# define STM32_USB_TX(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_TX_WOFFSET)
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# define STM32_USB_RX(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_RX_WOFFSET)
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#else
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# define STM32_USB_BTABLE_ADDR(ep,o) \
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(STM32_USBRAM_BASE + STM32_USB_BTABLE_RADDR(ep,o))
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# define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET)
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# define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET)
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# define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET)
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# define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET)
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#endif
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/* Register Bitfield Definitions ********************************************/
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@@ -239,16 +253,27 @@
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/* Reception buffer address */
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#define USB_ADDR_RX_ZERO (1 << 0) /* Bit 0 This bit must always be written as ‘0’ */
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#define USB_ADDR_RX_SHIFT (1) /* Bits 15:1 ADDRn_RX[15:1]: Reception Buffer Address */
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#define USB_ADDR_RX_MASK (0x7fff << USB_ADDR_RX_SHIFT)
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#ifdef CONFIG_STM32_STM32G0
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# define USB_ADDR_RX_SHIFT (2) /* Bits 15:2: Reception buffer address */
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# define USB_ADDR_RX_MASK (0x3fff << USB_ADDR_RX_SHIFT)
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#else
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# define USB_ADDR_RX_ZERO (1 << 0) /* Bit 0 must always be written as zero */
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# define USB_ADDR_RX_SHIFT (1) /* Bits 15:1: Reception buffer address */
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# define USB_ADDR_RX_MASK (0x7fff << USB_ADDR_RX_SHIFT)
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#endif
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/* Reception byte count */
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#define USB_COUNT_RX_BL_SIZE (1 << 15) /* Bit 15: BLock SIZE. */
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#define USB_COUNT_RX_NUM_BLOCK_SHIFT (10) /* Bits 14-10: Number of blocks */
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#ifdef CONFIG_STM32_STM32G0
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# define USB_COUNT_RX_BL_SIZE (1 << 31) /* Bit 31: Block size */
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# define USB_COUNT_RX_NUM_BLOCK_SHIFT (26) /* Bits 30-26: Number of blocks */
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# define USB_COUNT_RX_SHIFT (16) /* Bits 25-16: Reception byte count */
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#else
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# define USB_COUNT_RX_BL_SIZE (1 << 15) /* Bit 15: Block size */
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# define USB_COUNT_RX_NUM_BLOCK_SHIFT (10) /* Bits 14-10: Number of blocks */
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# define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception byte count */
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#endif
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#define USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT)
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#define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */
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#define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT)
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#endif /* CONFIG_STM32_HAVE_USBDEV */
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@@ -216,6 +216,25 @@ void stm32_pwr_enablebreg(bool region);
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void stm32_pwr_setvos(uint16_t vos);
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#endif
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/****************************************************************************
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* Name: stm32_pwr_enableusv
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*
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* Description:
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* Declare the USB supply valid or not valid. The USB transceiver cannot
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* be used on STM32G0 until the supply has been declared valid.
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*
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* Input Parameters:
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* enable - True: USB supply is valid; False: USB supply is not valid.
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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#ifdef CONFIG_STM32_STM32G0
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void stm32_pwr_enableusv(bool enable);
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#endif
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/****************************************************************************
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* Name: stm32_pwr_setpvd
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*
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@@ -34,6 +34,7 @@
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#include <nuttx/irq.h>
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#include "arm_internal.h"
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#include "hardware/stm32_rcc.h"
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#include "stm32_pwr.h"
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#if defined(CONFIG_STM32_PWR)
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@@ -91,6 +92,51 @@ void stm32_pwr_setvos(uint16_t vos)
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}
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}
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/****************************************************************************
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* Name: stm32_pwr_enableusv
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*
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* Description:
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* Declare the USB supply valid or not valid. The USB transceiver cannot
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* be used on STM32G0 until the supply has been declared valid.
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*
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* Input Parameters:
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* enable - True: USB supply is valid; False: USB supply is not valid.
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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#ifdef CONFIG_STM32_STM32G0
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void stm32_pwr_enableusv(bool enable)
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{
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uint32_t regval;
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bool wasenabled;
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regval = getreg32(STM32_RCC_APB1ENR);
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wasenabled = (regval & RCC_APB1ENR_PWREN) != 0;
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if (!wasenabled)
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{
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modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_PWREN);
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}
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if (enable)
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{
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modifyreg32(STM32_PWR_CR2, 0, PWR_CR2_USV);
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}
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else
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{
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modifyreg32(STM32_PWR_CR2, PWR_CR2_USV, 0);
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}
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if (!wasenabled)
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{
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modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_PWREN, 0);
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}
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}
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#endif
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/* TODO Other stm32_pwr_* functions need to be implemented */
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#endif /* CONFIG_STM32_PWR */
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File diff suppressed because it is too large
Load Diff
@@ -74,6 +74,7 @@
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#define STM32_USART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff USART4 */
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#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */
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#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */
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#define STM32_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB */
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#define STM32_CRS_BASE 0x40006C00 /* 0x40006C00-0x40006fff CRS */
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#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */
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#define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff DAC 1 */
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@@ -81,6 +82,8 @@
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#define STM32_LPTIM1_BASE 0x40007C00 /* 0x40007c00-0x40007fff LPTIM1 */
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#define STM32_LPUART1_BASE 0x40008000 /* 0x40008000-0x400083ff LPUART1 */
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#define STM32_LPTIM2_BASE 0x40009400 /* 0x40009400-0x400097ff LPTIM2 */
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#define STM32_USBRAM_BASE 0x40009800 /* 0x40009800-0x40009bff USB RAM1 */
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#define STM32_USBRAM2_BASE 0x40009c00 /* 0x40009c00-0x40009fff USB RAM2 */
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#define STM32_UCPD1_BASE 0x4000a000 /* 0x4000a000-0x4000a3ff UCPD1 */
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#define STM32_UCPD2_BASE 0x4000a400 /* 0x4000a400-0x4000a7ff UCPD2 */
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#define STM32_TAMP_BASE 0x4000b000 /* 0x4000b000-0x4000b3ff TAMP */
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@@ -273,6 +273,11 @@
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#define GPIO_USART4_TX_2 (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN10)
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#define GPIO_USART4_RTS_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN15)
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/* USB */
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#define GPIO_USB_DM (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN11)
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#define GPIO_USB_DP (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN12)
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/* TODO: LPTIM */
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/* TODO: LPUART */
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@@ -120,6 +120,7 @@
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#define PWR_CR2_PVDFT_MASK (7 << PWR_CR2_PLS_SHIFT)
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#define PWR_CR2_PVDRT_SHIFT (4) /* Bits 4-6: Power voltage detector rising threshold selection */
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#define PWR_CR2_PVDRT_MASK (7 << PWR_CR2_PLS_SHIFT)
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#define PWR_CR2_USV (1 << 10) /* Bit 10: USB supply valid */
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/* Power control register 3 */
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@@ -220,7 +220,8 @@
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/* Bits 2-3: Reserved */
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#define RCC_APB1RSTR_TIM6RST (1 << 4) /* Bit 4: Timer 6 reset */
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#define RCC_APB1RSTR_TIM7RST (1 << 5) /* Bit 5: Timer 7 reset */
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/* Bits 6-13: Reserved */
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/* Bits 6-12: Reserved */
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#define RCC_APB1RSTR_USBRST (1 << 13) /* Bit 13: USB reset */
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#define RCC_APB1RSTR_SPI2RST (1 << 14) /* Bit 14: SPI 2 reset */
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/* Bits 15-16: Reserved */
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#define RCC_APB1RSTR_USART2RST (1 << 17) /* Bit 17: USART 2 reset */
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@@ -284,9 +285,11 @@
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/* Bits 2-3: Reserved */
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#define RCC_APB1ENR_TIM6EN (1 << 4) /* Bit 4: Timer 6 enable */
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#define RCC_APB1ENR_TIM7EN (1 << 5) /* Bit 5: Timer 7 enable */
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/* Bits 6-13: Reserved */
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/* Bits 6-12: Reserved */
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#define RCC_APB1ENR_USBEN (1 << 13) /* Bit 13: USB enable */
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#define RCC_APB1ENR_SPI2EN (1 << 14) /* Bit 14: SPI 2 enable */
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/* Bits 15-16: Reserved */
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/* Bit 15: Reserved */
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#define RCC_APB1ENR_CRSEN (1 << 16) /* Bit 16: CRS enable */
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#define RCC_APB1ENR_USART2EN (1 << 17) /* Bit 17: USART 2 enable */
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#define RCC_APB1ENR_USART3EN (1 << 18) /* Bit 18: USART 3 enable */
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#define RCC_APB1ENR_USART4EN (1 << 19) /* Bit 19: USART 4 enable */
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@@ -54,6 +54,12 @@
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# endif
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#endif
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/* HSI48 is the only 48MHz clock source on STM32G0 */
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#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48)
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# define STM32_USE_HSI48
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#endif
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static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
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"Configure BOARD_LOOPSPERMSEC to non-default value.");
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@@ -205,6 +205,12 @@ static inline void rcc_enableapb1(void)
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regval |= RCC_APB1ENR_TIM7EN;
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#endif
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#ifdef CONFIG_STM32_USB
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/* USB clock enable */
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regval |= RCC_APB1ENR_USBEN;
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#endif
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#ifdef CONFIG_STM32_SPI2
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/* SPI 2 clock enable */
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@@ -241,6 +247,12 @@ static inline void rcc_enableapb1(void)
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regval |= RCC_APB1ENR_I2C1EN;
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#endif
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#if defined(CONFIG_STM32_CRS) || defined(STM32_USE_HSI48)
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/* Clock recovery system clock enable */
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regval |= RCC_APB1ENR_CRSEN;
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#endif
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#ifdef CONFIG_STM32_I2C2
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/* I2C 2 clock enable */
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@@ -674,6 +686,12 @@ static inline void rcc_enableperipherals(void)
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rcc_enableahb();
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rcc_enableapb2();
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rcc_enableapb1();
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#ifdef STM32_USE_HSI48
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||||
/* Enable HSI48 clocking to support USB transfers or RNG */
|
||||
|
||||
stm32_enable_hsi48(STM32_HSI48_SYNCSRC);
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
Reference in New Issue
Block a user