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Add register definitions for SAM4L BPM and SCIF blocks; SAM4L clock initialization now selects an optimal power scaling mode
This commit is contained in:
Gregory Nutt
@@ -54,66 +54,73 @@
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* After power-on reset, the sam3u device is running on a 4MHz internal RC. These
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* definitions will configure clocking with MCK = 48MHz, PLLA = 96, and CPU=48MHz.
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/* Select the DFLL as the source of the system clock.
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*
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* Options (define one):
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* BOARD_SYSCLK_SOURCE_RCSYS - System RC oscillator
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* BOARD_SYSCLK_SOURCE_OSC0 - Oscillator 0
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* BOARD_SYSCLK_SOURCE_PLL0 - Phase Locked Loop 0
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* BOARD_SYSCLK_SOURCE_DFLL0 - Digital Frequency Locked Loop
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* BOARD_SYSCLK_SOURCE_RC80M - 80 MHz RC oscillator
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* BOARD_SYSCLK_SOURCE_FCFAST12M - 12 MHz RC oscillator
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* BOARD_SYSCLK_SOURCE_FCFAST8M - 8 MHz RC oscillator
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* BOARD_SYSCLK_SOURCE_FCFAST4M - 4 MHz RC oscillator
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* BOARD_SYSCLK_SOURCE_RC1M - 1 MHz RC oscillator
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*/
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/* Main oscillator register settings */
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#define BOARD_SYSCLK_SOURCE_DFLL0 1
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#define BOARD_CKGR_MOR_MOSCXTST (63 << CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
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/* Nominal frequencies in on-chip RC oscillators. These are *not* configurable
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* but appear here for use in frequency calculations. NOTE: These may frequencies
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* may vary with temperature changes.
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*/
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/* PLLA configuration */
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#define BOARD_RCSYS_FREQUENCY 115000 /* Nominal frequency of RCSYS (Hz) */
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#define BOARD_RC32K_FREQUENCY 32768 /* Nominal frequency of RC32K (Hz) */
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#define BOARD_RC80M_FREQUENCY 80000000 /* Nominal frequency of RC80M (Hz) */
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#define BOARD_RCFAST4M_FREQUENCY 4000000 /* Nominal frequency of RCFAST4M (Hz) */
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#define BOARD_RCFAST8M_FREQUENCY 8000000 /* Nominal frequency of RCFAST8M (Hz) */
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#define BOARD_RCFAST12M_FREQUENCY 12000000 /* Nominal frequency of RCFAST12M (Hz) */
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#define BOARD_RC1M_FREQUENCY 1000000 /* Nominal frequency of RC1M (Hz) */
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#define BOARD_CKGR_PLLAR_MULA (7 << CKGR_PLLAR_MULA_SHIFT)
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#define BOARD_CKGR_PLLAR_STMODE CKGR_PLLAR_STMODE_FAST
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#define BOARD_CKGR_PLLAR_PLLACOUNT (63 << CKGR_PLLAR_PLLACOUNT_SHIFT)
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#define BOARD_CKGR_PLLAR_DIVA CKGR_PLLAR_DIVA_BYPASS
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/* On-board crystal frequencies */
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/* PMC master clock register settings */
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#define BOARD_OSC32_FREQUENCY 32768
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#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
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#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2
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/* Digital Frequency Locked Loop configuration
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* Fdfll = (Fclk * DFLLmul) / DFLLdiv
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* = 32768 * (48000000/32760) / 1 = 48MHz
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*
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* DFLL0 source options (select one):
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* BOARD_DFLL0_SOURCE_RCSYS - System RC oscillator
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* BOARD_DFLL0_SOURCE_OSC32K - 32.768KHz oscillator
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* BOARD_DFLL0_SOURCE_OSC0 - Oscillator 0
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* BOARD_DFLL0_SOURCE_RC80M - 80 MHz RC oscillator
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* BOARD_DFLL0_SOURCE_RC32K - 32 kHz RC oscillator
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*/
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/* USB UTMI PLL start-up time */
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#define BOARD_DFLL0_SOURCE_OSC32K 1
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#define BOARD_FDLL0_FREQUENCY 48000000
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#define BOARD_FDLL0_MUL (BOARD_FDLL0_FREQUENCY / BOARD_OSC32_FREQUENCY)
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#define BOARD_FDLL0_DIV 1
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#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << CKGR_UCKR_UPLLCOUNT_SHIFT)
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/* System clock dividers: Fbus = Fsys >> BUSshift */
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/* System clock dividers: Fbus = Fsys / (2 ^ BUS_div) */
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#define BOARD_SYSCLK_CPU_DIV 0
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#define BOARD_SYSCLK_PBA_DIV 0
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#define BOARD_SYSCLK_PBB_DIV 0
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#define BOARD_SYSCLK_PBC_DIV 0
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#define BOARD_SYSCLK_PBD_DIV 0
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#define BOARD_CPU_SHIFT 0 /* Fcpu = Fsys = 48MHz */
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#define BOARD_PBA_SHIFT 0 /* Fpba = Fsys = 48MHz */
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#define BOARD_PBB_SHIFT 0 /* Fpbb = Fsys = 48MHz */
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#define BOARD_PBC_SHIFT 0 /* Fpbc = Fsys = 48MHz */
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#define BOARD_PBD_SHIFT 0 /* Fpbd = Fsys = 48MHz */
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/* Resulting frequencies */
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#define SAM_MAINOSC_FREQUENCY (12000000)
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#define SAM_MCK_FREQUENCY (48000000)
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#define SAM_PLLA_FREQUENCY (96000000)
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#define SAM_CPU_FREQUENCY (48000000)
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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* divided by (2*(CLKDIV+1)).
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*
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* MCI_SPEED = MCK / (2*(CLKDIV+1))
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* CLKDIV = MCI / MCI_SPEED / 2 - 1
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*/
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/* MCK = 48MHz, CLKDIV = 59, MCI_SPEED = 48MHz / 2 * (59+1) = 400 KHz */
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#define HSMCI_INIT_CLKDIV (59 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 48MHz, CLKDIV = 1, MCI_SPEED = 48MHz / 2 * (1+1) = 12 MHz */
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#define HSMCI_MMCXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 48MHz, CLKDIV = 0, MCI_SPEED = 48MHz / 2 * (0+1) = 24 MHz */
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#define HSMCI_SDXFR_CLKDIV (0 << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
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#define BOARD_MAIN_FREQUENCY (12000000)
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#define BOARD_CPU_FREQUENCY (BOARD_MAIN_FREQUENCY >> BOARD_CPU_SHIFT)
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#define BOARD_PBA_FREQUENCY (BOARD_MAIN_FREQUENCY >> BOARD_PBA_SHIFT)
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#define BOARD_PBB_FREQUENCY (BOARD_MAIN_FREQUENCY >> BOARD_PBB_SHIFT)
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#define BOARD_PBC_FREQUENCY (BOARD_MAIN_FREQUENCY >> BOARD_PBC_SHIFT)
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#define BOARD_PBD_FREQUENCY (BOARD_MAIN_FREQUENCY >> BOARD_PBD_SHIFT)
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/* LED definitions ******************************************************************/
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/* There are three LEDs on board the SAM4L Xplained Pro board: The EDBG
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