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warning: #include outside of 'Included Files' section

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Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
This commit is contained in:
lipengfei28
2025-01-20 20:13:07 +08:00
committed by Xiang Xiao
parent 656db16ff1
commit 4b91d76869
2 changed files with 142 additions and 217 deletions
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arch/arm/src/imxrt/imxrt117x_mpuinit.c
-216
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File diff suppressed because it is too large Load Diff
arch/arm/src/imxrt/imxrt_mpuinit.c
+142 -1
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@@ -127,7 +127,148 @@ void imxrt_mpu_initialize(void)
mpu_user_intsram(datastart, dataend - datastart);
#else
# if defined(CONFIG_ARCH_FAMILY_IMXRT117x)
# include "imxrt117x_mpuinit.c"
uint32_t regval;
uint32_t region;
mpu_reset();
region = mpu_allocregion();
DEBUGASSERT(region == 0);
/* Select the region */
putreg32(region, MPU_RNR);
/* Select the region base address */
putreg32(region | MPU_RBAR_VALID, MPU_RBAR);
/* The configure the region */
regval = MPU_RASR_ENABLE | /* Enable region */
MPU_RASR_SIZE_LOG2(32) | /* entire memory */
MPU_RASR_TEX_SO | /* Strongly ordered */
MPU_RASR_AP_NONO | /* P:None U:None */
MPU_RASR_XN; /* Execute-never to prevent instruction fetch */
putreg32(regval, MPU_RASR);
#ifdef CONFIG_IMXRT_SEMC
mpu_configure_region(IMXRT_SEMC0_BASE, 512 * 1024 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device
* Not Cacheable
* Not Bufferable
* Not Shareable
* No Subregion disable */
);
#endif
mpu_configure_region(IMXRT_FLEXSPI2_CIPHER_BASE, 512 * 1024 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device
* Not Cacheable
* Not Bufferable
* Not Shareable
* No Subregion disable */
);
mpu_configure_region(IMXRT_ITCM_BASE, 1 * 1024 * 1024 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device
* Not Cacheable
* Not Bufferable
* Not Shareable
* No Subregion disable */
);
mpu_configure_region(IMXRT_ITCM_BASE, 256 * 1024,
MPU_RASR_AP_RORO | /* P:R0 U:R0 */
MPU_RASR_TEX_NOR /* Normal
* Not Cacheable
* Not Bufferable
* Not Shareable
* No Subregion disable */
);
mpu_configure_region(IMXRT_DTCM_BASE, 256 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_NOR /* Normal
* Not Cacheable
* Not Bufferable
* Not Shareable
* No Subregion disable */
);
mpu_configure_region(IMXRT_OCRAM_M4_BASE, 1 * 1024 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_SO | /* Strongly Ordered */
RASR_C_VALUE | /* Cacheable DCACHE ? 0 : 1 */
RASR_B_VALUE /* Bufferable WB ? 0 : 1
* Not Shareable
* No Subregion disable */
);
mpu_configure_region(IMXRT_OCRAM_M4_BASE + (1 * 1024 * 1024), 512 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_SO | /* Strongly Ordered */
RASR_C_VALUE | /* Cacheable DCACHE ? 0 : 1 */
RASR_B_VALUE /* Bufferable WB ? 0 : 1
* Not Shareable
* No Subregion disable */
);
mpu_configure_region(IMXRT_FLEXSPI1_CIPHER_BASE, 16 * 1024 * 1024,
MPU_RASR_AP_RORO | /* P:R0 U:R0 */
MPU_RASR_TEX_SO | /* Strongly Ordered */
MPU_RASR_C | /* Cacheable */
MPU_RASR_B /* Bufferable
* Not Shareable
* No Subregion disable */
);
mpu_configure_region(IMXRT_AIPS1_BASE, 16 * 1024 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device
* Not Cacheable
* Not Bufferable
* Not Shareable
* No Subregion disable */
);
mpu_configure_region(IMXRT_SIM_DISP_BASE, 2 * 1024 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device
* Not Cacheable
* Not Bufferable
* Not Shareable
* No Subregion disable */
);
mpu_configure_region(IMXRT_SIM_M7_BASE, 1 * 1024 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device
* Not Cacheable
* Not Bufferable
* Not Shareable
* No Subregion disable */
);
mpu_configure_region(IMXRT_GPU2D_BASE, 2 * 1024 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device
* Not Cacheable
* Not Bufferable
* Not Shareable
* No Subregion disable */
);
mpu_configure_region(IMXRT_AIPS_M7_BASE, 1 * 1024 * 1024,
MPU_RASR_AP_RWRW | /* P:RW U:RW */
MPU_RASR_TEX_DEV /* Device
* Not Cacheable
* Not Bufferable
* Not Shareable
* No Subregion disable */
);
# else
mpu_configure_region(0xc0000000, 512 * 1024 * 1024,
MPU_RASR_TEX_DEV | /* Device