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warning: #include outside of 'Included Files' section
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
This commit is contained in:
lipengfei28
Xiang Xiao
@@ -1,216 +0,0 @@
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/****************************************************************************
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* arch/arm/src/imxrt/imxrt117x_mpuinit.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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mpu_reset();
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/* Add default region to deny access to whole address space to workaround
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* speculative prefetch. Refer to Arm errata 1013783-B for more details.
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*/
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uint32_t regval;
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uint32_t region;
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region = mpu_allocregion();
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DEBUGASSERT(region == 0);
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/* Select the region */
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putreg32(region, MPU_RNR);
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/* Select the region base address */
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putreg32(region | MPU_RBAR_VALID, MPU_RBAR);
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/* The configure the region */
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regval = MPU_RASR_ENABLE | /* Enable region */
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MPU_RASR_SIZE_LOG2(32) | /* entire memory */
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MPU_RASR_TEX_SO | /* Strongly ordered */
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MPU_RASR_AP_NONO | /* P:None U:None */
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MPU_RASR_XN; /* Execute-never to prevent instruction fetch */
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putreg32(regval, MPU_RASR);
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#ifdef CONFIG_IMXRT_SEMC
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mpu_configure_region(IMXRT_SEMC0_BASE, 512 * 1024 * 1024,
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/* Instruction access Enabled */
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device */
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/* Not Cacheable */
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/* Not Bufferable */
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/* Not Shareable */
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/* No Subregion disable */
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);
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#endif
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mpu_configure_region(IMXRT_FLEXSPI2_CIPHER_BASE, 512 * 1024 * 1024,
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/* Instruction access Enabled */
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device */
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/* Not Cacheable */
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/* Not Bufferable */
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/* Not Shareable */
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/* No Subregion disable */
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);
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mpu_configure_region(IMXRT_ITCM_BASE, 1 * 1024 * 1024 * 1024,
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/* Instruction access Enabled */
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device */
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/* Not Cacheable */
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/* Not Bufferable */
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/* Not Shareable */
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/* No Subregion disable */
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);
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mpu_configure_region(IMXRT_ITCM_BASE, 256 * 1024,
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/* Instruction access Enabled */
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MPU_RASR_AP_RORO | /* P:R0 U:R0 */
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MPU_RASR_TEX_NOR /* Normal */
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/* Not Cacheable */
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/* Not Bufferable */
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/* Not Shareable */
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/* No Subregion disable */
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);
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mpu_configure_region(IMXRT_DTCM_BASE, 256 * 1024,
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/* Instruction access Enabled */
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_NOR /* Normal */
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/* Not Cacheable */
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/* Not Bufferable */
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/* Not Shareable */
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/* No Subregion disable */
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);
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mpu_configure_region(IMXRT_OCRAM_M4_BASE, 1 * 1024 * 1024,
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/* Instruction access Enabled */
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_SO | /* Strongly Ordered */
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RASR_C_VALUE | /* Cacheable DCACHE ? 0 : 1 */
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RASR_B_VALUE /* Bufferable WB ? 0 : 1 */
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/* Not Shareable */
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/* No Subregion disable */
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);
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mpu_configure_region(IMXRT_OCRAM_M4_BASE + (1 * 1024 * 1024), 512 * 1024,
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/* Instruction access Enabled */
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_SO | /* Strongly Ordered */
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RASR_C_VALUE | /* Cacheable DCACHE ? 0 : 1 */
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RASR_B_VALUE /* Bufferable WB ? 0 : 1 */
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/* Not Shareable */
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/* No Subregion disable */
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);
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mpu_configure_region(IMXRT_FLEXSPI1_CIPHER_BASE, 16 * 1024 * 1024,
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/* Instruction access Enabled */
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MPU_RASR_AP_RORO | /* P:R0 U:R0 */
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MPU_RASR_TEX_SO | /* Strongly Ordered */
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MPU_RASR_C | /* Cacheable */
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MPU_RASR_B /* Bufferable */
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/* Not Shareable */
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/* No Subregion disable */
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);
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mpu_configure_region(IMXRT_AIPS1_BASE, 16 * 1024 * 1024,
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/* Instruction access Enabled */
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device */
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/* Not Cacheable */
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/* Not Bufferable */
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/* Not Shareable */
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/* No Subregion disable */
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);
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mpu_configure_region(IMXRT_SIM_DISP_BASE, 2 * 1024 * 1024,
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/* Instruction access Enabled */
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device */
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/* Not Cacheable */
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/* Not Bufferable */
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/* Not Shareable */
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/* No Subregion disable */
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);
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mpu_configure_region(IMXRT_SIM_M7_BASE, 1 * 1024 * 1024,
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/* Instruction access Enabled */
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device */
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/* Not Cacheable */
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/* Not Bufferable */
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/* Not Shareable */
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/* No Subregion disable */
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);
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mpu_configure_region(IMXRT_GPU2D_BASE, 2 * 1024 * 1024,
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/* Instruction access Enabled */
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device */
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/* Not Cacheable */
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/* Not Bufferable */
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/* Not Shareable */
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/* No Subregion disable */
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);
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mpu_configure_region(IMXRT_AIPS_M7_BASE, 1 * 1024 * 1024,
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/* Instruction access Enabled */
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device */
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/* Not Cacheable */
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/* Not Bufferable */
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/* Not Shareable */
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/* No Subregion disable */
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);
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@@ -127,7 +127,148 @@ void imxrt_mpu_initialize(void)
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mpu_user_intsram(datastart, dataend - datastart);
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#else
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# if defined(CONFIG_ARCH_FAMILY_IMXRT117x)
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# include "imxrt117x_mpuinit.c"
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uint32_t regval;
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uint32_t region;
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mpu_reset();
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region = mpu_allocregion();
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DEBUGASSERT(region == 0);
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/* Select the region */
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putreg32(region, MPU_RNR);
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/* Select the region base address */
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putreg32(region | MPU_RBAR_VALID, MPU_RBAR);
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/* The configure the region */
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regval = MPU_RASR_ENABLE | /* Enable region */
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MPU_RASR_SIZE_LOG2(32) | /* entire memory */
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MPU_RASR_TEX_SO | /* Strongly ordered */
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MPU_RASR_AP_NONO | /* P:None U:None */
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MPU_RASR_XN; /* Execute-never to prevent instruction fetch */
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putreg32(regval, MPU_RASR);
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#ifdef CONFIG_IMXRT_SEMC
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mpu_configure_region(IMXRT_SEMC0_BASE, 512 * 1024 * 1024,
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device
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* Not Cacheable
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* Not Bufferable
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* Not Shareable
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* No Subregion disable */
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);
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#endif
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mpu_configure_region(IMXRT_FLEXSPI2_CIPHER_BASE, 512 * 1024 * 1024,
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device
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* Not Cacheable
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* Not Bufferable
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* Not Shareable
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* No Subregion disable */
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);
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mpu_configure_region(IMXRT_ITCM_BASE, 1 * 1024 * 1024 * 1024,
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device
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* Not Cacheable
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* Not Bufferable
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* Not Shareable
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* No Subregion disable */
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);
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mpu_configure_region(IMXRT_ITCM_BASE, 256 * 1024,
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MPU_RASR_AP_RORO | /* P:R0 U:R0 */
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MPU_RASR_TEX_NOR /* Normal
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* Not Cacheable
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* Not Bufferable
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* Not Shareable
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* No Subregion disable */
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);
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mpu_configure_region(IMXRT_DTCM_BASE, 256 * 1024,
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_NOR /* Normal
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* Not Cacheable
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* Not Bufferable
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* Not Shareable
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* No Subregion disable */
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);
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mpu_configure_region(IMXRT_OCRAM_M4_BASE, 1 * 1024 * 1024,
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_SO | /* Strongly Ordered */
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RASR_C_VALUE | /* Cacheable DCACHE ? 0 : 1 */
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RASR_B_VALUE /* Bufferable WB ? 0 : 1
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* Not Shareable
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* No Subregion disable */
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);
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mpu_configure_region(IMXRT_OCRAM_M4_BASE + (1 * 1024 * 1024), 512 * 1024,
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_SO | /* Strongly Ordered */
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RASR_C_VALUE | /* Cacheable DCACHE ? 0 : 1 */
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RASR_B_VALUE /* Bufferable WB ? 0 : 1
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* Not Shareable
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* No Subregion disable */
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);
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mpu_configure_region(IMXRT_FLEXSPI1_CIPHER_BASE, 16 * 1024 * 1024,
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MPU_RASR_AP_RORO | /* P:R0 U:R0 */
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MPU_RASR_TEX_SO | /* Strongly Ordered */
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MPU_RASR_C | /* Cacheable */
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MPU_RASR_B /* Bufferable
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* Not Shareable
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* No Subregion disable */
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);
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mpu_configure_region(IMXRT_AIPS1_BASE, 16 * 1024 * 1024,
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device
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* Not Cacheable
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* Not Bufferable
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* Not Shareable
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* No Subregion disable */
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);
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mpu_configure_region(IMXRT_SIM_DISP_BASE, 2 * 1024 * 1024,
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device
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* Not Cacheable
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* Not Bufferable
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* Not Shareable
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* No Subregion disable */
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);
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mpu_configure_region(IMXRT_SIM_M7_BASE, 1 * 1024 * 1024,
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device
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* Not Cacheable
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* Not Bufferable
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* Not Shareable
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* No Subregion disable */
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);
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mpu_configure_region(IMXRT_GPU2D_BASE, 2 * 1024 * 1024,
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device
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* Not Cacheable
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* Not Bufferable
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* Not Shareable
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* No Subregion disable */
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);
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mpu_configure_region(IMXRT_AIPS_M7_BASE, 1 * 1024 * 1024,
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MPU_RASR_AP_RWRW | /* P:RW U:RW */
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MPU_RASR_TEX_DEV /* Device
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* Not Cacheable
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* Not Bufferable
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* Not Shareable
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* No Subregion disable */
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);
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# else
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mpu_configure_region(0xc0000000, 512 * 1024 * 1024,
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MPU_RASR_TEX_DEV | /* Device
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