mirror of
https://github.com/apache/nuttx.git
synced 2026-06-04 23:03:27 +08:00
SAM4E: Add support for PIO and peripheral clocks
This commit is contained in:
Gregory Nutt
@@ -6645,4 +6645,6 @@
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for the SAM4E (2014-2-21).
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* arch/arm/src/sam34/chip/sam4e_memorymap.h: Add SAM4E memory map
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(2014-2-21).
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* arch/arm/src/sam34/sam4e_gpio.h, sam4e_periphclks.h, and chip/sam4e_pio.h:
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Add PIO support for the SAM4E (2014-2-21).
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File diff suppressed because it is too large
Load Diff
@@ -51,6 +51,7 @@
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#undef GPIO_HAVE_PULLDOWN
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#undef GPIO_HAVE_PERIPHCD
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#undef GPIO_HAVE_SCHMITT
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#undef GPIO_HAVE_DELAYR
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/* Bit-encoded input to sam_configgpio() ********************************************/
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@@ -51,6 +51,7 @@
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#undef GPIO_HAVE_PULLDOWN
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#undef GPIO_HAVE_PERIPHCD
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#undef GPIO_HAVE_SCHMITT
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#undef GPIO_HAVE_DELAYR
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/* Bit-encoded input to sam_configgpio() ********************************************/
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@@ -0,0 +1,207 @@
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/************************************************************************************
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* arch/arm/src/sam34/sam4e_gpio.h
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* General Purpose Input/Output (GPIO) definitions for the SAM4E
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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||||
* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_SAM4E_GPIO_H
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#define __ARCH_ARM_SRC_SAM34_SAM4E_GPIO_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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#define GPIO_HAVE_PULLDOWN 1
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#define GPIO_HAVE_PERIPHCD 1
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#define GPIO_HAVE_SCHMITT 1
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#define GPIO_HAVE_DELAYR 1
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/* Bit-encoded input to sam_configgpio() ********************************************/
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/* 32-bit Encoding:
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*
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* MMMC CCCC III. VPPB BBBB
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*/
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/* Input/Output mode:
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*
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* MMM. .... .... .... ....
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*/
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#define GPIO_MODE_SHIFT (17) /* Bits 17-19: GPIO mode */
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#define GPIO_MODE_MASK (7 << GPIO_MODE_SHIFT)
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# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input */
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# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* Output */
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# define GPIO_PERIPHA (2 << GPIO_MODE_SHIFT) /* Controlled by periph A signal */
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# define GPIO_PERIPHB (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */
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# define GPIO_PERIPHC (4 << GPIO_MODE_SHIFT) /* Controlled by periph C signal */
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# define GPIO_PERIPHD (5 << GPIO_MODE_SHIFT) /* Controlled by periph D signal */
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/* These bits set the configuration of the pin:
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* NOTE: No definitions for parallel capture mode
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*
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* ...C CCCC .... .... ....
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*/
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#define GPIO_CFG_SHIFT (12) /* Bits 12-16: GPIO configuration bits */
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#define GPIO_CFG_MASK (31 << GPIO_CFG_SHIFT)
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# define GPIO_CFG_DEFAULT (0 << GPIO_CFG_SHIFT) /* Default, no attribute */
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# define GPIO_CFG_PULLUP (1 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-up */
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# define GPIO_CFG_PULLDOWN (2 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-down */
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# define GPIO_CFG_DEGLITCH (4 << GPIO_CFG_SHIFT) /* Bit 12: Internal glitch filter */
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# define GPIO_CFG_OPENDRAIN (8 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */
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# define GPIO_CFG_SCHMITT (16 << GPIO_CFG_SHIFT) /* Bit 13: Schmitt trigger */
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/* Additional interrupt modes:
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*
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* .... .... III. .... ....
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*/
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#define GPIO_INT_SHIFT (9) /* Bits 9-11: GPIO interrupt bits */
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#define GPIO_INT_MASK (7 << GPIO_INT_SHIFT)
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# define _GIO_INT_AIM (1 << 10) /* Bit 10: Additional Interrupt modes */
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# define _GPIO_INT_LEVEL (1 << 9) /* Bit 9: Level detection interrupt */
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# define _GPIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */
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# define _GPIO_INT_RH (1 << 8) /* Bit 9: Rising edge/High level detection interrupt */
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# define _GPIO_INT_FL (0) /* (vs. Falling edge/Low level detection interrupt) */
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# define GPIO_INT_HIGHLEVEL (_GIO_INT_AIM | _GPIO_INT_LEVEL | _GPIO_INT_RH)
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# define GPIO_INT_LOWLEVEL (_GIO_INT_AIM | _GPIO_INT_LEVEL | _GPIO_INT_FL)
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# define GPIO_INT_RISING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_RH)
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# define GPIO_INT_FALLING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_FL)
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# define GPIO_INT_BOTHEDGES (0)
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/* If the pin is an GPIO output, then this identifies the initial output value:
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*
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* .... .... .... V... ....
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*/
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#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Inital value of output */
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#define GPIO_OUTPUT_CLEAR (0)
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/* This identifies the GPIO port:
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*
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* .... .... .... .PP. ....
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*/
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#define GPIO_PORT_SHIFT (5) /* Bit 5-6: Port number */
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#define GPIO_PORT_MASK (3 << GPIO_PORT_SHIFT)
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# define GPIO_PORT_PIOA (0 << GPIO_PORT_SHIFT)
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# define GPIO_PORT_PIOB (1 << GPIO_PORT_SHIFT)
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# define GPIO_PORT_PIOC (2 << GPIO_PORT_SHIFT)
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/* This identifies the bit in the port:
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*
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* .... .... .... ...B BBBB
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*/
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#define GPIO_PIN_SHIFT (0) /* Bits 0-4: GPIO number: 0-31 */
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#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
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#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
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#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
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#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
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#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
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#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
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#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
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#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
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#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
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#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
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#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
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#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
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#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
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#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
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#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
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#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
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#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
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#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT)
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#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT)
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#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT)
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#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT)
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#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT)
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#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT)
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#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT)
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#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT)
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#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT)
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#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT)
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#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT)
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#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT)
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#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT)
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#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT)
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#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
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#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/* Must be big enough to hold the 32-bit encoding */
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typedef uint32_t gpio_pinset_t;
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#ifndef __ASSEMBLY__
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_SAM34_SAM4E_GPIO_H */
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@@ -0,0 +1,179 @@
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/************************************************************************************
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* arch/arm/src/sam34/sam4e_periphclks.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_SAM4E_PERIPHCLKS_H
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#define __ARCH_ARM_SRC_SAM34_SAM4E_PERIPHCLKS_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <arch/irq.h>
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#include "chip/sam3u_pmc.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Helper macros */
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#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
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#define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1)
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#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0)
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#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1)
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#define sam_supc_enableclk() sam_enableperiph0(SAM_PID_SUPC)
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#define sam_rstc_enableclk() sam_enableperiph0(SAM_PID_RSTC)
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#define sam_rtc_enableclk() sam_enableperiph0(SAM_PID_RTC)
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#define sam_rtt_enableclk() sam_enableperiph0(SAM_PID_RTT)
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#define sam_wdt_enableclk() sam_enableperiph0(SAM_PID_WDT)
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#define sam_pmc_enableclk() sam_enableperiph0(SAM_PID_PMC)
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#define sam_eefc_enableclk() sam_enableperiph0(SAM_PID_EEFC)
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#define sam_uart0_enableclk() sam_enableperiph0(SAM_PID_UART0)
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#define sam_smc_enableclk() sam_enableperiph0(SAM_PID_SMC)
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#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
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#define sam_piob_enableclk() sam_enableperiph0(SAM_PID_PIOB)
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#define sam_pioc_enableclk() sam_enableperiph0(SAM_PID_PIOC)
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#define sam_piod_enableclk() sam_enableperiph0(SAM_PID_PIOD)
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#define sam_pioe_enableclk() sam_enableperiph0(SAM_PID_PIOE)
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#define sam_usart0_enableclk() sam_enableperiph0(SAM_PID_USART0)
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#define sam_usart1_enableclk() sam_enableperiph0(SAM_PID_USART1)
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#define sam_hsmci_enableclk() sam_enableperiph0(SAM_PID_HSMCI)
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#define sam_twi0_enableclk() sam_enableperiph0(SAM_PID_TWI0)
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#define sam_twi1_enableclk() sam_enableperiph0(SAM_PID_TWI1)
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#define sam_spi0_enableclk() sam_enableperiph0(SAM_PID_SPI0)
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#define sam_dmac_enableclk() sam_enableperiph0(SAM_PID_DMAC)
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#define sam_tc0_enableclk() sam_enableperiph0(SAM_PID_TC0)
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#define sam_tc1_enableclk() sam_enableperiph0(SAM_PID_TC1)
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#define sam_tc2_enableclk() sam_enableperiph0(SAM_PID_TC2)
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#define sam_tc3_enableclk() sam_enableperiph0(SAM_PID_TC3)
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#define sam_tc4_enableclk() sam_enableperiph0(SAM_PID_TC4)
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#define sam_tc5_enableclk() sam_enableperiph0(SAM_PID_TC5)
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#define sam_tc6_enableclk() sam_enableperiph0(SAM_PID_TC6)
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#define sam_tc7_enableclk() sam_enableperiph0(SAM_PID_TC7)
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#define sam_tc8_enableclk() sam_enableperiph0(SAM_PID_TC8)
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#define sam_afec0_enableclk() sam_enableperiph0(SAM_PID_AFEC0)
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#define sam_afec1_enableclk() sam_enableperiph0(SAM_PID_AFEC1)
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#define sam_dacc_enableclk() sam_enableperiph1(SAM_PID_DACC)
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#define sam_acc_enableclk() sam_enableperiph1(SAM_PID_ACC)
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#define sam_arm_enableclk() sam_enableperiph1(SAM_PID_ARM)
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#define sam_udp_enableclk() sam_enableperiph1(SAM_PID_UDP)
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#define sam_pwm_enableclk() sam_enableperiph1(SAM_PID_PWM)
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#define sam_can0_enableclk() sam_enableperiph1(SAM_PID_CAN0)
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#define sam_can1_enableclk() sam_enableperiph1(SAM_PID_CAN1)
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#define sam_aes_enableclk() sam_enableperiph1(SAM_PID_AES)
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#define sam_emac_enableclk() sam_enableperiph1(SAM_PID_EMAC)
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#define sam_uart1_enableclk() sam_enableperiph1(SAM_PID_UART1)
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#define sam_supc_disableclk() sam_disableperiph0(SAM_PID_SUPC)
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#define sam_rstc_disableclk() sam_disableperiph0(SAM_PID_RSTC)
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#define sam_rtc_disableclk() sam_disableperiph0(SAM_PID_RTC)
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#define sam_rtt_disableclk() sam_disableperiph0(SAM_PID_RTT)
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#define sam_wdt_disableclk() sam_disableperiph0(SAM_PID_WDT)
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#define sam_pmc_disableclk() sam_disableperiph0(SAM_PID_PMC)
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#define sam_eefc_disableclk() sam_disableperiph0(SAM_PID_EEFC)
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#define sam_uart0_disableclk() sam_disableperiph0(SAM_PID_UART0)
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#define sam_smc_disableclk() sam_disableperiph0(SAM_PID_SMC)
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#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
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#define sam_piob_disableclk() sam_disableperiph0(SAM_PID_PIOB)
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#define sam_pioc_disableclk() sam_disableperiph0(SAM_PID_PIOC)
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#define sam_piod_disableclk() sam_disableperiph0(SAM_PID_PIOD)
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#define sam_pioe_disableclk() sam_disableperiph0(SAM_PID_PIOE)
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#define sam_usart0_disableclk() sam_disableperiph0(SAM_PID_USART0)
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#define sam_usart1_disableclk() sam_disableperiph0(SAM_PID_USART1)
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#define sam_hsmci_disableclk() sam_disableperiph0(SAM_PID_HSMCI)
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#define sam_twi0_disableclk() sam_disableperiph0(SAM_PID_TWI0)
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#define sam_twi1_disableclk() sam_disableperiph0(SAM_PID_TWI1)
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#define sam_spi0_disableclk() sam_disableperiph0(SAM_PID_SPI0)
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#define sam_dmac_disableclk() sam_disableperiph0(SAM_PID_DMAC)
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#define sam_tc0_disableclk() sam_disableperiph0(SAM_PID_TC0)
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#define sam_tc1_disableclk() sam_disableperiph0(SAM_PID_TC1)
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#define sam_tc2_disableclk() sam_disableperiph0(SAM_PID_TC2)
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#define sam_tc3_disableclk() sam_disableperiph0(SAM_PID_TC3)
|
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#define sam_tc4_disableclk() sam_disableperiph0(SAM_PID_TC4)
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#define sam_tc5_disableclk() sam_disableperiph0(SAM_PID_TC5)
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#define sam_tc6_disableclk() sam_disableperiph0(SAM_PID_TC6)
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#define sam_tc7_disableclk() sam_disableperiph0(SAM_PID_TC7)
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#define sam_tc8_disableclk() sam_disableperiph0(SAM_PID_TC8)
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#define sam_afec0_disableclk() sam_disableperiph0(SAM_PID_AFEC0)
|
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#define sam_afec1_disableclk() sam_disableperiph0(SAM_PID_AFEC1)
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||||
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||||
#define sam_dacc_disableclk() sam_disableperiph1(SAM_PID_DACC)
|
||||
#define sam_acc_disableclk() sam_disableperiph1(SAM_PID_ACC)
|
||||
#define sam_arm_disableclk() sam_disableperiph1(SAM_PID_ARM)
|
||||
#define sam_udp_disableclk() sam_disableperiph1(SAM_PID_UDP)
|
||||
#define sam_pwm_disableclk() sam_disableperiph1(SAM_PID_PWM)
|
||||
#define sam_can0_disableclk() sam_disableperiph1(SAM_PID_CAN0)
|
||||
#define sam_can1_disableclk() sam_disableperiph1(SAM_PID_CAN1)
|
||||
#define sam_aes_disableclk() sam_disableperiph1(SAM_PID_AES)
|
||||
#define sam_emac_disableclk() sam_disableperiph1(SAM_PID_EMAC)
|
||||
#define sam_uart1_disableclk() sam_disableperiph1(SAM_PID_UART1)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_SAM4E_PERIPHCLKS_H */
|
||||
@@ -51,6 +51,7 @@
|
||||
#define GPIO_HAVE_PULLDOWN 1
|
||||
#define GPIO_HAVE_PERIPHCD 1
|
||||
#define GPIO_HAVE_SCHMITT 1
|
||||
#undef GPIO_HAVE_DELAYR
|
||||
|
||||
/* Bit-encoded input to sam_configgpio() ********************************************/
|
||||
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/sam34/sam_gpio.c
|
||||
* General Purpose Input/Output (GPIO) logic for the SAM3U and SAM4S
|
||||
* General Purpose Input/Output (GPIO) logic for the SAM3U, SAM4S and SAM4E
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2010, 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -57,6 +57,8 @@
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
|
||||
defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# include "chip/sam3u_pio.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# include "chip/sam4e_pio.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
# include "chip/sam4s_pio.h"
|
||||
#else
|
||||
@@ -506,7 +508,7 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
|
||||
lldbg(" ABSR: %08x SCIFSR: %08x DIFSR: %08x IFDGSR: %08x\n",
|
||||
getreg32(base + SAM_PIO_ABSR_OFFSET), getreg32(base + SAM_PIO_SCIFSR_OFFSET),
|
||||
getreg32(base + SAM_PIO_DIFSR_OFFSET), getreg32(base + SAM_PIO_IFDGSR_OFFSET));
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
lldbg(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n",
|
||||
getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
|
||||
getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIOC_PPDSR));
|
||||
@@ -520,12 +522,17 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
|
||||
lldbg(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n",
|
||||
getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
|
||||
getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
lldbg(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
lldbg(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
|
||||
getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
|
||||
getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4E
|
||||
lldbg("SCHMITT: %08x DELAYR:%08x\n",
|
||||
getreg32(base + SAM_PIO_SCHMITT_OFFSET));
|
||||
#else
|
||||
lldbg("SCHMITT: %08x\n",
|
||||
getreg32(base + SAM_PIO_SCHMITT_OFFSET));
|
||||
#endif
|
||||
#endif
|
||||
irqrestore(flags);
|
||||
return OK;
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/sam34/sam_gpio.h
|
||||
*
|
||||
* Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2009-2011, 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -51,6 +51,8 @@
|
||||
# include "sam3u_gpio.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# include "sam3x_gpio.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# include "sam4e_gpio.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
# include "sam4l_gpio.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/sam34/sam_periphclks.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -46,6 +46,8 @@
|
||||
# include "sam3u_periphclks.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
|
||||
# include "sam3x_periphclks.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4E)
|
||||
# include "sam4e_periphclks.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
# include "sam4l_periphclks.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
|
||||
|
||||
@@ -906,6 +906,13 @@ Where <subdir> is one of the following:
|
||||
CONFIG_FS_NXFFS=n
|
||||
CONFIG_FS_ROMFS=n
|
||||
|
||||
2. This configuration targets Linux using a generic ARM EABI toolchain:
|
||||
|
||||
CONFIG_LINUX=y
|
||||
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
|
||||
|
||||
But that can easily be re-configured.
|
||||
|
||||
2. You may also want to define the following in your configuration file.
|
||||
Otherwise, you will have not feedback about what is going on:
|
||||
|
||||
|
||||
Reference in New Issue
Block a user