Add support for Olimex STM32-P107 board (contributed by Max Holtzberg)

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5018 42af7a65-404d-4744-a932-0658087f49c3
2026-05-20 04:16:35 +08:00 · 2012-08-10 17:07:02 +00:00
parent fd8dac9c40
commit 4996e1117e
29 changed files with 3730 additions and 137 deletions
@@ -3140,3 +3140,7 @@
 	  customize the behavior or NSH.
 	* arch/arm/src/stm32/chip/stm32f1*_pinmap.h: STM32 CAN TX/RX pins reversed;
 	  inconsistent conditional compilation.  Reported by Max Holtzberg.
+	* arch/arm/*/stm32:  Add support for STM32 F107 "Connectivity Line" 
+	  Ethernet (contributed by Max Holtzberg).
+	* configs/olimex-stm32-p107:  Add board support for the Olimiex STM32-P107
+	   board (contributed by Max Holtzberg).
@@ -8,7 +8,7 @@
  <tr align="center" bgcolor="#e4e4e4">
    <td>
      <h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
-      <p>Last Updated: July 25, 2012</p>
+      <p>Last Updated: August 10, 2012</p>
    </td>
  </tr>
 </table>
@@ -120,7 +120,7 @@

 <p>
  <b>Goals</b>.
-  Nuttx is a real timed embedded operating system (RTOS).
+  NuttX is a real timed embedded operating system (RTOS).
  Its goals are:
 <p>
 <center><table width="90%">
@@ -286,7 +286,7 @@
    <p>
      <li>
        Easily extensible to new processor architectures, SoC architecture, or board architectures.
-        A <a href="NuttxPortingGuide.html">Porting Guide</a> is available.
+        A <a href="NuttXPortingGuide.html">Porting Guide</a> is available.
      </li>
    </p>
 </tr>
@@ -373,7 +373,7 @@
  <td><br></td>
  <td>
    <p>
-      <li>Well documented in the NuttX <a href="NuttxUserGuide.html">User Guide</a>.</li>
+      <li>Well documented in the NuttX <a href="NuttXUserGuide.html">User Guide</a>.</li>
    </p>
 </tr>

@@ -503,7 +503,7 @@
  <td><br></td>
  <td>
    <p>
-      <li><a href="NuttxPortingGuide.html#pwrmgmt">Power management</a> sub-system.</li>
+      <li><a href="NuttXPortingGuide.html#pwrmgmt">Power management</a> sub-system.</li>
    </p>
 </tr>
 <tr>
@@ -922,7 +922,7 @@
         This configuration file contains a long list of settings that control
         what is built into NuttX and what is not.
         There are hundreds of such settings
-         (see the <a href="NuttxPortingGuide.html#apndxconfigs">NuttX Porting Guide</a>
+         (see the <a href="NuttXPortingGuide.html#apndxconfigs">NuttX Porting Guide</a>
         for a partial list that excludes platform specific settings).
         These many, many configuration options allow NuttX to be highly tuned to
         meet size requirements.
@@ -954,7 +954,7 @@
 </table>

 <p>
-  Most Nuttx-related discussion occurs on the <a href="http://tech.groups.yahoo.com/group/nuttx/" target="_top"><i>Yahoo!</i> NuttX group</a>.
+  Most NuttX-related discussion occurs on the <a href="http://tech.groups.yahoo.com/group/nuttx/" target="_top"><i>Yahoo!</i> NuttX group</a>.
  You are cordially invited to <a href="http://groups.yahoo.com/group/nuttx/join" target="_top">join</a>.
  I make a special effort to answer any questions and provide any help that I can.
 </p>
@@ -1554,13 +1554,26 @@
  <td><br></td>
  <td><hr></td>
 </tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      <b>STMicro STM32F100x</b>.
+      Chip support for these STM32 &quot;Value Line&quot; family was contributed by Mike Smith and users have reported that they have successful brought up NuttX on there proprietary boards using this logic.
+      However, there is <i>no</i> specific board support for this chip families in the NuttX source tree.
+    </p>
+</tr>
+<tr>
+  <td><br></td>
+  <td><hr></td>
+</tr>
 <tr>
  <td><br></td>
  <td>
    <p>
      <b>STMicro STM32F103x</b>.
      Support for four MCUs and three board configurations are available.
-      MCU support includes: STM32F103ZET6, STM32F103RET6, STM32F103VCT, and STM32F107VC.
+      MCU support includes: STM32F103ZET6, STM32F103RET6, and STM32F103VCT.
      Boards supported include:
    </p>
    <ol>
@@ -1623,10 +1636,13 @@
  <td><br></td>
  <td>
    <p>
-      <b>STMicro STM32F00x and STM32F107x</b>.
-      Chip support for these STM32 F1 families are present in NuttX and users have reported that they have successful brought up NuttX on there proprietary boards using this logic.
-      However, there is specific board support for these chip families.
-    </p>
+      <b>STMicro STM32F107x</b>.
+      Chip support for the STM32 F1 &quot;Connectivity Line&quot; family has been present in NuttX and users have reported that they have successful brought up NuttX on there proprietary boards using this logic.
+      Support for the <a href="https://www.olimex.com/dev/stm32-p107.html">Olimex STM32-P107</a> was contributed by Max Holtzberg and first appeared in NuttX-6.21.
+    <ul>
+      <b>STATUS:</b>
+      Configurations for the basic OS test and NSH are available and verified.
+    </ul>
   </td>
 </tr>
 <tr>
@@ -1833,7 +1849,7 @@
  <td><br></td>
  <td>
    <p>
-      <b>FreeScale Kinetics K40</b>.
+      <b>FreeScale Kinetis K40</b>.
      This port uses the Freescale Kinetis KwikStik K40.
      Refer to the <a href="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=KWIKSTIK-K40">Freescale web site</a> for further information about this board.
      The Kwikstik is used with the FreeScale Tower System (mostly just to provide a simple UART connection)
@@ -1860,7 +1876,7 @@
  <td><br></td>
  <td>
    <p>
-      <b>FreeScale Kinetics K60</b>.
+      <b>FreeScale Kinetis K60</b>.
      This port uses the Freescale Kinetis TWR-K60N512 tower system.
      Refer to the <a href="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=TWR-K60N512-KIT">Freescale web site</a> for further information about this board.
      The TWR-K60N51 includes with the FreeScale Tower System which provides (among other things) a DBP UART connection.
@@ -1890,7 +1906,7 @@
  <td>
    <p>
      <b>STMicro STM3240G-EVAL</b>.
-      This port uses the Freescale STMicro STM3240G-EVAL board featuring the STM32F407IGH6 MCU.
+      This port uses the STMicro STM3240G-EVAL board featuring the STM32F407IGH6 MCU.
      Refer to the <a href="http://www.st.com/internet/evalboard/product/252216.jsp">STMicro web site</a> for further information about this board.
    </p>
    <ul>
@@ -1927,7 +1943,7 @@
    <ul>
      <p>
        <b>STATUS:</b>
-        The basic port for the STM32F-Discovery was contributed by Mike Smith and was first released in NuttX-6.14.
+        The basic port for the STM32F4-Discovery was contributed by Mike Smith and was first released in NuttX-6.14.
      </p>
    </ul>
  </td>
@@ -1952,7 +1968,7 @@
        This includes verified support for:  SYSTICK system time,  pin and GPIO configuration, and a serial console.
      </p>
      <p>
-        Several drivers have been coped from the related LPC17xx port but require integration into the LPC43xx:  ADC, DAC, GPDMA, I2C, SPI, and SSP.
+        Several drivers have been copied from the related LPC17xx port but require integration into the LPC43xx:  ADC, DAC, GPDMA, I2C, SPI, and SSP.
        The registers for these blocks are the same in both the LPC43xx and the LPC17xx and they should integrate into the LPC43xx very easily by simply adapting the clocking and pin configuration logic.
      </p>
      <p>
@@ -1965,8 +1981,9 @@
        Some of these can be leveraged from other MCUs that appear to support the same peripheral IP:
        <ul>
          <li>
-            USB0 appears to be the same as the USB OTG peripheral for the LPC31xx.
-            It should be possible to drop in the LPC31xx driver with a small porting effort.
+            The LPC43xx USB0 peripheral appears to be the same as the USB OTG peripheral for the LPC31xx.
+            The LPC31xx USB0 device-side driver has been copied from the LPC31xx port but also integration into the LPC43xx (clocking and pin configuration).
+            It should be possible to complete poriting of this LPC31xx driver with a small porting effort.
          </li>
          <li>
            The Ethernet block looks to be based on the same IP as the STM32 Ethernet and, as a result, it should be possible to leverage the NuttX STM32 Ethernet driver with a little more effort.
@@ -2025,7 +2042,7 @@
  <td><br></td>
  <td>
    <p>
-      <b>Micropendous 3 AT9USB64x</b> and <b>AT9USB6128x</b>.
+      <b>Micropendous 3 AT90USB64x</b> and <b>AT90USB6128x</b>.
      This port of NuttX to the Opendous Micropendous 3 board. The Micropendous3 is
      may be populated with an AT90USB646, 647, 1286, or 1287.  I have only the AT90USB647
      version for testing.  This version have very limited memory resources: 64K of
@@ -2049,7 +2066,7 @@
  <td><br></td>
  <td>
    <p>
-      <b>PJRC Teensy++ 2.0 AT9USB1286</b>.
+      <b>PJRC Teensy++ 2.0 AT90USB1286</b>.
      This is a port of NuttX to the PJRC Teensy++ 2.0 board.
      This board was developed by <a href="http://pjrc.com/teensy/">PJRC</a>.
      The Teensy++ 2.0 is based on an Atmel AT90USB1286 MCU.
@@ -2105,7 +2122,7 @@
      <p>
        <b>Development Environments:</b>
        1) Linux with native Linux GNU toolchain, 2) Cygwin with Cygwin GNU toolchain, or 3) Cygwin with Windows native toolchain. 
-        All testing, however, has been performed using the Nuttx DIY toolchain for Linux  or Cygwin is provided by the NuttX
+        All testing, however, has been performed using the NuttX DIY toolchain for Linux  or Cygwin is provided by the NuttX
        <a href="http://sourceforge.net/projects/nuttx/files/buildroot/">buildroot</a> package.
        As a result, that toolchain is recommended.
      </p>
@@ -2399,7 +2416,7 @@
      <p>
       <b>STATUS:</b>
         Two verified configurations are available:
-         (1) The basic OS test configuration that verfies the correctness port of Nuttx, and (2) an extensive <a href="NuttShell.html">NuttShell (NSH)</a> configuration.
+         (1) The basic OS test configuration that verfies the correctness port of NuttX, and (2) an extensive <a href="NuttShell.html">NuttShell (NSH)</a> configuration.
         The NSH configuration includes:
         (1) Full network support,
         (2) Verified SPI driver,
@@ -2447,7 +2464,7 @@
    <p>
      <b>SH-1 SH7032</b>.
      This port uses the Hitachi SH-1 Low-Cost Evaluation Board (SH1_LCEVB1), US7032EVB,
-      with a GNU arm-elf toolchain* under Linux or Cygwin.
+      with a GNU ELF toolchain* under Linux or Cygwin.
    </p>
    <ul>
      <p>
@@ -2813,9 +2830,9 @@ avr, m68k, m68hc11, m68hc12, m9s12, blackfin, m32c, h8, and SuperH ports.</block
    </p>
    <blockquote>
      <p>
-         &quot;I've installed ZDS-II 5.1.1 (IDE for ez80-based boards) on wine (windows emulator for UNIX) and to my surprise, not many changes were needed to make SVN snapshot of Nuttx buildable...
+         &quot;I've installed ZDS-II 5.1.1 (IDE for ez80-based boards) on wine (windows emulator for UNIX) and to my surprise, not many changes were needed to make SVN snapshot of NuttX buildable...
         I've tried nsh profile and build process completed successfully.
-         One remark is necessary: Nuttx makefiles for ez80 are referencing <code>cygpath</code> utility.
+         One remark is necessary: NuttX makefiles for ez80 are referencing <code>cygpath</code> utility.
         Wine provides similar thing called <code>winepath</code> which is compatible and offers compatible syntax.
         To use that, <code>winepath</code> (which itself is a shell script) has to be copied as <code>cygpath</code> somewhere in <code>$PATH</code>, and edited as in following patch:
       </p>
@@ -3210,11 +3227,11 @@ buildroot-1.10 2011-05-06 &lt;gnutt@nuttx.org&gt;
 </tr>
 <tr>
  <td valign="top" width="22"><img height="20" width="20" src="favicon.ico"></td>
-  <td><a href="NuttxUserGuide.html">User Guide</a></td>
+  <td><a href="NuttXUserGuide.html">User Guide</a></td>
 </tr>
 <tr>
  <td valign="top" width="22"><img height="20" width="20" src="favicon.ico"></td>
-  <td><a href="NuttxPortingGuide.html">Porting Guide</a></td>
+  <td><a href="NuttXPortingGuide.html">Porting Guide</a></td>
 </tr>
 <tr>
  <td valign="top" width="22"><img height="20" width="20" src="favicon.ico"></td>
@@ -167,7 +167,13 @@
 #  define STM32_IRQ_EXTI1510    (56) /* 40: EXTI Line[15:10] interrupts */
 #  define STM32_IRQ_RTCALRM     (57) /* 41: RTC alarm through EXTI line interrupt */
 #  define STM32_IRQ_OTGFSWKUP   (58) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
-                                     /* 43-49: Reserved */
+#  define STM32_IRQ_RESERVED0   (59) /* 43: Reserved 0 */
+#  define STM32_IRQ_RESERVED1   (60) /* 44: Reserved 1 */
+#  define STM32_IRQ_RESERVED2   (61) /* 45: Reserved 2 */
+#  define STM32_IRQ_RESERVED3   (62) /* 46: Reserved 3 */
+#  define STM32_IRQ_RESERVED4   (63) /* 47: Reserved 4 */
+#  define STM32_IRQ_RESERVED5   (64) /* 48: Reserved 5 */
+#  define STM32_IRQ_RESERVED6   (65) /* 49: Reserved 6 */
 #  define STM32_IRQ_TIM5        (66) /* 50: TIM5 global interrupt */
 #  define STM32_IRQ_SPI3        (67) /* 51: SPI3 global interrupt */
 #  define STM32_IRQ_UART4       (68) /* 52: UART4 global interrupt */
@@ -89,43 +89,49 @@
 #define GPIO_DAC_OUT2           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
 #endif

-#if 0 /* Needs further investigation */
+/* Section 29.3 in the stm32 datasheet (Doc ID 13902 Rev 14) */
+
 #define GPIO_ETH_MDC            (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN1)
 #define GPIO_ETH_MDIO           (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
-#define GPIO_ETH_MIICOL         (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
-#define GPIO_ETH_MIICRSWKUP     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
-#define GPIO_ETH_MIIRXCLK       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
-
+#define GPIO_ETH_MIICOL         (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ETH_MIICRSWKUP     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ETH_MIIRXCLK       (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
 #if defined(CONFIG_STM32_ETH_REMAP)
-#  define GPIO_ETH_MIIRXD0      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
-#  define GPIO_ETH_MIIRXD1      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
-#  define GPIO_ETH_MIIRXD2      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN11)
-#  define GPIO_ETH_MIIRXD3      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
-#  define GPIO_ETH_MIIRXDV      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
+#  define GPIO_ETH_MIIRXD0      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
+#  define GPIO_ETH_MIIRXD1      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
+#  define GPIO_ETH_MIIRXD2      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN11)
+#  define GPIO_ETH_MIIRXD3      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
+#  define GPIO_ETH_MIIRXDV      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
 #else
-#  define GPIO_ETH_MIIRXD0      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
-#  define GPIO_ETH_MIIRXD1      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
-#  define GPIO_ETH_MIIRXD2      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
-#  define GPIO_ETH_MIIRXD3      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
-#  define GPIO_ETH_MIIRXDV      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
+#  define GPIO_ETH_MIIRXD0      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
+#  define GPIO_ETH_MIIRXD1      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
+#  define GPIO_ETH_MIIRXD2      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
+#  define GPIO_ETH_MIIRXD3      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
+#  define GPIO_ETH_MIIRXDV      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
 #endif

-#define GPIO_ETH_MIIRXER        (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
-#define GPIO_ETH_MIITXCLK       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_ETH_MIIRXER        (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_ETH_MIITXCLK       (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN3)
 #define GPIO_ETH_MIITXD0        (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
 #define GPIO_ETH_MIITXD1        (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
 #define GPIO_ETH_MIITXD2        (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN2)
 #define GPIO_ETH_MIITXD3        (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
 #define GPIO_ETH_MIITXEN        (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
-#define GPIO_ETH_PPSOUT         (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
-#define GPIO_ETH_RMIICRSDV      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
-#define GPIO_ETH_RMIIREFCLK     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
-#define GPIO_ETH_RMIIRXD0       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
-#define GPIO_ETH_RMIIRXD1       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
-#define GPIO_ETH_RMIITXD0       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
-#define GPIO_ETH_RMIITXD1       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
-#define GPIO_ETH_RMIITXEN       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_ETH_PPS_OUT        (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+
+#define GPIO_ETH_RMII_REF_CLK   (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
+#if defined(CONFIG_STM32_ETH_REMAP)
+#  define GPIO_ETH_RMII_CRS_DV    (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
+#  define GPIO_ETH_RMII_RXD0      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
+#  define GPIO_ETH_RMII_RXD1      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
+#else
+#  define GPIO_ETH_RMII_CRS_DV    (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
+#  define GPIO_ETH_RMII_RXD0      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
+#  define GPIO_ETH_RMII_RXD1      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
 #endif
+#define GPIO_ETH_RMII_TXD0      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_ETH_RMII_TXD1      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_ETH_RMII_TX_EN     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)

 #if defined(CONFIG_STM32_I2C1_REMAP)
 #  define GPIO_I2C1_SCL         (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
@@ -148,9 +154,7 @@
 #define GPIO_I2S3_SD            (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
 #define GPIO_I2S3_WS            (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)

-#if 0 /* Needs further investigation */
 #define GPIO_MCO                (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
-#endif

 #if 0 /* Needs further investigation */
 #define GPIO_OTG_FSDM           (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
@@ -271,6 +271,9 @@
 #  define AFIO_MAPR_SWJ              (1 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 001: Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
 #  define AFIO_MAPR_SWDP             (2 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 010: JTAG-DP Disabled and SW-DP Enabled */
 #  define AFIO_MAPR_DISAB            (4 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 100: JTAG-DP Disabled and SW-DP Disabled */
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define AFIO_MAPR_MII_RMII_SEL     (1 << 23) /* MII or RMII selection */
+#endif
 #define AFIO_MAPR_PD01_REMAP         (1 << 15) /* Bit 15 : Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
 #define AFIO_MAPR_CAN_REMAP_SHIFT    (13)      /* Bits 14-13: CAN Alternate function remapping */
 #define AFIO_MAPR_CAN_REMAP_MASK     (3 << AFIO_MAPR_CAN_REMAP_SHIFT)
@@ -278,7 +281,7 @@
 #  define AFIO_MAPR_PB89             (2 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 10: CANRX mapped to PB8, CANTX mapped to PB9 */
 #  define AFIO_MAPR_PD01             (3 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 11: CANRX mapped to PD0, CANTX mapped to PD1 */
 #define AFIO_MAPR_TIM4_REMAP         (1 << 12) /* Bit 12: TIM4 remapping */
-#define AFIO_MAPR_TIM3_REMAP_SHIFT  (10)      /* Bits 11-10: TIM3 remapping */
+#define AFIO_MAPR_TIM3_REMAP_SHIFT   (10)      /* Bits 11-10: TIM3 remapping */
 #define AFIO_MAPR_TIM3_REMAP_MASK    (3 << AFIO_MAPR_TIM3_REMAP_SHIFT)
 #  define AFIO_MAPR_TIM3_NOREMAP     (0 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
 #  define AFIO_MAPR_TIM3_PARTREMAP   (2 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -52,7 +52,10 @@
 #define STM32_RCC_APB1ENR_OFFSET    0x001c  /* APB1 Peripheral Clock enable register */
 #define STM32_RCC_BDCR_OFFSET       0x0020  /* Backup domain control register */
 #define STM32_RCC_CSR_OFFSET        0x0024  /* Control/status register */
-#ifdef CONFIG_STM32_VALUELINE
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define STM32_RCC_AHBRSTR_OFFSET  0x0028  /* AHB Reset register */
+#endif
+#if defined(CONFIG_STM32_VALUELINE) || defined(CONFIG_STM32_CONNECTIVITYLINE)
 #  define STM32_RCC_CFGR2_OFFSET    0x002c  /* Clock configuration register 2 */
 #endif

@@ -68,7 +71,10 @@
 #define STM32_RCC_APB1ENR           (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
 #define STM32_RCC_BDCR              (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
 #define STM32_RCC_CSR               (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
-#ifdef CONFIG_STM32_VALUELINE
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define STM32_RCC_AHBRSTR         (STM32_RCC_BASE+STM32_RCC_AHBRSTR_OFFSET)
+#endif
+#if defined(CONFIG_STM32_VALUELINE) || defined(CONFIG_STM32_CONNECTIVITYLINE)
 #  define STM32_RCC_CFGR2           (STM32_RCC_BASE+STM32_RCC_CFGR2_OFFSET)
 #endif

@@ -88,6 +94,12 @@
 #define RCC_CR_CSSON                (1 << 19) /* Bit 19: Clock Security System enable */
 #define RCC_CR_PLLON                (1 << 24) /* Bit 24: PLL enable */
 #define RCC_CR_PLLRDY               (1 << 25) /* Bit 25: PLL clock ready flag */
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define RCC_CR_PLL2ON             (1 << 26) /* Bit 26: PLL2 enable */
+#  define RCC_CR_PLL2RDY            (1 << 27) /* Bit 27: PLL2 clock ready flag */
+#  define RCC_CR_PLL3ON             (1 << 28) /* Bit 28: PLL3 enable */
+#  define RCC_CR_PLL3RDY            (1 << 29) /* Bit 29: PLL3 ready flag */
+#endif

 /* Clock configuration register */

@@ -153,12 +165,16 @@
 #  define RCC_CFGR_PLLMUL_CLKx16    (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
 #define RCC_CFGR_USBPRE             (1 << 22) /* Bit 22: USB prescaler */
 #define RCC_CFGR_MCO_SHIFT          (24)      /* Bits 26-24: Microcontroller Clock Output */
-#define RCC_CFGR_MCO_MASK           (7 << RCC_CFGR_MCO_SHIFT)
-#  define RCC_CFGR_NOCLK            (0 << RCC_CFGR_MCO_SHIFT) /* 0xx: No clock */
-#  define RCC_CFGR_SYSCLK           (4 << RCC_CFGR_MCO_SHIFT) /* 100: System clock selected */
-#  define RCC_CFGR_INTCLK           (5 << RCC_CFGR_MCO_SHIFT) /* 101: Internal 8 MHz RC oscillator clock selected */
-#  define RCC_CFGR_EXTCLK           (6 << RCC_CFGR_MCO_SHIFT) /* 110: External 1-25 MHz oscillator clock selected */
-#  define RCC_CFGR_PLLCLKd2         (7 << RCC_CFGR_MCO_SHIFT) /* 111: PLL clock divided by 2 selected */
+#define RCC_CFGR_MCO_MASK           (0x0f << RCC_CFGR_MCO_SHIFT)
+#  define RCC_CFGR_NOCLK            (0 << RCC_CFGR_MCO_SHIFT)  /* 0xx: No clock */
+#  define RCC_CFGR_SYSCLK           (4 << RCC_CFGR_MCO_SHIFT)  /* 100: System clock selected */
+#  define RCC_CFGR_INTCLK           (5 << RCC_CFGR_MCO_SHIFT)  /* 101: Internal 8 MHz RC oscillator clock selected */
+#  define RCC_CFGR_EXTCLK           (6 << RCC_CFGR_MCO_SHIFT)  /* 110: External 1-25 MHz oscillator clock selected */
+#  define RCC_CFGR_PLLCLKd2         (7 << RCC_CFGR_MCO_SHIFT)  /* 111: PLL clock divided by 2 selected */
+#  define RCC_CFGR_PLL2CLK          (8 << RCC_CFGR_MCO_SHIFT)  /* 1000: PLL2 clock selected */
+#  define RCC_CFGR_PLL3CLKd2        (9 << RCC_CFGR_MCO_SHIFT)  /* 1001: PLL3 clock devided by 2 selected */
+#  define RCC_CFGR_XT1              (10 << RCC_CFGR_MCO_SHIFT) /* 1010: external 3-25 MHz oscillator clock selected (for Ethernet) */
+#  define RCC_CFGR_PLL3CLK          (11 << RCC_CFGR_MCO_SHIFT) /* 1011: PLL3 clock selected (for Ethernet) */

 /* Clock interrupt register */

@@ -231,6 +247,18 @@
 #define RCC_AHBENR_CRCEN            (1 << 6)  /* Bit 6: CRC clock enable */
 #define RCC_AHBENR_FSMCEN           (1 << 8)  /* Bit 8: FSMC clock enable */
 #define RCC_AHBENR_SDIOEN           (1 << 10) /* Bit 10: SDIO clock enable */
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define RCC_AHBENR_ETHMACEN       (1 << 14) /* Bit 14: Ethernet MAC clock enable */
+#  define RCC_AHBENR_ETHMACTXEN     (1 << 15) /* Bit 15: Ethernet MAC TX clock enable */
+#  define RCC_AHBENR_ETHMACRXEN     (1 << 16) /* Bit 16: Ethernet MAC RX clock enable */
+#endif
+
+/* AHB peripheral clock reset register (RCC_AHBRSTR) */
+
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define RCC_AHBRSTR_OTGFSRST      (1 << 12) /* USB OTG FS reset */
+#  define RCC_AHBRSTR_ETHMACRST     (1 << 14) /* Ethernet MAC reset */
+#endif

 /* APB2 Peripheral Clock enable register */

@@ -301,26 +329,86 @@
 #define RCC_CSR_WWDGRSTF            (1 << 30) /* Bit 30: Window watchdog reset flag */
 #define RCC_CSR_LPWRRSTF            (1 << 31) /* Bit 31: Low-Power reset flag */

-#ifdef CONFIG_STM32_VALUELINE
+#if defined(CONFIG_STM32_VALUELINE) || defined(CONFIG_STM32_CONNECTIVITYLINE)

-/* Clock configuration register 2 */
+/* Clock configuration register 2 (For connectivity line only) */

-#  define RCC_CFGR2_PREDIV1d1       0  /* HSE input not divided */
-#  define RCC_CFGR2_PREDIV1d2       1  /* HSE input divided by 2 */
-#  define RCC_CFGR2_PREDIV1d3       2  /* HSE input divided by 3 */
-#  define RCC_CFGR2_PREDIV1d4       3  /* HSE input divided by 4 */
-#  define RCC_CFGR2_PREDIV1d5       4  /* HSE input divided by 5 */
-#  define RCC_CFGR2_PREDIV1d6       5  /* HSE input divided by 6 */
-#  define RCC_CFGR2_PREDIV1d7       6  /* HSE input divided by 7 */
-#  define RCC_CFGR2_PREDIV1d8       7  /* HSE input divided by 8 */
-#  define RCC_CFGR2_PREDIV1d9       8  /* HSE input divided by 9 */
-#  define RCC_CFGR2_PREDIV1d10      9  /* HSE input divided by 10 */
-#  define RCC_CFGR2_PREDIV1d11      10 /* HSE input divided by 11 */
-#  define RCC_CFGR2_PREDIV1d12      11 /* HSE input divided by 12 */
-#  define RCC_CFGR2_PREDIV1d13      12 /* HSE input divided by 13 */
-#  define RCC_CFGR2_PREDIV1d14      13 /* HSE input divided by 14 */
-#  define RCC_CFGR2_PREDIV1d15      14 /* HSE input divided by 15 */
-#  define RCC_CFGR2_PREDIV1d16      15 /* HSE input divided by 16 */
+#define RCC_CFGR2_PREDIV1_SHIFT     (0)
+#define RCC_CFGR2_PREDIV1_MASK      (0x0f << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d1       (0 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d2       (1 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d3       (2 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d4       (3 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d5       (4 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d6       (5 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d7       (6 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d8       (7 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d9       (8 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d10      (9 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d11      (10 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d12      (11 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d13      (12 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d14      (13 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d15      (14 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d16      (15 << RCC_CFGR2_PREDIV1_SHIFT)
+
+#define RCC_CFGR2_PREDIV2_SHIFT     (4)
+#define RCC_CFGR2_PREDIV2_MASK      (0x0f << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d1       (0 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d2       (1 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d3       (2 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d4       (3 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d5       (4 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d6       (5 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d7       (6 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d8       (7 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d9       (8 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d10      (9 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d11      (10 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d12      (11 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d13      (12 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d14      (13 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d15      (14 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d16      (15 << RCC_CFGR2_PREDIV2_SHIFT)
+
+#define RCC_CFGR2_PLL2MUL_SHIFT     (8)
+#define RCC_CFGR2_PLL2MUL_MASK      (0x0f << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx8       (6 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx9       (7 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx10      (8 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx11      (9 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx12      (10 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx13      (11 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx14      (12 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx16      (14 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx20      (15 << RCC_CFGR2_PLL2MUL_SHIFT)
+
+#define RCC_CFGR2_PLL3MUL_SHIFT     (12)
+#define RCC_CFGR2_PLL3MUL_MASK      (0x0f << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx8       (6 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx9       (7 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx10      (8 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx11      (9 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx12      (10 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx13      (11 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx14      (12 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx16      (14 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx20      (15 << RCC_CFGR2_PLL3MUL_SHIFT)
+
+#define RCC_CFGR2_PREDIV1SRC_SHIFT  (16)
+#define RCC_CFGR2_PREDIV1SRC_MASK   (0x01 << RCC_CFGR2_PREDIV1SRC_SHIFT)
+#  define RCC_CFGR2_PREDIV1SRC_HSE  (0 << RCC_CFGR2_PREDIV1SRC_SHIFT)
+#  define RCC_CFGR2_PREDIV1SRC_PLL2 (1 << RCC_CFGR2_PREDIV1SRC_SHIFT)
+
+#define RCC_CFGR2_I2S2SRC_SHIFT     (17)
+#define RCC_CFGR2_I2S2SRC_MASK      (0x01 << RCC_CFGR2_I2S2SRC_SHIFT)
+#  define RCC_CFGR2_I2S2SRC_SYSCLK  (0 << RCC_CFGR2_I2S2SRC_SHIFT)
+#  define RCC_CFGR2_I2S2SRC_PLL3    (1 << RCC_CFGR2_I2S2SRC_SHIFT)
+
+#define RCC_CFGR2_I2S3SRC_SHIFT     (17)
+#define RCC_CFGR2_I2S3SRC_MASK      (0x01 << RCC_CFGR2_I2S3SRC_SHIFT)
+#  define RCC_CFGR2_I2S3SRC_SYSCLK  (0 << RCC_CFGR2_I2S3SRC_SHIFT)
+#  define RCC_CFGR2_I2S3SRC_PLL3    (1 << RCC_CFGR2_I2S3SRC_SHIFT)

 #endif

@@ -89,7 +89,8 @@ VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2)         /* Vector 16+12: DMA1 Channel 2
 VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3)         /* Vector 16+13: DMA1 Channel 3 global interrupt */
 VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4)         /* Vector 16+14: DMA1 Channel 4 global interrupt */
 VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5)         /* Vector 16+15: DMA1 Channel 5 global interrupt */
-VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6)         /* Vector 16+16: DMA1 Channel 7 global interrupt */
+VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6)         /* Vector 16+16: DMA1 Channel 6 global interrupt */
+VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7)         /* Vector 16+17: DMA1 Channel 7 global interrupt */
 VECTOR(stm32_adc12, STM32_IRQ_ADC12)             /* Vector 16+18: ADC1 and ADC2 global interrupt */
 VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX)           /* Vector 16+19: CAN1 TX interrupts */
 VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0)         /* Vector 16+20: CAN1 RX0 interrupts */
@@ -115,6 +116,13 @@ VECTOR(stm32_usart3, STM32_IRQ_USART3)           /* Vector 16+39: USART3 global
 VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510)       /* Vector 16+40: EXTI Line[15:10] interrupts */
 VECTOR(stm32_rtcalr, STM32_IRQ_RTCALRM)          /* Vector 16+41: RTC alarm through EXTI line interrupt */
 VECTOR(stm32_otgfswkup, STM32_IRQ_OTGFSWKUP)     /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */
+UNUSED(STM32_IRQ_RESERVED0)                      /* Vector 16+43: Reserved 0 */
+UNUSED(STM32_IRQ_RESERVED1)                      /* Vector 16+44: Reserved 1 */
+UNUSED(STM32_IRQ_RESERVED2)                      /* Vector 16+55: Reserved 2 */
+UNUSED(STM32_IRQ_RESERVED3)                      /* Vector 16+46: Reserved 3 */
+UNUSED(STM32_IRQ_RESERVED4)                      /* Vector 16+47: Reserved 4 */
+UNUSED(STM32_IRQ_RESERVED5)                      /* Vector 16+48: Reserved 5 */
+UNUSED(STM32_IRQ_RESERVED6)                      /* Vector 16+49: Reserved 6 */
 VECTOR(stm32_tim5, STM32_IRQ_TIM5)               /* Vector 16+50: TIM5 global interrupt */
 VECTOR(stm32_spi3, STM32_IRQ_SPI3 )              /* Vector 16+51: SPI3 global interrupt */
 VECTOR(stm32_uart4 , STM32_IRQ_UART4)            /* Vector 16+52: UART4 global interrupt */
@@ -85,7 +85,7 @@
 #  error "Logic to support multiple Ethernet interfaces is incomplete"
 #endif

-#ifndef CONFIG_STM32_SYSCFG
+#if !defined(CONFIG_STM32_SYSCFG) && !defined(CONFIG_STM32_CONNECTIVITYLINE)
 #  error "CONFIG_STM32_SYSCFG must be defined in the NuttX configuration"
 #endif

@@ -2657,6 +2657,13 @@ static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv)

 #elif defined(CONFIG_STM32_RMII)

+  /* Setup MCO pin for alternative usage */
+
+#if defined(CONFIG_STM32_RMII_MCO)
+  stm32_configgpio(GPIO_MCO);
+  stm32_mcoconfig(BOARD_CFGR_MCO_SOURCE);
+#endif
+
  /* Select the RMII interface */

  stm32_selectrmii();
@@ -2673,7 +2680,7 @@ static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv)
  stm32_configgpio(GPIO_ETH_RMII_RXD1);
  stm32_configgpio(GPIO_ETH_RMII_TXD0);
  stm32_configgpio(GPIO_ETH_RMII_TXD1);
-  stm32_configgpio(GPIO_ETH_RMII_TX_CLK);
+  /* stm32_configgpio(GPIO_ETH_RMII_TX_CLK); not needed? */
  stm32_configgpio(GPIO_ETH_RMII_TX_EN);

 #endif
@@ -2704,14 +2711,25 @@ static void stm32_ethreset(FAR struct stm32_ethmac_s *priv)
 {
  uint32_t regval;

-  /* Reset the Ethernet on the AHB1 bus */
+  /* Reset the Ethernet on the AHB bus (F1 Connectivity Line) or AHB1 bus (F2
+   * and F4)
+   */

+#if defined(CONFIG_STM32_CONNECTIVITYLINE)
+  regval  = stm32_getreg(STM32_RCC_AHBRSTR);
+  regval |= RCC_AHBRSTR_ETHMACRST;
+  stm32_putreg(regval, STM32_RCC_AHBRSTR);
+
+  regval &= ~RCC_AHBRSTR_ETHMACRST;
+  stm32_putreg(regval, STM32_RCC_AHBRSTR);
+#else
  regval  = stm32_getreg(STM32_RCC_AHB1RSTR);
  regval |= RCC_AHB1RSTR_ETHMACRST;
  stm32_putreg(regval, STM32_RCC_AHB1RSTR);

  regval &= ~RCC_AHB1RSTR_ETHMACRST;
  stm32_putreg(regval, STM32_RCC_AHB1RSTR);
+#endif

  /* Perform a software reset by setting the SR bit in the DMABMR register.
   * This Resets all MAC subsystem internal registers and logic.  After this
@@ -116,6 +116,39 @@ static inline void stm32_mco1config(uint32_t source, uint32_t div)
 }
 #endif

+/************************************************************************************
+ * Name: stm32_mcoconfig
+ *
+ * Description:
+ *   Selects the clock source to output on MC pin (PA8) for stm32f10xxx.
+ *   PA8 should be configured in alternate function mode.
+ *
+ * Input Parameters:
+ *   source - One of the definitions for the RCC_CFGR_MCO definitions from
+ *     chip/stm32f10xxx_rcc.h {RCC_CFGR_SYSCLK, RCC_CFGR_INTCLK, RCC_CFGR_EXTCLK,
+ *     RCC_CFGR_PLLCLKd2, RCC_CFGR_PLL2CLK, RCC_CFGR_PLL3CLKd2, RCC_CFGR_XT1,
+ *     RCC_CFGR_PLL3CLK}
+ *
+ * Returned Value:
+ *   None
+ *
+ ************************************************************************************/
+
+#if defined(CONFIG_STM32_CONNECTIVITYLINE)
+static inline void stm32_mcoconfig(uint32_t source)
+{
+  uint32_t regval;
+
+  /* Set MCO source */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~(RCC_CFGR_MCO_MASK);
+  regval |= (source & RCC_CFGR_MCO_MASK);
+  putreg32(regval, STM32_RCC_CFGR);
+}
+#endif
+
+
 /************************************************************************************
 * Name: stm32_mco2config
 *
@@ -1615,7 +1615,7 @@ static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
      /* SD normal operation clocking (narrow 1-bit mode) */

      case CLOCK_SD_TRANSFER_1BIT:
-        clckr = (SDIO_CLCKR_SDXFR | SDIO_CLKCR_CLKEN)
+        clckr = (SDIO_CLCKR_SDXFR | SDIO_CLKCR_CLKEN);
        break;
    }

@@ -143,6 +143,9 @@ stm32_vectors:
 #undef VECTOR
 #define VECTOR(l,i) .word l

+#undef UNUSED
+#define UNUSED(i) .word stm32_reserved
+
 #if defined(CONFIG_STM32_STM32F10XX)
 #  include "chip/chip/stm32f10xxx_vectors.h"
 #elif defined(CONFIG_STM32_STM32F20XX)
@@ -176,6 +179,9 @@ handlers:
 #undef VECTOR
 #define VECTOR(l,i) HANDLER l, i

+#undef UNUSED
+#define UNUSED(i)
+
 #if defined(CONFIG_STM32_STM32F10XX)
 #  include "chip/chip/stm32f10xxx_vectors.h"
 #elif defined(CONFIG_STM32_STM32F20XX)
@@ -144,6 +144,12 @@ static inline void rcc_enableahb(void)
  regval |=  RCC_AHBENR_SDIOEN;
 #endif

+#if defined(CONFIG_STM32_ETHMAC) && defined(CONFIG_STM32_CONNECTIVITYLINE)
+  /* Ethernet clock enable */
+
+  regval |= (RCC_AHBENR_ETHMACEN | RCC_AHBENR_ETHMACTXEN | RCC_AHBENR_ETHMACRXEN);
+#endif
+
  putreg32(regval, STM32_RCC_AHBENR);   /* Enable peripherals */
 }

@@ -1603,6 +1603,12 @@ configs/olimex-lpc2378
  Linux or Cygwin.  STATUS: ostest and NSH configurations available.
  This port for the NXP LPC2378 was contributed by Rommel Marcelo.

+configs/olimex-stm32-p107
+  This port uses the Olimex STM32-P107 board (STM32F107VC) and a GNU arm-elf
+  toolchain* under Linux or Cygwin. See the https://www.olimex.com/dev/stm32-p107.html
+  for further information.  Contributed by Max Holtzberg.  STATUS: Configurations
+  for the basic OS test and NSH are available and verified.
+
 configs/olimex-strp711
  This port uses the Olimex STR-P711 board and a GNU arm-elf toolchain* under
  Linux or Cygwin. See the http://www.olimex.com/dev/str-p711.html" for
@@ -12,11 +12,17 @@ Contents
  - Development Environment
  - GNU Toolchain Options
  - IDEs
+  - Code Red IDE/Tools
+    Booting the LPCLink
+    Using GDB
+    Troubleshooting
+    Command Line Flash Programming
+    Executing from SPIFI
+    USB DFU Booting
  - NuttX buildroot Toolchain
  - Serial Console
  - FPU
  - LPC4330-Xplorer Configuration Options
-  - USB Host Configuration
  - Configurations

 LPC4330-Xplorer board
@@ -263,8 +269,8 @@ IDEs
  Startup files will probably cause you some headaches.  The NuttX startup file
  is arch/arm/src/common/up_vectors.S.

-Code Red IDE
-^^^^^^^^^^^^
+Code Red IDE/Tools
+^^^^^^^^^^^^^^^^^^

  Booting the LPCLink
  -------------------
@@ -418,6 +424,39 @@ Code Red IDE
  found in the configs/lpc4330-xplorer/scripts directory can do that with
  a single command line command.

+  Executing from SPIFI
+  --------------------
+
+  By default, the configurations here assume that you are executing directly
+  from SRAM.
+
+    CONFIG_BOOT_SRAM=y             : Executing in SRAM
+    CONFIG_LPC32_CODEREDW=y        : Code Red under Windows
+
+  To execute from SPIFI, you would need to set:
+
+    CONFIG_BOOT_SPIFI=y            : Executing from SPIFI
+    CONFIG_DRAM_SIZE=(128*1024)    : SRAM Bank0 size
+    CONFIG_DRAM_START=0x10000000   : SRAM Bank0 base address
+    CONFIG_SPIFI_OFFSET=(512*1024) : SPIFI file system offset
+
+  To boot the LPC4330-Xplorer from SPIFI the DIP switches should be 1-OFF,
+  2-ON, 3-ON, 4-ON (LOW LOW LOW HIGH in Table 19, MSB to LSB).
+
+  If the code in flash hard faults after reset and crt_emu_lpc18_43_nxp
+  can't reset the MCU, an alternative is to temporarily change switch 1
+  to  ON and press the reset button so it enters UART boot mode. Then
+  change it back to OFF and reset to boot again from flash.
+
+  # Use -wire to specify the debug probe in use:
+  #   (empty)       Red Probe+
+  #   -wire=winusb  LPC-Link on Windows XP
+  #   -wire=hid     LPC-Link on Windows Vista/ Windows 7
+  # Add -g -4 for verbose output
+
+  crt_emu_lpc18_43_nxp -wire=hid -pLPC4330 -load-base=0x14000000 
+    -flash-load-exec=nuttx.bin -flash-driver=LPC1850A_4350A_SPIFI.cfx
+
  USB DFU Booting
  ---------------

@@ -804,41 +843,6 @@ LPC4330-Xplorer Configuration Options
      application can guarantee that all end-user I/O buffers
      reside in AHB SRAM.

-USB Host Configuration
-======================
-
-The LPC4330-Xplorer board supports a USB host interface.  The hidkbd
-example can be used to test this interface.
-
-The NuttShell (NSH) lpc4330-xplorer can also be modified in order to support USB
-host operations.  To make these modifications, do the following:
-
-1. First configure to build the NSH configuration from the top-level
-   NuttX directory:
-
-   cd tools
-   ./configure lpc4330-xplorer/nsh
-   cd ..
-
-2. Then edit the top-level .config file to enable USB host.  Make the
-   following changes:
-
-   CONFIG_LPC43_USBHOST=n
-   CONFIG_USBHOST=n
-   CONFIG_SCHED_WORKQUEUE=y
-
-When this change is made, NSH should be extended to support USB flash
-devices.  When a FLASH device is inserted, you should see a device
-appear in the /dev (pseudo) directory.  The device name should be
-like /dev/sda, /dev/sdb, etc.  The USB mass storage device, is present
-it can be mounted from the NSH command line like:
-
-   ls /dev
-   mount -t vfat /dev/sda /mnt/flash
-
-Files on the connect USB flash device should then be accessible under
-the mountpoint /mnt/flash.
-
 Configurations
 ==============

@@ -901,12 +905,12 @@ Where <subdir> is one of the following:
      CONFIG_BOOT_SRAM=y             : Executing in SRAM
      CONFIG_LPC32_CODEREDW=y        : Code Red under Windows

-    To execute from SRAM, you would need to set:
+    To execute from SPIFI, you would need to set:

      CONFIG_BOOT_SPIFI=y            : Executing from SPIFI
      CONFIG_DRAM_SIZE=(128*1024)    : SRAM Bank0 size
      CONFIG_DRAM_START=0x10000000   : SRAM Bank0 base address
-      CONFIG_SPIFI_OFFSET=(128*1024) : SPIFI file system offset
+      CONFIG_SPIFI_OFFSET=(512*1024) : SPIFI file system offset

    CONFIG_MM_REGIONS should also be increased if you want to other SRAM banks
    to the memory pool.
@@ -0,0 +1,141 @@
+/************************************************************************************
+ * configs/olimex-stm32-p107/include/board.h
+ *
+ *   Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+#include "stm32_rcc.h"
+#include "stm32_sdio.h"
+#include "stm32_internal.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+#define BOARD_CFGR_MCO_SOURCE    RCC_CFGR_PLL3CLK
+
+/* Clocking *************************************************************************/
+
+/* On-board crystal frequency is 25MHz (HSE) */
+
+#define STM32_BOARD_XTAL        25000000ul
+#define STM32_PLL_FREQUENCY     (72000000)
+#define STM32_SYSCLK_FREQUENCY  STM32_PLL_FREQUENCY
+
+#define STM32_HCLK_FREQUENCY    STM32_PLL_FREQUENCY
+#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY  /* same as above, to satisfy compiler */
+
+/* APB2 clock (PCLK2) is HCLK (72MHz) */
+
+#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK
+#define STM32_PCLK2_FREQUENCY   STM32_HCLK_FREQUENCY
+#define STM32_APB2_CLKIN        (STM32_PCLK2_FREQUENCY)   /* Timers 2-7, 12-14 */
+
+/* APB2 timers 1 and 8 will receive PCLK2. */
+
+#define STM32_APB2_TIM1_CLKIN   (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN   (STM32_PCLK2_FREQUENCY)
+
+/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
+
+#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd2
+#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
+
+/* APB1 timers 2-4 will be twice PCLK1 (I presume the remaining will receive PCLK1) */
+
+#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN   (STM32_PCLK1_FREQUENCY)
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+/************************************************************************************
+ * Name: stm32_boardinitialize
+ *
+ * Description:
+ *   All STM32 architectures must provide the following entry point.  This entry point
+ *   is called early in the intitialization -- after all memory has been configured
+ *   and mapped but before any devices have been initialized.
+ *
+ ************************************************************************************/
+
+void stm32_boardinitialize(void);
+
+/************************************************************************************
+ * Name: stm32_board_clockconfig
+ *
+ * Description:
+ *   Any STM32 board may replace the "standard" board clock configuration logic with
+ *   its own, custom clock cofiguration logic.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
+void stm32_board_clockconfig(void);
+#endif
+
+/************************************************************************************
+ * Name: stm32_selectrmii
+ *
+ * Description:
+ *   Selects the RMII inteface.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ************************************************************************************/
+
+static inline void stm32_selectrmii(void)
+{
+  uint32_t regval;
+
+  regval = getreg32(STM32_AFIO_MAPR);
+  regval |= AFIO_MAPR_MII_RMII_SEL;
+  putreg32(regval, STM32_AFIO_MAPR);
+}
+
@@ -0,0 +1,174 @@
+############################################################################
+# configs/olimex-stm32-p107/nsh/Make.defs
+#
+#   Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+
+# Setup for the selected toolchain
+
+ifeq ($(CONFIG_STM32_DFU),y)
+  LDSCRIPT = ld.script.dfu
+else
+  LDSCRIPT = ld.script
+endif
+
+ifeq ($(CONFIG_STM32_CODESOURCERYW),y)
+  # CodeSourcery under Windows
+  CROSSDEV = arm-none-eabi-
+  WINTOOL = y
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+endif
+ifeq ($(CONFIG_STM32_CODESOURCERYL),y)
+  # CodeSourcery under Linux
+  CROSSDEV = arm-none-eabi-
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+  MAXOPTIMIZATION = -O2
+endif
+ifeq ($(CONFIG_STM32_DEVKITARM),y)
+  # devkitARM under Windows
+  CROSSDEV = arm-eabi-
+  WINTOOL = y
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+endif
+ifeq ($(CONFIG_STM32_RAISONANCE),y)
+  # Raisonance RIDE7 under Windows
+  CROSSDEV = arm-none-eabi-
+  WINTOOL = y
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+endif
+ifeq ($(CONFIG_STM32_BUILDROOT),y)
+  # NuttX buildroot under Linux or Cygwin
+  CROSSDEV = arm-elf-
+  ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft
+  MAXOPTIMIZATION = -Os
+endif
+
+ifeq ($(WINTOOL),y)
+  # Windows-native toolchains
+  DIRLINK = $(TOPDIR)/tools/winlink.sh
+  DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+  MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+  ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+  ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+  MAXOPTIMIZATION = -O2
+else
+  # Linux/Cygwin-native toolchain 
+  MKDEP = $(TOPDIR)/tools/mkdeps.sh
+  ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+  ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(CROSSDEV)ar rcs
+NM = $(CROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ("${CONFIG_DEBUG_SYMBOLS}","y")
+  ARCHOPTIMIZATION = -g
+else
+  ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow
+ARCHWARNINGSXX = -Wall -Wshadow
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-elf-)
+  LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  LDFLAGS += -g
+endif
+
+define PREPROCESS
+	@echo "CPP: $1->$2"
+	@$(CPP) $(CPPFLAGS) $1 -o $2
+endef
+
+define COMPILE
+	@echo "CC: $1"
+	@$(CC) -c $(CFLAGS) $1 -o $2
+endef
+
+define COMPILEXX
+	@echo "CXX: $1"
+	@$(CXX) -c $(CXXFLAGS) $1 -o $2
+endef
+
+define ASSEMBLE
+	@echo "AS: $1"
+	@$(CC) -c $(AFLAGS) $1 -o $2
+endef
+
+define ARCHIVE
+	echo "AR: $2"; \
+	$(AR) $1 $2 || { echo "$(AR) $1 $2 FAILED!" ; exit 1 ; }
+endef
+
+define CLEAN
+	@rm -f *.o *.a
+endef
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe
+HOSTLDFLAGS =
+
@@ -0,0 +1,54 @@
+############################################################################
+# configs/olimex-stm32-p107/nsh/appconfig
+#
+#   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+# Path to example in apps/examples containing the user_start entry point
+
+CONFIGURED_APPS += system/readline
+CONFIGURED_APPS += nshlib
+
+CONFIGURED_APPS += examples/nsh
+
+ifeq ($(CONFIG_NET),y)
+CONFIGURED_APPS += netutils/uiplib
+# CONFIGURED_APPS += netutils/resolv
+# CONFIGURED_APPS += netutils/webclient
+# CONFIGURED_APPS += netutils/tftpc
+# CONFIGURED_APPS += netutils/ftpc
+# CONFIGURED_APPS += netutils/ftpd
+ifeq ($(CONFIG_NSH_TELNET),y)
+CONFIGURED_APPS += netutils/telnetd
+endif
+endif
+
@@ -0,0 +1,75 @@
+#!/bin/bash
+# configs/olimex-stm32-p107/nsh/setenv.sh
+#
+#   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$_" = "$0" ] ; then
+  echo "You must source this script, not run it!" 1>&2
+  exit 1
+fi
+
+WD=`pwd`
+if [ ! -x "setenv.sh" ]; then
+  echo "This script must be executed from the top-level NuttX build directory"
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+  export PATH_ORIG="${PATH}"
+fi
+
+# This the Cygwin path to the location where I installed the RIDE
+# toolchain under windows.  You will also have to edit this if you install
+# the RIDE toolchain in any other location
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin"
+
+# This the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows.  You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+
+# These are the Cygwin paths to the locations where I installed the Atollic
+# toolchain under windows.  You will also have to edit this if you install
+# the Atollic toolchain in any other location.  /usr/bin is added before
+# the Atollic bin path because there is are binaries named gcc.exe and g++.exe
+# at those locations as well.
+#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin"
+#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin"
+
+# This the Cygwin path to the location where I build the buildroot
+# toolchain.
+#export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
+
+echo "PATH : ${PATH}"
@@ -0,0 +1,174 @@
+############################################################################
+# configs/olimex-stm32-p107/ostest/Make.defs
+#
+#   Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+
+# Setup for the selected toolchain
+
+ifeq ($(CONFIG_STM32_DFU),y)
+  LDSCRIPT = ld.script.dfu
+else
+  LDSCRIPT = ld.script
+endif
+
+ifeq ($(CONFIG_STM32_CODESOURCERYW),y)
+  # CodeSourcery under Windows
+  CROSSDEV = arm-none-eabi-
+  WINTOOL = y
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+endif
+ifeq ($(CONFIG_STM32_CODESOURCERYL),y)
+  # CodeSourcery under Linux
+  CROSSDEV = arm-none-eabi-
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+  MAXOPTIMIZATION = -O2
+endif
+ifeq ($(CONFIG_STM32_DEVKITARM),y)
+  # devkitARM under Windows
+  CROSSDEV = arm-eabi-
+  WINTOOL = y
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+endif
+ifeq ($(CONFIG_STM32_RAISONANCE),y)
+  # Raisonance RIDE7 under Windows
+  CROSSDEV = arm-none-eabi-
+  WINTOOL = y
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+endif
+ifeq ($(CONFIG_STM32_BUILDROOT),y)
+  # NuttX buildroot under Linux or Cygwin
+  CROSSDEV = arm-elf-
+  ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft
+  MAXOPTIMIZATION = -Os
+endif
+
+ifeq ($(WINTOOL),y)
+  # Windows-native toolchains
+  DIRLINK = $(TOPDIR)/tools/winlink.sh
+  DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+  MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+  ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+  ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+  MAXOPTIMIZATION = -O2
+else
+  # Linux/Cygwin-native toolchain 
+  MKDEP = $(TOPDIR)/tools/mkdeps.sh
+  ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+  ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(CROSSDEV)ar rcs
+NM = $(CROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ("${CONFIG_DEBUG_SYMBOLS}","y")
+  ARCHOPTIMIZATION = -g
+else
+  ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow
+ARCHWARNINGSXX = -Wall -Wshadow
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-elf-)
+  LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  LDFLAGS += -g
+endif
+
+define PREPROCESS
+	@echo "CPP: $1->$2"
+	@$(CPP) $(CPPFLAGS) $1 -o $2
+endef
+
+define COMPILE
+	@echo "CC: $1"
+	@$(CC) -c $(CFLAGS) $1 -o $2
+endef
+
+define COMPILEXX
+	@echo "CXX: $1"
+	@$(CXX) -c $(CXXFLAGS) $1 -o $2
+endef
+
+define ASSEMBLE
+	@echo "AS: $1"
+	@$(CC) -c $(AFLAGS) $1 -o $2
+endef
+
+define ARCHIVE
+	echo "AR: $2"; \
+	$(AR) $1 $2 || { echo "$(AR) $1 $2 FAILED!" ; exit 1 ; }
+endef
+
+define CLEAN
+	@rm -f *.o *.a
+endef
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe
+HOSTLDFLAGS =
+
@@ -0,0 +1,38 @@
+############################################################################
+# configs/olimex-stm32-p107/ostest/appconfig
+#
+#   Copyright (C) 2011 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+# Path to example in apps/examples containing the user_start entry point
+
+CONFIGURED_APPS += examples/ostest
@@ -0,0 +1,75 @@
+#!/bin/bash
+# configs/olimex-stm32-p107/ostest/setenv.sh
+#
+#   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$_" = "$0" ] ; then
+  echo "You must source this script, not run it!" 1>&2
+  exit 1
+fi
+
+WD=`pwd`
+if [ ! -x "setenv.sh" ]; then
+  echo "This script must be executed from the top-level NuttX build directory"
+  exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then
+  export PATH_ORIG="${PATH}"
+fi
+
+# This the Cygwin path to the location where I installed the RIDE
+# toolchain under windows.  You will also have to edit this if you install
+# the RIDE toolchain in any other location
+#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin"
+
+# This the Cygwin path to the location where I installed the CodeSourcery
+# toolchain under windows.  You will also have to edit this if you install
+# the CodeSourcery toolchain in any other location
+export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
+
+# These are the Cygwin paths to the locations where I installed the Atollic
+# toolchain under windows.  You will also have to edit this if you install
+# the Atollic toolchain in any other location.  /usr/bin is added before
+# the Atollic bin path because there is are binaries named gcc.exe and g++.exe
+# at those locations as well.
+#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin"
+#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin"
+
+# This the Cygwin path to the location where I build the buildroot
+# toolchain.
+#export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
+
+echo "PATH : ${PATH}"
@@ -0,0 +1,106 @@
+/****************************************************************************
+ * configs/olimex-stm32-p107/scripts/ld.script
+ *
+ *   Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+MEMORY
+{
+	flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+	sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+
+}
+
+OUTPUT_ARCH(arm)
+ENTRY(_stext)
+SECTIONS
+{
+	.text : {
+		_stext = ABSOLUTE(.);
+		*(.vectors)
+		*(.text .text.*)        
+		*(.fixup)
+		*(.gnu.warning)
+		*(.rodata .rodata.*)        
+		*(.gnu.linkonce.t.*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.got)
+		*(.gcc_except_table)
+		*(.gnu.linkonce.r.*)
+		_etext = ABSOLUTE(.);
+	} > flash
+
+	_eronly = ABSOLUTE(.);
+
+	/* The STM32F107VC has 64Kb of SRAM beginning at the following address */
+
+	.data : {
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		CONSTRUCTORS
+		_edata = ABSOLUTE(.);
+	} > sram AT > flash
+
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} >sram
+
+	__exidx_start = ABSOLUTE(.);
+	.ARM.exidx : {
+		*(.ARM.exidx*)
+	} >sram
+	__exidx_end = ABSOLUTE(.);
+
+	.bss : {
+		_sbss = ABSOLUTE(.);
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		_ebss = ABSOLUTE(.);
+	} > sram
+
+	/* Stabs debugging sections. */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
@@ -0,0 +1,106 @@
+/****************************************************************************
+ * configs/olimex-stm32-p107/scripts/ld.script.dfu
+ *
+ *   Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* Don't know if this is correct. Just 256K-48K (not testet) */
+MEMORY
+{
+    flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K
+    sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+OUTPUT_ARCH(arm)
+ENTRY(_stext)
+SECTIONS
+{
+	.text : {
+		_stext = ABSOLUTE(.);
+		*(.vectors)
+		*(.text .text.*)        
+		*(.fixup)
+		*(.gnu.warning)
+		*(.rodata .rodata.*)        
+		*(.gnu.linkonce.t.*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.got)
+		*(.gcc_except_table)
+		*(.gnu.linkonce.r.*)
+		_etext = ABSOLUTE(.);
+	} > flash
+
+	_eronly = ABSOLUTE(.);
+
+	/* The STM32F103Z has 64Kb of SRAM beginning at the following address */
+
+	.data : {
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		CONSTRUCTORS
+		_edata = ABSOLUTE(.);
+	} > sram AT > flash
+
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} >sram
+
+	__exidx_start = ABSOLUTE(.);
+	.ARM.exidx : {
+		*(.ARM.exidx*)
+	} >sram
+	__exidx_end = ABSOLUTE(.);
+
+	.bss : {
+		_sbss = ABSOLUTE(.);
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		_ebss = ABSOLUTE(.);
+	} > sram
+
+	/* Stabs debugging sections. */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
@@ -0,0 +1,89 @@
+############################################################################
+# configs/olimex-stm32-p107/src/Makefile
+#
+#   Copyright (C) 2009-2010, 2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+
+CFLAGS		+= -I$(TOPDIR)/sched
+
+ASRCS		= 
+AOBJS		= $(ASRCS:.S=$(OBJEXT))
+
+CSRCS		= up_boot.c
+
+ifeq ($(CONFIG_CAN),y)
+CSRCS		+= up_can.c
+endif
+
+COBJS		= $(CSRCS:.c=$(OBJEXT))
+
+SRCS		= $(ASRCS) $(CSRCS)
+OBJS		= $(AOBJS) $(COBJS)
+
+ARCH_SRCDIR	= $(TOPDIR)/arch/$(CONFIG_ARCH)/src
+ifeq ($(WINTOOL),y)
+  CFLAGS	+= -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
+			-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
+			-I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
+else
+  CFLAGS	+= -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
+endif
+
+all: libboard$(LIBEXT)
+
+$(AOBJS): %$(OBJEXT): %.S
+	$(call ASSEMBLE, $<, $@)
+
+$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c
+	$(call COMPILE, $<, $@)
+
+libboard$(LIBEXT): $(OBJS)
+	@( for obj in $(OBJS) ; do \
+		$(call ARCHIVE, $@, $${obj}); \
+	done ; )
+
+.depend: Makefile $(SRCS)
+	@$(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
+	@touch $@
+
+depend: .depend
+
+clean:
+	@rm -f libboard$(LIBEXT) *~ .*.swp
+	$(call CLEAN)
+
+distclean: clean
+	@rm -f Make.dep .depend
+
+-include Make.dep
@@ -0,0 +1,181 @@
+/************************************************************************************
+ * configs/olimex-stm32-p107/src/up_boot.c
+ * arch/arm/src/board/up_boot.c
+ *
+ *   Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_boardinitialize
+ *
+ * Description:
+ *   All STM32 architectures must provide the following entry point.  This entry point
+ *   is called early in the intitialization -- after all memory has been configured
+ *   and mapped but before any devices have been initialized.
+ *
+ ************************************************************************************/
+
+void stm32_boardinitialize(void)
+{
+}
+
+/************************************************************************************
+ * Name: stm32_board_clockconfig
+ *
+ * Description:
+ *   Any STM32 board may replace the "standard" board clock configuration logic with
+ *   its own, custom clock cofiguration logic.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
+void stm32_board_clockconfig(void)
+{
+  uint32_t regval;
+    
+  regval  = getreg32(STM32_RCC_CR);
+  regval &= ~RCC_CR_HSEBYP;         /* Disable HSE clock bypass */
+  regval |= RCC_CR_HSEON;           /* Enable HSE */
+  putreg32(regval, STM32_RCC_CR);
+
+  /* Set flash wait states
+   * Sysclk runs with 72MHz -> 2 waitstates.
+   * 0WS from 0-24MHz
+   * 1WS from 24-48MHz
+   * 2WS from 48-72MHz
+   */
+
+  regval  = getreg32(STM32_FLASH_ACR);
+  regval &= ~FLASH_ACR_LATENCY_MASK;
+  regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE);
+  putreg32(regval, STM32_FLASH_ACR);
+     
+  regval = getreg32(STM32_RCC_CFGR2);
+  regval &= ~(RCC_CFGR2_PREDIV2_MASK 
+        | RCC_CFGR2_PLL2MUL_MASK
+        | RCC_CFGR2_PREDIV1SRC_MASK
+        | RCC_CFGR2_PREDIV1_MASK);
+  regval |= RCC_CFGR2_PREDIV2d5;       /* 25MHz / 5 */
+  regval |= RCC_CFGR2_PLL2MULx8;       /* 5MHz * 8 => 40MHz */
+  regval |= RCC_CFGR2_PREDIV1SRC_PLL2; /* Use PLL2 as input for PREDIV1 */
+  regval |= RCC_CFGR2_PREDIV1d5;       /* 40MHz / 5 => 8MHz */
+  putreg32(regval, STM32_RCC_CFGR2);
+
+  /* Set the PCLK2 divider */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~(RCC_CFGR_PPRE2_MASK | RCC_CFGR_HPRE_MASK);
+  regval |= STM32_RCC_CFGR_PPRE2;
+  regval |= RCC_CFGR_HPRE_SYSCLK;
+  putreg32(regval, STM32_RCC_CFGR);
+  
+  /* Set the PCLK1 divider */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_PPRE1_MASK;
+  regval |= STM32_RCC_CFGR_PPRE1;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  regval = getreg32(STM32_RCC_CR);
+  regval |= RCC_CR_PLL2ON;
+  putreg32(regval, STM32_RCC_CR);
+
+  /* Wait for PLL2 ready */
+
+  while((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0);
+
+  /* Setup PLL3 for RMII clock on MCO */
+
+  regval = getreg32(STM32_RCC_CFGR2);
+  regval &= ~(RCC_CFGR2_PLL3MUL_MASK);
+  regval |= RCC_CFGR2_PLL3MULx10;
+  putreg32(regval, STM32_RCC_CFGR2);
+
+  /* Switch PLL3 on */
+
+  regval = getreg32(STM32_RCC_CR);
+  regval |= RCC_CR_PLL3ON;
+  putreg32(regval, STM32_RCC_CR);
+    
+  while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL3RDY) == 0);
+
+  /* Set main PLL source 8MHz * 9 => 72MHz*/
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK);
+  regval |= (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_CLKx9);
+  putreg32(regval, STM32_RCC_CFGR);
+    
+  /* Switch main PLL on */
+
+  regval = getreg32(STM32_RCC_CR);
+  regval |= RCC_CR_PLLON;
+  putreg32(regval, STM32_RCC_CR);
+
+  while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
+
+  /* Select PLL as system clock source */
+
+  regval  = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_SW_MASK;
+  regval |= RCC_CFGR_SW_PLL;
+  putreg32(regval, STM32_RCC_CFGR);
+   
+  /* Wait until PLL is used as the system clock source */
+
+  while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_PLL) == 0);
+}
+#endif
@@ -0,0 +1,132 @@
+/************************************************************************************
+ * configs/olimex-stm32-p107/src/up_can.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/can.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+
+#include "stm32.h"
+#include "stm32_can.h"
+
+#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2))
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Configuration ********************************************************************/
+/* The STM32F107VC supports CAN1 and CAN2 */
+
+#define CAN_PORT 1
+
+/* Debug ***************************************************************************/
+/* Non-standard debug that may be enabled just for testing CAN */
+
+#ifdef CONFIG_DEBUG_CAN
+#  define candbg    dbg
+#  define canvdbg   vdbg
+#  define canlldbg  lldbg
+#  define canllvdbg llvdbg
+#else
+#  define candbg(x...)
+#  define canvdbg(x...)
+#  define canlldbg(x...)
+#  define canllvdbg(x...)
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: can_devinit
+ *
+ * Description:
+ *   All STM32 architectures must provide the following interface to work with
+ *   examples/can.
+ *
+ ************************************************************************************/
+
+int can_devinit(void)
+{
+  static bool initialized = false;
+  struct can_dev_s *can;
+  int ret;
+
+  /* Check if we have already initialized */
+
+  if (!initialized)
+    {
+      /* Call stm32_caninitialize() to get an instance of the CAN interface */
+
+      can = stm32_caninitialize(CAN_PORT);
+      if (can == NULL)
+        {
+          candbg("ERROR:  Failed to get CAN interface\n");
+          return -ENODEV;
+        }
+
+      /* Register the CAN driver at "/dev/can0" */
+
+      ret = can_register("/dev/can0", can);
+      if (ret < 0)
+        {
+          candbg("ERROR: can_register failed: %d\n", ret);
+          return ret;
+        }
+
+      /* Now we are initialized */
+
+      initialized = true;
+    }
+
+  return OK;
+}
+
+#endif /* CONFIG_CAN && CONFIG_STM32_CAN1 */
@@ -45,6 +45,7 @@
 ************************************************************************************/

 #include <nuttx/config.h>
+
 #ifndef __ASSEMBLY__
 # include <stdint.h>
 #endif
@@ -54,7 +55,6 @@

 #include "muxbus.h"

-
 /************************************************************************************
 * Definitions
 ************************************************************************************/
@@ -88,9 +88,9 @@

 /* AHB clock (HCLK, 36 MHz) is SYSCLK on HSI or SYSCLK/2 on HSE */

-#define STM32_RCC_CFGR_HPRE_HSI	RCC_CFGR_HPRE_SYSCLK
-#define STM32_RCC_CFGR_HPRE_HSE	RCC_CFGR_HPRE_SYSCLKd2
-#define STM32_HCLK_FREQUENCY   	STM32_BOARD_HCLK
+#define STM32_RCC_CFGR_HPRE_HSI RCC_CFGR_HPRE_SYSCLK
+#define STM32_RCC_CFGR_HPRE_HSE RCC_CFGR_HPRE_SYSCLKd2
+#define STM32_HCLK_FREQUENCY    STM32_BOARD_HCLK

 /* APB2 clock (PCLK2) is HCLK (36MHz) */

@@ -179,7 +179,7 @@
 #define LED_SIGNAL        5  /* ... */
 #define LED_ASSERTION     6  /* ... */
 #define LED_PANIC         7  /* ... */
-#define LED_IDLE		  8	 /* shows idle state */
+#define LED_IDLE          8  /* shows idle state */


 /************************************************************************************
@@ -200,9 +200,6 @@ extern "C" {
 * Board Clock Configuration, called immediatelly after boot
 ************************************************************************************/
 
-EXTERN void stm32_board_clockconfig(void);
-
- 
 /************************************************************************************
 * Name: stm32_boardinitialize
 *
@@ -215,6 +212,18 @@ EXTERN void stm32_board_clockconfig(void);

 EXTERN void stm32_boardinitialize(void);

+/************************************************************************************
+ * Name: stm32_board_clockconfig
+ *
+ * Description:
+ *   Any STM32 board may replace the "standard" board clock configuration logic with
+ *   its own, custom clock cofiguration logic.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
+EXTERN void stm32_board_clockconfig(void);
+#endif

 /************************************************************************************
 * Button support. (TODO: button is not yet supported)
@@ -225,7 +234,6 @@ EXTERN void up_buttoninit(void);
 EXTERN uint8_t up_buttons(void);
 #endif

-
 #undef EXTERN
 #if defined(__cplusplus)
 }