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Merged nuttx/nuttx into master

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Young
2016-08-10 13:16:28 +08:00
parent 358a265c4a 7823a1680e
commit 4838528266
628 changed files with 4649 additions and 2408 deletions
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Documentation/README.html
+3 -3
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@@ -31,11 +31,11 @@ nuttx/
| |- arm/
| | `- src
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/arm/src/lpc214x/README.txt" target="_blank">lpc214x/README.txt</a>
| |- sh/
| |- renesas/
| | |- include/
| | | `-<a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/sh/include/README.txt" target="_blank">README.txt</a>
| | | `-<a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/renesas/include/README.txt" target="_blank">README.txt</a>
| | |- src/
| | | `-<a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/sh/src/README.txt" target="_blank">README.txt</a>
| | | `-<a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/renesas/src/README.txt" target="_blank">README.txt</a>
| |- x86/
| | |- include/
| | | `-<a href="https://bitbucket.org/nuttx/nuttx/src/master/arch/x86/include/README.txt" target="_blank">README.txt</a>
README.txt
+1 -1
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@@ -1250,7 +1250,7 @@ nuttx/
| |- arm/
| | `- src
| | `- lpc214x/README.txt
| |- sh/
| |- renesas/
| | |- include/
| | | `-README.txt
| | |- src/
TODO
+1 -1
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@@ -1737,7 +1737,7 @@ o ARM (arch/arm/)
upon return. This could be improved as well: If there is no
context switch, then the static registers need not be restored
because they will not be modified by the called C code.
(see arch/sh/src/sh1/sh1_vector.S for example)
(see arch/renesas/src/sh1/sh1_vector.S for example)
Status: Open
Priority: Low
arch/Kconfig
+12 -12
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@@ -45,7 +45,7 @@ config ARCH_RGMP
RTOS and GPOS on Multi-Processor (RGMP) architecture. See
http://rgmp.sourceforge.net/wiki/index.php/Main_Page.
config ARCH_SH
config ARCH_RENESAS
bool "Renesas"
select ARCH_NOINTC
select ARCH_HAVE_INTERRUPTSTACK
@@ -83,23 +83,23 @@ endchoice
config ARCH
string
default "arm" if ARCH_ARM
default "avr" if ARCH_AVR
default "hc" if ARCH_HC
default "mips" if ARCH_MIPS
default "rgmp" if ARCH_RGMP
default "sh" if ARCH_SH
default "sim" if ARCH_SIM
default "x86" if ARCH_X86
default "z16" if ARCH_Z16
default "z80" if ARCH_Z80
default "arm" if ARCH_ARM
default "avr" if ARCH_AVR
default "hc" if ARCH_HC
default "mips" if ARCH_MIPS
default "rgmp" if ARCH_RGMP
default "renesas" if ARCH_RENESAS
default "sim" if ARCH_SIM
default "x86" if ARCH_X86
default "z16" if ARCH_Z16
default "z80" if ARCH_Z80
source arch/arm/Kconfig
source arch/avr/Kconfig
source arch/hc/Kconfig
source arch/mips/Kconfig
source arch/rgmp/Kconfig
source arch/sh/Kconfig
source arch/renesas/Kconfig
source arch/sim/Kconfig
source arch/x86/Kconfig
source arch/z16/Kconfig
arch/README.txt
+13 -10
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@@ -150,11 +150,13 @@ arch/arm - ARM-based micro-controllers
Architecture Support
arch/arm/include and arch/arm/src/common
arch/arm/src/arm and arch/arm/include/arm
arch/arm/src/armv7-a and arch/arm/include/armv6-m
arch/arm/src/armv7-a and arch/arm/include/armv7-a
arch/arm/src/armv7-m and arch/arm/include/armv7-m
arch/arm/src/armv7-r and arch/arm/include/armv7-4
arch/arm/src/armv7-r and arch/arm/include/armv7-r
MCU support
arch/arm/include/a1x and arch/arm/src/a1x
arch/arm/include/c5471 and arch/arm/src/c5471
arch/arm/include/calypso and arch/arm/src/calypso
arch/arm/include/dm320 and arch/arm/src/dm320
@@ -210,6 +212,16 @@ arch/mips
arch/mips/include/pic32mx and arch/mips/src/pic32mx
arch/mips/include/pic32mz and arch/mips/src/pic32mz
arch/renesas - Support for Renesas and legacy Hitachi microcontrollers.
This include SuperH and M16C.
Architecture Support
arch/renesas/include and arch/renesas/src/common
MCU support
arch/renesas/include/m16c and arch/renesas/src/m16c
arch/renesas/include/sh1 and arch/renesas/src/sh1
arch/rgmp
RGMP stands for RTOS and GPOS on Multi-Processor. RGMP is a project
@@ -221,15 +233,6 @@ arch/rgmp
See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further
information about RGMP.
arch/sh - SuperH and related Hitachi/Renesas microcontrollers
Architecture Support
arch/sh/include and arch/sh/src/common
MCU support
arch/sh/include/m16c and arch/sh/src/m16c
arch/sh/include/sh1 and arch/sh/src/sh1
arch/x86 - Intel x86 architectures
This directory holds related, 32- and 64-bit architectures from Intel.
At present, this includes the following subdirectories:
arch/arm/Kconfig
+13 -8
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@@ -51,6 +51,7 @@ config ARCH_CHIP_DM320
config ARCH_CHIP_EFM32
bool "Energy Micro"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_SPI_BITORDER
select ARMV7M_CMNVECTOR
---help---
Energy Micro EFM32 microcontrollers (ARM Cortex-M).
@@ -206,14 +207,15 @@ config ARCH_CHIP_SAM34
config ARCH_CHIP_SAMV7
bool "Atmel SAMV7"
select ARCH_HAVE_CMNVECTOR
select ARMV7M_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_TICKLESS
select ARMV7M_HAVE_STACKCHECK
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_SPI_CS_CONTROL
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
Atmel SAMV7 (ARM Cortex-M7) architectures
@@ -221,11 +223,12 @@ config ARCH_CHIP_STM32
bool "STMicro STM32 F1/F2/F3/F4"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_TIMEKEEPING
select ARCH_HAVE_SPI_BITORDER
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M3/4).
@@ -233,12 +236,13 @@ config ARCH_CHIP_STM32
config ARCH_CHIP_STM32F7
bool "STMicro STM32 F7"
select ARCH_HAVE_CMNVECTOR
select ARMV7M_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_SPI_BITORDER
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M7).
@@ -246,13 +250,14 @@ config ARCH_CHIP_STM32F7
config ARCH_CHIP_STM32L4
bool "STMicro STM32 L4"
select ARCH_HAVE_CMNVECTOR
select ARMV7M_CMNVECTOR
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_SPI_BITORDER
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M4).
arch/arm/include/calypso/clock.h
+3 -3
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@@ -1,5 +1,5 @@
#ifndef _CALYPSO_CLK_H
#define _CALYPSO_CLK_H
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H
#define __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H
#include <stdint.h>
@@ -64,4 +64,4 @@ void calypso_debugunit(int enable);
void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout,
uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1);
#endif /* _CALYPSO_CLK_H */
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H */
arch/arm/include/calypso/debug.h
+3 -3
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@@ -1,5 +1,5 @@
#ifndef _DEBUG_H
#define _DEBUG_H
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H
#define __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
@@ -28,4 +28,4 @@
#define printd(x, args ...)
#endif
#endif /* _DEBUG_H */
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H */
arch/arm/include/calypso/defines.h
+3 -4
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@@ -1,6 +1,5 @@
#ifndef _DEFINES_H
#define _DEFINES_H
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H
#define __ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H
#define __attribute_const__ __attribute__((__const__))
@@ -15,4 +14,4 @@
/* force placement in zero-waitstate memory */
#define __ramtext __section(".ramtext")
#endif /* !_DEFINES_H */
#endif /* !__ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H */
arch/arm/include/calypso/irq.h
+3 -3
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@@ -41,8 +41,8 @@
#error "This file should never be included directly! Use <nuttx/irq.h>"
#endif
#ifndef _CALYPSO_IRQ_H
#define _CALYPSO_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H
#define __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H
#ifndef __ASSEMBLY__
@@ -78,4 +78,4 @@ enum irq_nr {
#define IRQ_SYSTIMER IRQ_TIMER2
#endif /* _CALYPSO_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H */
arch/arm/include/calypso/memory.h
+3 -3
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@@ -1,5 +1,5 @@
#ifndef _MEMORY_H
#define _MEMORY_H
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H
#define __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short *)(a))
@@ -25,4 +25,4 @@
#define readw(a) __arch_getw(a)
#define readl(a) __arch_getl(a)
#endif /* _MEMORY_H */
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H */
arch/arm/include/calypso/timer.h
+3 -3
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@@ -1,5 +1,5 @@
#ifndef _CAL_TIMER_H
#define _CAL_TIMER_H
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H
#define __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H
/* Enable or Disable a timer */
void hwtimer_enable(int num, int on);
@@ -22,4 +22,4 @@ void wdog_reset(void);
/* power up the timers */
void hwtimer_init(void);
#endif /* _CAL_TIMER_H */
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H */
arch/arm/include/calypso/uwire.h
+2 -2
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@@ -1,5 +1,5 @@
#ifndef _CALYPSO_UWIRE_H
#define _CALYPSO_UWIRE_H
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_UWIRE_H
#define __ARCH_ARM_INCLUDE_CALYPSO_UWIRE_H
void uwire_init(void);
int uwire_xfer(int cs, int bitlen, const void *dout, void *din);
#endif
arch/arm/include/lpc214x/irq.h
+3 -3
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@@ -37,8 +37,8 @@
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_LPC214X_IRQ_H
#define __ARCH_LPC214X_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_LPC214X_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC214X_IRQ_H
/****************************************************************************
* Included Files
@@ -127,5 +127,5 @@ void up_detach_vector(int vector);
#endif
#endif
#endif /* __ARCH_LPC214X_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_LPC214X_IRQ_H */
arch/arm/include/lpc2378/irq.h
+3 -3
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@@ -43,8 +43,8 @@
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_LPC2378_IRQ_H
#define __ARCH_LPC2378_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_LPC2378_IRQ_H
#define __ARCH_ARM_INCLUDE_LPC2378_IRQ_H
/****************************************************************************
* Included Files
@@ -149,4 +149,4 @@ void up_detach_vector(int vector);
#endif
#endif
#endif /* __ARCH_LPC2378_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_LPC2378_IRQ_H */
arch/arm/src/c5471/chip.h
+4 -4
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@@ -1,5 +1,5 @@
/****************************************************************************
* c5471/chip.h
* arch/arm/src/c5471/chip.h
*
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __C5471_CHIP_H
#define __C5471_CHIP_H
#ifndef __ARCH_ARM_SRC_C5471_CHIP_H
#define __ARCH_ARM_SRC_C5471_CHIP_H
/****************************************************************************
* Included Files
@@ -368,4 +368,4 @@
* Public Function Prototypes
****************************************************************************/
#endif /* __C5471_CHIP_H */
#endif /* __ARCH_ARM_SRC_C5471_CHIP_H */
arch/arm/src/calypso/chip.h
+3 -3
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@@ -37,8 +37,8 @@
*
****************************************************************************/
#ifndef __CALYPSO_CHIP_H
#define __CALYPSO_CHIP_H
#ifndef __ARCH_ARM_SRC_CALYPSO_CHIP_H
#define __ARCH_ARM_SRC_CALYPSO_CHIP_H
/****************************************************************************
* Included Files
@@ -208,4 +208,4 @@
* Public Function Prototypes
****************************************************************************/
#endif /* __CALYPSO_CHIP_H */
#endif /* __ARCH_ARM_SRC_CALYPSO_CHIP_H */
arch/arm/src/dm320/chip.h
+3 -3
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@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __DM320_CHIP_H
#define __DM320_CHIP_H
#ifndef __ARCH_ARM_SRC_DM320_CHIP_H
#define __ARCH_ARM_SRC_DM320_CHIP_H
/************************************************************************************
* Included Files
@@ -58,4 +58,4 @@
* Inline Functions
************************************************************************************/
#endif /* __DM320_CHIP_H */
#endif /* __ARCH_ARM_SRC_DM320_CHIP_H */
arch/arm/src/dm320/dm320_emif.h
+3 -3
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@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __DM320_DM320_EMIF_H
#define __DM320_DM320_EMIF_H
#ifndef __ARCH_ARM_SRC_DM320_DM320_EMIF_H
#define __ARCH_ARM_SRC_DM320_DM320_EMIF_H
/************************************************************************************
* Included Files
@@ -105,4 +105,4 @@
#endif
#endif /* __DM320_DM320_EMIF_H */
#endif /* __ARCH_ARM_SRC_DM320_DM320_EMIF_H */
arch/arm/src/dm320/dm320_gio.h
+2 -2
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@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __DM320_DM320GIO_H
#define __DM320_DM320GIO_H
#ifndef __ARCH_ARM_SRC_DM320_DM320_GIO_H
#define __ARCH_ARM_SRC_DM320_DM320_GIO_H
/************************************************************************************
* Included Files
arch/arm/src/dm320/dm320_intc.h
+3 -3
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@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __DM320_DM320_INTC_H
#define __DM320_DM320_INTC_H
#ifndef __ARCH_ARM_SRC_DM320_DM320_INTC_H
#define __ARCH_ARM_SRC_DM320_DM320_INTC_H
/************************************************************************************
* Included Files
@@ -98,4 +98,4 @@
#endif
#endif /* __DM320_DM320_INTC_H */
#endif /* __ARCH_ARM_SRC_DM320_DM320_INTC_H */
arch/arm/src/dm320/dm320_memorymap.h
+3 -3
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@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __DM320_MEMORYMAP_H
#define __DM320_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_DM320_DM320_MEMORYMAP_H
#define __ARCH_ARM_SRC_DM320_DM320_MEMORYMAP_H
/************************************************************************************
* Included Files
@@ -261,4 +261,4 @@
#endif
#endif /* __DM320_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_DM320_DM320_MEMORYMAP_H */
arch/arm/src/dm320/dm320_timer.h
+3 -3
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@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __DM320_TIMER_H
#define __DM320_TIMER_H
#ifndef __ARCH_ARM_SRC_DM320_DM320_TIMER_H
#define __ARCH_ARM_SRC_DM320_DM320_TIMER_H
/************************************************************************************
* Included Files
@@ -105,4 +105,4 @@
#endif
#endif /* __DM320_TIMER_H */
#endif /* __ARCH_ARM_SRC_DM320_DM320_TIMER_H */
arch/arm/src/dm320/dm320_uart.h
+3 -3
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@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __DM320_UART_H
#define __DM320_UART_H
#ifndef __ARCH_ARM_SRC_DM320_DM320_UART_H
#define __ARCH_ARM_SRC_DM320_DM320_UART_H
/************************************************************************************
* Included Files
@@ -173,4 +173,4 @@
* Inline Functions
************************************************************************************/
#endif /* __DM320_UART_H */
#endif /* __ARCH_ARM_SRC_DM320_DM320_UART_H */
arch/arm/src/efm32/efm32_spi.c
+76 -36
View File
@@ -185,6 +185,10 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev,
uint32_t frequency);
static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode);
static void spi_setbits(struct spi_dev_s *dev, int nbits);
#ifdef CONFIG_SPI_HWFEATURES
static int spi_hwfeatures(FAR struct spi_dev_s *dev,
spi_hwfeatures_t features);
#endif
static uint8_t spi_status(struct spi_dev_s *dev, enum spi_dev_e devid);
#ifdef CONFIG_SPI_CMDDATA
static int spi_cmddata(struct spi_dev_s *dev, enum spi_dev_e devid,
@@ -218,7 +222,7 @@ static const struct spi_ops_s g_spiops =
.setmode = spi_setmode,
.setbits = spi_setbits,
#ifdef CONFIG_SPI_HWFEATURES
.hwfeatures = 0,
.hwfeatures = spi_hwfeatures,
#endif
.status = spi_status,
#ifdef CONFIG_SPI_CMDDATA
@@ -976,47 +980,16 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
const struct efm32_spiconfig_s *config;
uint32_t regval;
uint32_t setting;
bool lsbfirst;
spiinfo("nbits=%d\n", nbits);
DEBUGASSERT(priv && priv->config);
config = priv->config;
/* Bit order is encoded by the sign of nbits */
/* Has the number of bits changed? */
if (nbits < 0)
if (nbits != priv->nbits)
{
/* LSB first */
lsbfirst = true;
nbits = -nbits;
}
else
{
/* MSH first */
lsbfirst = false;
}
/* Has the number of bits or the bit order changed? */
if (nbits != priv->nbits || lsbfirst != priv->lsbfirst)
{
/* Set the new bit order */
regval = spi_getreg(config, EFM32_USART_CTRL_OFFSET);
if (lsbfirst)
{
regval &= ~USART_CTRL_MSBF;
}
else
{
regval |= USART_CTRL_MSBF;
}
spi_putreg(config, EFM32_USART_CTRL_OFFSET, regval);
/* Select the new number of bits */
switch (nbits)
@@ -1086,11 +1059,78 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
* faster
*/
priv->nbits = nbits;
priv->lsbfirst = lsbfirst;
priv->nbits = nbits;
}
}
/****************************************************************************
* Name: spi_hwfeatures
*
* Description:
* Set hardware-specific feature flags.
*
* Input Parameters:
* dev - Device-specific state data
* features - H/W feature flags
*
* Returned Value:
* Zero (OK) if the selected H/W features are enabled; A negated errno
* value if any H/W feature is not supportable.
*
****************************************************************************/
#ifdef CONFIG_SPI_HWFEATURES
static int spi_hwfeatures(FAR struct spi_dev_s *dev, spi_hwfeatures_t features)
{
#ifdef CONFIG_SPI_BITORDER
struct efm32_spidev_s *priv = (struct efm32_spidev_s *)dev;
const struct efm32_spiconfig_s *config;
uint32_t regval;
bool lsbfirst;
spiinfo("features=%08x\n", features);
DEBUGASSERT(priv && priv->config);
config = priv->config;
/* Bit order is encoded by the sign of nbits */
lsbfirst = ((features & HWFEAT_LSBFIRST) != 0);
/* Has the number of bits or the bit order changed? */
if (lsbfirst != priv->lsbfirst)
{
/* Set the new bit order */
regval = spi_getreg(config, EFM32_USART_CTRL_OFFSET);
if (lsbfirst)
{
regval &= ~USART_CTRL_MSBF;
}
else
{
regval |= USART_CTRL_MSBF;
}
spi_putreg(config, EFM32_USART_CTRL_OFFSET, regval);
/* Save the selection so the subsequence re-configurations will be
* faster
*/
priv->lsbfirst = lsbfirst;
}
/* Other H/W features are not supported */
return ((features & ~HWFEAT_LSBFIRST) == 0) ? OK : -ENOSYS;
#else
return -ENOSYS;
#endif
}
#endif
/****************************************************************************
* Name: spi_status
*
arch/arm/src/lpc214x/chip.h
+3 -3
View File
@@ -33,8 +33,8 @@
*
****************************************************************************************************/
#ifndef __LPC214X_CHIP_H
#define __LPC214X_CHIP_H
#ifndef __ARCH_ARM_SRC_LPC214X_CHIP_H
#define __ARCH_ARM_SRC_LPC214X_CHIP_H
/****************************************************************************************************
* Included Files
@@ -346,4 +346,4 @@
* Public Function Prototypes
****************************************************************************************************/
#endif /* __LPC214X_CHIP_H */
#endif /* __ARCH_ARM_SRC_LPC214X_CHIP_H */
arch/arm/src/lpc214x/lpc214x_apb.h
+3 -3
View File
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC214X_APB_H
#define _ARCH_ARM_SRC_LPC214X_APB_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_APB_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_APB_H
/************************************************************************************
* Included Files
@@ -69,4 +69,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC214X_APB_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_APB_H */
arch/arm/src/lpc214x/lpc214x_i2c.h
+3 -3
View File
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC214X_I2C_H
#define _ARCH_ARM_SRC_LPC214X_I2C_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_I2C_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_I2C_H
/************************************************************************************
* Included Files
@@ -138,4 +138,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC214X_I2C_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_I2C_H */
arch/arm/src/lpc214x/lpc214x_pinsel.h
+3 -3
View File
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC214X_PINSEL_H
#define _ARCH_ARM_SRC_LPC214X_PINSEL_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_PINSEL_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_PINSEL_H
/************************************************************************************
* Included Files
@@ -256,4 +256,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC214X_PINSEL_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_PINSEL_H */
arch/arm/src/lpc214x/lpc214x_pll.h
+3 -3
View File
@@ -33,8 +33,8 @@
*
****************************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC214X_PLL_H
#define _ARCH_ARM_SRC_LPC214X_PLL_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_PLL_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_PLL_H
/****************************************************************************************************
* Included Files
@@ -102,4 +102,4 @@
* Public Function Prototypes
****************************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC214X_PLL_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_PLL_H */
arch/arm/src/lpc214x/lpc214x_power.h
+3 -3
View File
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC214X_POWER_H
#define _ARCH_ARM_SRC_LPC214X_POWER_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_POWER_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_POWER_H
/************************************************************************************
* Included Files
@@ -87,4 +87,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC214X_POWER_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_POWER_H */
arch/arm/src/lpc214x/lpc214x_spi.h
+3 -3
View File
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC214X_SPI_H
#define _ARCH_ARM_SRC_LPC214X_SPI_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_SPI_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_SPI_H
/************************************************************************************
* Included Files
@@ -181,4 +181,4 @@ struct spi_dev_s; /* Forward reference */
FAR struct spi_dev_s *lpc214x_spibus_initialize(int port);
#endif /* _ARCH_ARM_SRC_LPC214X_SPI_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_SPI_H */
arch/arm/src/lpc214x/lpc214x_timer.h
+3 -3
View File
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __LPC214X_TIMER_H
#define __LPC214X_TIMER_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_TIMER_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_TIMER_H
/************************************************************************************
* Included Files
@@ -149,4 +149,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* __LPC214X_TIMER_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_TIMER_H */
arch/arm/src/lpc214x/lpc214x_uart.h
+3 -3
View File
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __LPC214X_UART_H
#define __LPC214X_UART_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_UART_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_UART_H
/************************************************************************************
* Included Files
@@ -139,4 +139,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* __LPC214X_UART_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_UART_H */
arch/arm/src/lpc214x/lpc214x_vic.h
+3 -3
View File
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __LPC214X_VIC_H
#define __LPC214X_VIC_H
#ifndef __ARCH_ARM_SRC_LPC214X_LPC214X_VIC_H
#define __ARCH_ARM_SRC_LPC214X_LPC214X_VIC_H
/************************************************************************************
* Included Files
@@ -67,4 +67,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* __LPC214X_VIC_H */
#endif /* __ARCH_ARM_SRC_LPC214X_LPC214X_VIC_H */
arch/arm/src/lpc2378/chip.h
+3 -3
View File
@@ -38,8 +38,8 @@
*
****************************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC2378_CHIP_H
#define _ARCH_ARM_SRC_LPC2378_CHIP_H
#ifndef __ARCH_ARM_SRC_LPC2378_CHIP_H
#define __ARCH_ARM_SRC_LPC2378_CHIP_H
/****************************************************************************************************
* Included Files
@@ -1003,4 +1003,4 @@ are for LPC24xx only. */
* Public Function Prototypes
****************************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC2378_CHIP_H */
#endif /* __ARCH_ARM_SRC_LPC2378_CHIP_H */
arch/arm/src/lpc2378/lpc2378.h
+3 -3
View File
@@ -38,8 +38,8 @@
*
****************************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC2378_INTERNAL_H
#define _ARCH_ARM_SRC_LPC2378_INTERNAL_H
#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_H
#define __ARCH_ARM_SRC_LPC2378_LPC23XX_H
/****************************************************************************************************
* Included Files
@@ -67,4 +67,4 @@ void lpc2378_statledon(void);
#endif
#endif /* _ARCH_ARM_SRC_LPC2378_INTERNAL_H */
#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_H */
arch/arm/src/lpc2378/lpc23xx_gpio.h
+3 -3
View File
@@ -38,8 +38,8 @@
*
************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
#define _ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
#define __ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H
/************************************************************************************
* Included Files
@@ -68,4 +68,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H */
#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_GPIO_H */
arch/arm/src/lpc2378/lpc23xx_pinsel.h
+3 -3
View File
@@ -38,8 +38,8 @@
*
************************************************************************************/
#ifndef _ARCH_ARM_SRC_LPC23XX_PINSEL_H
#define _ARCH_ARM_SRC_LPC23XX_PINSEL_H
#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_PINSEL_H
#define __ARCH_ARM_SRC_LPC2378_LPC23XX_PINSEL_H
/************************************************************************************
* Included Files
@@ -789,4 +789,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* _ARCH_ARM_SRC_LPC23XX_PINSEL_H */
#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_PINSEL_H */
arch/arm/src/sam34/sam_gpio.c
+69 -2
View File
@@ -54,6 +54,7 @@
#include "chip.h"
#include "sam_gpio.h"
#include "sam_periphclks.h"
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
@@ -96,7 +97,7 @@ static inline uintptr_t sam_gpiobase(gpio_pinset_t cfgset)
* Name: sam_gpiopin
*
* Description:
* Returun the base address of the GPIO register set
* Return the base address of the GPIO register set
*
****************************************************************************/
@@ -105,6 +106,66 @@ static inline int sam_gpiopin(gpio_pinset_t cfgset)
return 1 << ((cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT);
}
/****************************************************************************
* Name: sam_gpio_enableclk
*
* Description:
* Enable clocking on the PIO port. Port clocking is required in the
* following cases:
*
* - In order to read values in input pins from the port
* - If the port supports interrupting pins
* - If glitch filtering is enabled
* - If necessary to read the input value on an open drain output (this
* may be done in TWI logic to detect hangs on the I2C bus).
*
****************************************************************************/
static inline int sam_gpio_enableclk(gpio_pinset_t cfgset)
{
/* Enable the peripheral clock for the GPIO's port controller. */
switch (cfgset & GPIO_PORT_MASK)
{
case GPIO_PORT_PIOA:
sam_pioa_enableclk();
break;
case GPIO_PORT_PIOB:
sam_piob_enableclk();
break;
#ifdef GPIO_PORT_PIOC
case GPIO_PORT_PIOC:
sam_pioc_enableclk();
break;
#endif
#ifdef GPIO_PORT_PIOD
case GPIO_PORT_PIOD:
sam_piod_enableclk();
break;
#endif
#ifdef GPIO_PORT_PIOE
case GPIO_PORT_PIOE:
sam_pioe_enableclk();
break;
#endif
#ifdef GPIO_PORT_PIOF
case GPIO_PORT_PIOF:
sam_piof_enableclk();
break;
#endif
default:
return -EINVAL;
}
return OK;
}
/****************************************************************************
* Name: sam_configinput
*
@@ -171,6 +232,7 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
{
regval &= ~pin;
}
putreg32(regval, base + SAM_PIO_SCHMITT_OFFSET);
#endif
@@ -184,7 +246,12 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
* another, new API... perhaps sam_configfilter()
*/
return OK;
/* Enable the peripheral clock for the GPIO's port controller.
* A GPIO input value is only sampled if the peripheral clock for its
* controller is enabled.
*/
return sam_gpio_enableclk(cfgset);
}
/****************************************************************************
arch/arm/src/samv7/sam_spi.c
+5 -1
View File
@@ -1221,6 +1221,7 @@ static int spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
#ifdef CONFIG_SPI_HWFEATURES
static int spi_hwfeatures(struct spi_dev_s *dev, uint8_t features)
{
#ifdef CONFIG_SPI_CS_CONTROL
struct sam_spics_s *spics = (struct sam_spics_s *)dev;
struct sam_spidev_s *spi = spi_device(spics);
uint32_t regval;
@@ -1280,7 +1281,10 @@ static int spi_hwfeatures(struct spi_dev_s *dev, uint8_t features)
spi->escape_lastxfer = false;
}
return 0;
return ((features & ~HWFEAT_FORCE_CS_CONTROL_MASK) == 0) ? OK : -ENOSYS;
#else
return -ENOSYS;
#endif
}
#endif
arch/arm/src/stm32/Kconfig
+2
View File
@@ -1398,6 +1398,8 @@ config STM32_STM32F37XX
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
select STM32_HAVE_USART3
config STM32_STM32F40XX
arch/arm/src/stm32/chip/stm32f37xxx_syscfg.h
+1 -1
View File
@@ -113,7 +113,7 @@
#define SYSCFG_EXTICR_PORTC (2) /* 0010: PC[x] pin */
#define SYSCFG_EXTICR_PORTD (3) /* 0011: PD[x] pin */
#define SYSCFG_EXTICR_PORTE (4) /* 0100: Reserved */
#define SYSCFG_EXTICR_PORTE (5) /* 0101: PF[x] pin */
#define SYSCFG_EXTICR_PORTF (5) /* 0101: PF[x] pin */
#define SYSCFG_EXTICR_PORT_MASK (15)
#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
arch/arm/src/stm32/stm32_bbsram.c
+2 -2
View File
@@ -256,7 +256,7 @@ static void stm32_bbsram_semtake(FAR struct stm32_bbsram_s *priv)
static inline void stm32_bbsram_unlock(void)
{
(void)stm32_pwr_enablebkp(true);
stm32_pwr_enablebkp(true);
}
/****************************************************************************
@@ -276,7 +276,7 @@ static inline void stm32_bbsram_unlock(void)
static inline void stm32_bbsram_lock(void)
{
(void)stm32_pwr_enablebkp(false);
stm32_pwr_enablebkp(false);
}
/****************************************************************************
arch/arm/src/stm32/stm32_lse.c
+3 -20
View File
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_lse.c
*
* Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.orgr>
*
* Redistribution and use in source and binary forms, with or without
@@ -45,18 +45,6 @@
#include "stm32_rcc.h"
#include "stm32_waste.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -74,14 +62,12 @@
void stm32_rcc_enablelse(void)
{
bool bkpenabled;
/* The LSE is in the RTC domain and write access is denied to this domain
* after reset, you have to enable write access using DBP bit in the PWR CR
* register before to configuring the LSE.
*/
bkpenabled = stm32_pwr_enablebkp(true);
stm32_pwr_enablebkp(true);
#if defined(CONFIG_STM32_STM32L15XX)
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
@@ -115,8 +101,5 @@ void stm32_rcc_enablelse(void)
/* Disable backup domain access if it was disabled on entry */
if (!bkpenabled)
{
(void)stm32_pwr_enablebkp(false);
}
stm32_pwr_enablebkp(false);
}
arch/arm/src/stm32/stm32_pwr.c
+34 -12
View File
@@ -2,7 +2,7 @@
* arch/arm/src/stm32/stm32_pwr.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved.
* Authors: Uros Platise <uros.platise@isotel.eu>
* Gregory Nutt <gnutt@nuttx.org>
*
@@ -40,21 +40,19 @@
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "up_arch.h"
#include "stm32_pwr.h"
#if defined(CONFIG_STM32_PWR)
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Private Functions
************************************************************************************/
@@ -85,46 +83,70 @@ static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint1
* Enables access to the backup domain (RTC registers, RTC backup data registers
* and backup SRAM).
*
* NOTE: Reference counting is used in order to supported nested calls to this
* function. As a consequence, every call to stm32_pwr_enablebkp(true) must
* be followed by a matching call to stm32_pwr_enablebkp(false).
*
* Input Parameters:
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
* True: The backup domain was previously writable.
* None
*
************************************************************************************/
bool stm32_pwr_enablebkp(bool writable)
void stm32_pwr_enablebkp(bool writable)
{
static uint16_t writable_counter = 0;
irqstate_t flags;
uint16_t regval;
bool waswritable;
bool wait = false;
flags = enter_critical_section();
/* Get the current state of the STM32 PWR control register */
regval = stm32_pwr_getreg(STM32_PWR_CR_OFFSET);
waswritable = ((regval & PWR_CR_DBP) != 0);
if (writable)
{
DEBUGASSERT(writable_counter < UINT16_MAX);
writable_counter++;
}
else if (writable_counter > 0)
{
writable_counter--;
}
/* Enable or disable the ability to write */
if (waswritable && !writable)
if (waswritable && writable_counter == 0)
{
/* Disable backup domain access */
regval &= ~PWR_CR_DBP;
stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
}
else if (!waswritable && writable)
else if (!waswritable && writable_counter > 0)
{
/* Enable backup domain access */
regval |= PWR_CR_DBP;
stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
wait = true;
}
leave_critical_section(flags);
if (wait)
{
/* Enable does not happen right away */
up_udelay(4);
}
return waswritable;
}
/************************************************************************************
arch/arm/src/stm32/stm32_pwr.h
+6 -2
View File
@@ -73,15 +73,19 @@ extern "C"
* Enables access to the backup domain (RTC registers, RTC backup data registers
* and backup SRAM).
*
* NOTE: Reference counting is used in order to supported nested calls to this
* function. As a consequence, every call to stm32_pwr_enablebkp(true) must
* be followed by a matching call to stm32_pwr_enablebkp(false).
*
* Input Parameters:
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
* True: The backup domain was previously writable.
* None
*
************************************************************************************/
bool stm32_pwr_enablebkp(bool writable);
void stm32_pwr_enablebkp(bool writable);
/************************************************************************************
* Name: stm32_pwr_enablebreg
arch/arm/src/stm32/stm32_rcc.c
+2 -2
View File
@@ -128,7 +128,7 @@ static inline void rcc_resetbkp(void)
regval = getreg32(RTC_MAGIC_REG);
if (regval != RTC_MAGIC)
{
(void)stm32_pwr_enablebkp(true);
stm32_pwr_enablebkp(true);
/* We might be changing RTCSEL - to ensure such changes work, we must
* reset the backup domain (having backed up the RTC_MAGIC token)
@@ -137,7 +137,7 @@ static inline void rcc_resetbkp(void)
modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST);
modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0);
(void)stm32_pwr_enablebkp(false);
stm32_pwr_enablebkp(false);
}
}
#else
arch/arm/src/stm32/stm32_rtcc.c
+11 -11
View File
@@ -222,7 +222,7 @@ static void rtc_wprunlock(void)
* registers and backup SRAM).
*/
(void)stm32_pwr_enablebkp(true);
stm32_pwr_enablebkp(true);
/* The following steps are required to unlock the write protection on all the
* RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR).
@@ -261,7 +261,7 @@ static inline void rtc_wprlock(void)
* registers and backup SRAM).
*/
(void)stm32_pwr_enablebkp(false);
stm32_pwr_enablebkp(false);
}
/************************************************************************************
@@ -598,7 +598,7 @@ int up_rtc_initialize(void)
regval = getreg32(RTC_MAGIC_REG);
(void)stm32_pwr_enablebkp(true);
stm32_pwr_enablebkp(true);
if (regval != RTC_MAGIC)
{
@@ -673,7 +673,7 @@ int up_rtc_initialize(void)
}
}
(void)stm32_pwr_enablebkp(false);
stm32_pwr_enablebkp(false);
/* Loop, attempting to initialize/resume the RTC. This loop is necessary
* because it seems that occasionally it takes longer to initialize the RTC
@@ -724,11 +724,17 @@ int up_rtc_initialize(void)
* backup data registers and backup SRAM).
*/
(void)stm32_pwr_enablebkp(true);
stm32_pwr_enablebkp(true);
/* Remember that the RTC is initialized */
putreg32(RTC_MAGIC, RTC_MAGIC_REG);
/* Disable write access to the backup domain (RTC registers, RTC
* backup data registers and backup SRAM).
*/
stm32_pwr_enablebkp(false);
}
else
{
@@ -740,12 +746,6 @@ int up_rtc_initialize(void)
rtc_dumpregs("Did resume");
}
/* Disable write access to the backup domain (RTC registers, RTC backup
* data registers and backup SRAM).
*/
(void)stm32_pwr_enablebkp(false);
if (ret != OK && nretry > 0)
{
rtcinfo("setup/resume ran %d times and failed with %d\n",
arch/arm/src/stm32/stm32_rtcounter.c
+4 -4
View File
@@ -377,7 +377,7 @@ int up_rtc_initialize(void)
* registers and backup SRAM).
*/
(void)stm32_pwr_enablebkp(true);
stm32_pwr_enablebkp(true);
/* Set access to the peripheral, enable the backup domain (BKP) and the lower
* power external 32,768Hz (Low-Speed External, LSE) oscillator. Configure the
@@ -428,7 +428,7 @@ int up_rtc_initialize(void)
* registers and backup SRAM).
*/
(void)stm32_pwr_enablebkp(false);
stm32_pwr_enablebkp(false);
return OK;
}
@@ -605,7 +605,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
/* Enable write access to the backup domain */
flags = enter_critical_section();
(void)stm32_pwr_enablebkp(true);
stm32_pwr_enablebkp(true);
/* Then write the broken out values to the RTC counter and BKP overflow register
* (hi-res mode only)
@@ -625,7 +625,7 @@ int up_rtc_settime(FAR const struct timespec *tp)
putreg16(regvals.ovf, RTC_TIMEMSB_REG);
#endif
(void)stm32_pwr_enablebkp(false);
stm32_pwr_enablebkp(false);
leave_critical_section(flags);
return OK;
}

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