arch/risc-v/mpfs: Enable caches by default on E51 core

E51 needs to use vendor specific CSR to enable L1 cache.

This adds the relevant register setting and makes it
configurable by CONFIG_MPFS_E51_ENABLE_CACHE. With this flag set, the L2
cache on E51 depends on the cache lane configuration. Disabling this flag
disables all caches on E51.

Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>

arch/risc-v/src/mpfs/Kconfig

@@ -195,6 +195,12 @@ config MPFS_DDR_MANUAL_ADDCMD_TRAINING
 	---help---
 		This adds code for manual addcmd training. To use it also enable bit 1 in LIBERO_SETTING_TRAINING_SKIP_SETTING to skip the automatic one
 
+config MPFS_E51_ENABLE_CACHE
+	bool "Enable L1 cache on E51 core"
+	default y
+	---help---
+		Enables L1 cache for E51 core. Note: if this is disabled, also L2 cache won't work on E51, regardless of cache lane configuration.
+
 config MPFS_ENABLE_CACHE
 	bool "Enable L2 cache"
 	depends on MPFS_BOOTLOADER

arch/risc-v/src/mpfs/mpfs_head.S

@@ -32,6 +32,7 @@
 #include "mpfs_memorymap.h"
 #include "riscv_internal.h"
 #include "riscv_macros.S"
+#include "mpfs_e51_csr.h"
 
 /****************************************************************************
  * Public Symbols
@@ -108,6 +109,7 @@ __start:
   li   x31, 0
 
   /* Skip delegation register, mmu and floating point initializations if E51 */
+
   csrr a0, CSR_MHARTID
   beqz a0, .skip_e51
 
@@ -125,8 +127,22 @@ __start:
 
   sfence.vma x0, x0
 
+  /* Skip the following E51 specific settings for u54 */
+
+  beqz x0, .skip_u54
+
 .skip_e51:
 
+  /* Enable/disable L1 caches with vendor specific CSR on E51 */
+
+#ifdef CONFIG_MPFS_E51_ENABLE_CACHE
+  csrw CSR_E51_MCACHE_CTL, (E51_MCACHE_CTL_DCACHE_EN | E51_MCACHE_CTL_ICACHE_EN)
+#else
+  csrw CSR_E51_MCACHE_CTL, 0
+#endif
+
+.skip_u54:
+
 /* initialize global pointer, global data
  * The __global_pointer is allocated in the linker script.
  * It points to a location between _sdata and _edata as the offsets used in the gp are +/- 2k