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boards/xtensa/esp32s3: Fix esp32s3-devkitc:knsh
This defconfig uses the legacy bootloader (based on ESP-IDF's bootloader) and, due a recent update on SPI flash support, its initialization was missing data to be moved to the IRAM during the boot process. Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
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simbit18
parent
6fd0bd21be
commit
44867b80ae
@@ -105,7 +105,6 @@ SECTIONS
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_iram_text_start = ABSOLUTE(.);
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*(.iram1 .iram1.*)
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esp32s3_userspace.*(.literal .text .literal.* .text.*)
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*librtc.a:(.literal .text .literal.* .text.*)
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*libkarch.a:esp32s3_spiflash.*(.literal .text .literal.* .text.*)
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*libkarch.a:cache_hal.*(.literal .text .literal.* .text.*)
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@@ -115,6 +114,20 @@ SECTIONS
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*libkarch.a:xtensa_interruptcontext.*(.literal .text .literal.* .text.*)
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*libkarch.a:xtensa_testset.*(.literal .text .literal.* .text.*)
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*libkarch.a:esp_app_desc.*(.literal .text .literal.* .text.*)
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*libkarch.a:esp_spiflash.*(.literal .text .literal.* .text.*)
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*libkarch.a:esp_flash_api.*(.text .text.* .literal .literal.*)
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*libkarch.a:esp_flash_spi_init.*(.text .text.* .literal .literal.*)
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*libkarch.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*)
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*libkarch.a:spi_flash_encrypt_hal_iram.*(.text .text.* .literal .literal.*)
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*libkarch.a:spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*)
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*libkarch.a:spi_flash_chip*.*(.literal .literal.* .text .text.*)
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*libkarch.a:spi_flash_wrap.*(.literal .literal.* .text .text.*)
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*libkarch.a:spi_flash_os_func_noos.*(.literal .literal.* .text .text.*)
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*libkarch.a:spi_flash_os_func_app.*(.literal .literal.* .text .text.*)
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*libkarch.a:flash_brownout_hook.*(.literal .literal.* .text .text.*)
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*libkarch.a:esp_cache.*(.literal .literal.* .text .text.*)
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*libkarch.a:cache_utils.*(.literal .literal.* .text .text.*)
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*libkarch.a:memspi_host_driver.*(.literal .literal.* .text .text.*)
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*libsched.a:sched_suspendscheduler.*(.literal .text .literal.* .text.*)
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*libsched.a:sched_note.*(.literal .text .literal.* .text.*)
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@@ -209,12 +222,27 @@ SECTIONS
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KEEP (*(.jcr))
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*(.dram1 .dram1.*)
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*libphy.a:(.rodata .rodata.*)
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esp32s3_userspace.*(.rodata .rodata.*)
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*libkarch.a:esp32s3_spiflash.*(.rodata .rodata.*)
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*libkarch.a:xtensa_cpupause.*(.rodata .rodata.*)
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*libkarch.a:xtensa_copystate.*(.rodata .rodata.*)
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*libkarch.a:xtensa_interruptcontext.*(.rodata .rodata.*)
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*libkarch.a:xtensa_testset.*(.rodata .rodata.*)
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*libkarch.a:esp_spiflash.*(.rodata .rodata.*)
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*libkarch.a:esp_flash_api.*(.rodata .rodata.*)
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*libkarch.a:esp_flash_spi_init.*(.rodata .rodata.*)
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*libkarch.a:spi_flash_hal_iram.*(.rodata .rodata.*)
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*libkarch.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.*)
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*libkarch.a:spi_flash_hal_gpspi.*(.rodata .rodata.*)
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*libkarch.a:spi_flash_chip*.*(.rodata .rodata.*)
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*libkarch.a:spi_flash_wrap.*(.rodata .rodata.*)
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*libkarch.a:spi_flash_os_func_noos.*(.rodata .rodata.*)
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*libkarch.a:spi_flash_os_func_app.*(.rodata .rodata.*)
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*libkarch.a:flash_brownout_hook.*(.rodata .rodata.*)
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*libkarch.a:esp_cache.*(.rodata .rodata.*)
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*libkarch.a:cache_utils.*(.rodata .rodata.*)
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*libkarch.a:memspi_host_driver.*(.rodata .rodata.*)
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*libkarch.a:esp_mmu_map.*(.rodata .rodata.*)
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*libkarch.a:ext_mem_layout.*(.rodata .rodata.*)
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*libsched.a:sched_suspendscheduler.*(.rodata .rodata.*)
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*libsched.a:sched_thistask.*(.rodata .rodata.*)
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@@ -355,4 +383,25 @@ SECTIONS
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. = ALIGN(4);
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} >KDROM
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/*
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* This section holds RTC data that should have fixed addresses.
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* The data are not initialized at power-up and are retained during deep sleep.
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*/
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.rtc_reserved (NOLOAD):
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{
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. = ALIGN(4);
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_rtc_reserved_start = ABSOLUTE(.);
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/* New data can only be added here to ensure existing data are not moved.
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* Because data have adhered to the end of the segment and code is relied
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* on it.
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* >> put new data here <<
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*/
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*(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
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KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
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_rtc_reserved_end = ABSOLUTE(.);
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} > rtc_reserved_seg
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}
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@@ -73,6 +73,8 @@
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# define FLASH_SIZE 0x1000000
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#endif
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#define RESERVE_RTC_MEM 24
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MEMORY
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{
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metadata (RX) : org = 0x0, len = 0x30
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@@ -82,7 +84,7 @@ MEMORY
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/* Instruction RAM */
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UIRAM (RWX) : org = SRAM_IRAM_ORG, len = 16K
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KIRAM (RWX) : org = ORIGIN(UIRAM) + LENGTH(UIRAM), len = 48K
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KIRAM (RWX) : org = ORIGIN(UIRAM) + LENGTH(UIRAM), len = 64K
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/* Flash mapped instruction data. */
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@@ -115,5 +117,30 @@ MEMORY
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KDROM (R) : org = 0x3c000020, len = CONFIG_ESP32S3_KERNEL_IMAGE_SIZE - 0x20
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UDROM (R) : org = ORIGIN(KDROM) + LENGTH(KDROM) + ORIGIN(ROM), len = FLASH_SIZE - LENGTH(KDROM) - ORIGIN(ROM)
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}
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/* RTC fast memory (executable). Persists over deep sleep. */
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rtc_iram_seg(RWX) : org = 0x600fe000, len = 0x2000 - RESERVE_RTC_MEM
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/* RTC fast memory (same block as above), viewed from data bus */
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rtc_data_seg(RW) : org = 0x600fe000, len = 0x2000 - RESERVE_RTC_MEM
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/* We reduced the size of rtc_iram_seg by RESERVE_RTC_MEM value.
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* It reserves the amount of RTC fast memory that we use for this memory segment.
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* This segment is intended for keeping:
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* - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
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* - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
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* The aim of this is to keep data that will not be moved around and have a fixed address.
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*/
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rtc_reserved_seg(RW) : org = 0x600fe000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
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/* RTC slow memory (data accessible). Persists over deep sleep.
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* Start of RTC slow memory is reserved for ULP co-processor code + data,
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* if enabled.
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*/
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rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM,
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len = 0x2000 - CONFIG_ESP32S3_ULP_COPROC_RESERVE_MEM
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}
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