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Gregory Nutt
2017-02-27 06:25:31 -06:00
parent f97a99e051
commit 433ed93aa0
2 changed files with 5 additions and 0 deletions
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arch/arm/src/stm32/stm32_gpio.c
+1
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@@ -788,5 +788,6 @@ bool stm32_gpioread(uint32_t pinset)
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
} }
return 0; return 0;
} }
arch/arm/src/stm32/stm32_pwm.c
+4
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@@ -1139,6 +1139,8 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg)
pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
} }
/* REVISIT: CNT and ARR may be 32-bits wide */
pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n",
pwm_getreg(priv, STM32_GTIM_CCER_OFFSET), pwm_getreg(priv, STM32_GTIM_CCER_OFFSET),
pwm_getreg(priv, STM32_GTIM_CNT_OFFSET), pwm_getreg(priv, STM32_GTIM_CNT_OFFSET),
@@ -1152,6 +1154,8 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg)
pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET)); pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET));
} }
/* REVISIT: CCR1-CCR4 may be 32-bits wide */
if (priv->timid == 16 || priv->timid == 17) if (priv->timid == 16 || priv->timid == 17)
{ {
pwminfo(" CCR1: %04x\n", pwminfo(" CCR1: %04x\n",