From 433ed93aa027512da1593005bfa5b980f3862bcf Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 27 Feb 2017 06:25:31 -0600 Subject: [PATCH] Add some comments. --- arch/arm/src/stm32/stm32_gpio.c | 1 + arch/arm/src/stm32/stm32_pwm.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/stm32/stm32_gpio.c index 03c6544e2d6..9eb5fb9597b 100644 --- a/arch/arm/src/stm32/stm32_gpio.c +++ b/arch/arm/src/stm32/stm32_gpio.c @@ -788,5 +788,6 @@ bool stm32_gpioread(uint32_t pinset) pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } + return 0; } diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index 83a1a4cd7df..3aa5f698a39 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -1139,6 +1139,8 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg) pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); } + /* REVISIT: CNT and ARR may be 32-bits wide */ + pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", pwm_getreg(priv, STM32_GTIM_CCER_OFFSET), pwm_getreg(priv, STM32_GTIM_CNT_OFFSET), @@ -1152,6 +1154,8 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg) pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET)); } + /* REVISIT: CCR1-CCR4 may be 32-bits wide */ + if (priv->timid == 16 || priv->timid == 17) { pwminfo(" CCR1: %04x\n",