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stm32h7: support SDRAM via FMC peripherial (#459)
* stm32h7: Add support for SDRAM connected to FMC
* stm32h7: nxstyle fixes in stm32_fmc.h and stm32h7x3xx_rcc.{c,h}
This commit is contained in:
Andrey Zabolotnyi
committed by
GitHub
GitHub
parent
2991836ee8
commit
3ff956dc00
@@ -58,6 +58,12 @@
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# define getreg32(a) (*(volatile uint32_t *)(a))
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# define putreg32(v,a) (*(volatile uint32_t *)(a) = (v))
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/* Non-atomic, but more effective modification of registers */
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# define modreg8(v,m,a) putreg8((getreg8(a) & ~(m)) | ((v) & (m)), a)
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# define modreg16(v,m,a) putreg16((getreg16(a) & ~(m)) | ((v) & (m)), a)
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# define modreg32(v,m,a) putreg32((getreg32(a) & ~(m)) | ((v) & (m)), a)
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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@@ -289,9 +289,13 @@ config STM32H7_ETHMAC
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select ARCH_HAVE_PHY
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config STM32H7_FMC
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bool "FMC"
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default n
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depends on STM32H7_HAVE_FMC
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bool "FMC"
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default n
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depends on STM32H7_HAVE_FMC
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---help---
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Enable Flexible Memory Controller.
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To correctly configure FMC for your hardware, you will have to define
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a number of macros in your board.h file. See stm32_fmc.c for directions.
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config STM32H7_OTGFS
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bool "OTG FS"
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@@ -1187,14 +1191,6 @@ endif # STM32H7_RTC_LSECLOCK
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endmenu # RTC Configuration
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config STM32H7_EXTERNAL_RAM
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bool "External RAM on FMC"
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default n
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depends on STM32H7_FMC
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select ARCH_HAVE_HEAP2
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---help---
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In addition to internal SDRAM, external RAM may be available through the FMC.
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menu "QuadSPI Configuration"
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depends on STM32H7_QUADSPI
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -60,33 +60,57 @@
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#include "hardware/stm32_memorymap.h"
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#include "stm32_mpuinit.h"
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#include "stm32_dtcm.h"
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#include "stm32_fmc.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Internal SRAM is available in all members of the STM32 family. The
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* following definitions must be provided to specify the size and
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* location of internal(system) SRAM:
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/* At startup the kernel will invoke up_addregion() so that platform code
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* may register available memories for use as part of system heap.
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* The global configuration option CONFIG_MM_REGIONS defines the maximal
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* number of non-contiguous memory ranges that may be registered with the
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* system heap. You must make sure it is large enough to hold all memory
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* regions you intend to use.
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*
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* In addition to internal SRAM, external RAM may also be available through
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* the FMC. In order to use FMC RAM, the following additional things need
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* to be present in the NuttX configuration file:
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* The following memory types can be used for heap on STM32H7 platform:
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*
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* CONFIG_STM32H7_FMC=y : Enables the FMC
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* CONFIG_STM32H7_FMC_S[D]RAM=y : SRAM and/or SDRAM is available via the FMC.
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* Either of these autoselects
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* CONFIG_ARCH_HAVE_HEAP2 which is what we
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* are interested in here.
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* CONFIG_HEAP2_BASE : The base address of the external RAM in
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* the FMC address space
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* CONFIG_HEAP2_SIZE : The size of the external RAM in the FMC
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* address space
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* CONFIG_MM_REGIONS : Must be set to a large enough value to
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* include the FMC external RAM (as determined
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* by the rules provided below)
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* - AXI SRAM is a 512kb memory area. This will be automatically registered
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* with the system heap in up_allocate_heap, all the other memory
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* regions will be registered in up_addregion().
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* So, CONFIG_MM_REGIONS must be at least 1 to use AXI SRAM.
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*
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* CONFIG_STM32H7_DTCMEXCLUDE : Set to exclude the DTCM from heap
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* - Internal SRAM is available in all members of the STM32 family.
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* This is always registered with system heap.
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* There are two contiguous regions of internal SRAM:
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* SRAM1+SRAM2+SRAM3 and SRAM4 at a separate address.
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* So, add 2 more to CONFIG_MM_REGIONS.
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*
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* - Tightly Coupled Memory (TCM RAM), we can use Data TCM (DTCM) for system
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* heap. Note that DTCM has a number of limitations, for example DMA
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* transfers to/from DTCM are limited.
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* Define CONFIG_STM32H7_DTCMEXCLUDE to exclude the DTCM from heap.
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* +1 to CONFIG_MM_REGIONS if you want to use DTCM.
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*
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* - External SDRAM can be connected to the FMC peripherial. Initialization
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* of FMC is done as up_addregion() will invoke stm32_fmc_init().
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* Please read the comment in stm32_fmc.c how to initialize FMC
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* correctly.
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*
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* Then, up to two regions of SDRAM may be registered with the heap:
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*
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* - BOARD_SDRAM1_SIZE, if defined, declares the size of SDRAM
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* at address STM32_FMC_BANK5. +1 to CONFIG_MM_REGIONS.
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* - BOARD_SDRAM2_SIZE, if defined, declares the size of SDRAM
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* at address STM32_FMC_BANK6. +1 to CONFIG_MM_REGIONS.
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*
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* - Additionaly, you may use the following options to add one more region
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* of memory to system heap:
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*
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* - CONFIG_ARCH_HAVE_HEAP2=y
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* - CONFIG_HEAP2_BASE=base address of memory area.
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* - CONFIG_HEAP2_SIZE=size of memory area.
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* - +1 to CONFIG_MM_REGIONS
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*/
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/* Set the start and end of the SRAMs */
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@@ -114,28 +138,6 @@
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# undef HAVE_DTCM
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#endif
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/* There are <x> possible heap configurations:
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*
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* Configuration 1. System SRAM (only)
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* CONFIG_MM_REGIONS == 1
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* Configuration 2. System SRAM and SRAM123
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* CONFIG_MM_REGIONS == 2
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* Configuration 3. System SRAM and SRAM123 and DTCM
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* CONFIG_MM_REGIONS == 3
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* HAVE_DTCM defined
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* Configuration 4. System SRAM and SRAM123 and DTCM and SRAM4
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* CONFIG_MM_REGIONS == 4
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* HAVE_DTCM defined
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* Configuration 5. System SRAM and SRAM123 and DTCM and SRAM4 and FMC RAM
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* CONFIG_MM_REGIONS == 5
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* HAVE_DTCM defined
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*
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* TODO ....
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*
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* Let's make sure that all definitions are consistent before doing
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* anything else
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*/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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@@ -204,7 +206,8 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
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* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
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*/
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uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
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uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
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CONFIG_MM_KERNEL_HEAPSIZE;
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size_t usize = SRAM123_END - ubase;
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int log2;
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@@ -246,6 +249,10 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
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up_heap_color(*heap_start, *heap_size);
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#endif
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/* Display memory ranges to help debugging */
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minfo("%uKb of SRAM at %p\n", *heap_size / 1024, *heap_start);
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}
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/****************************************************************************
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@@ -266,7 +273,8 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
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* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
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*/
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uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
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uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
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CONFIG_MM_KERNEL_HEAPSIZE;
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size_t usize = SRAM123_END - ubase;
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int log2;
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@@ -292,6 +300,38 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
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}
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#endif
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/****************************************************************************
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* Name: addregion
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*
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* Description:
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* Make a range of memory available for allocation from system heap.
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* If debug is disabled, compiler should optimize out the "desc" strings.
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*
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****************************************************************************/
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static void addregion (uintptr_t start, uint32_t size, const char *desc)
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{
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/* Display memory ranges to help debugging */
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minfo("%uKb of %s at %p\n", size / 1024, desc, (FAR void *)start);
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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/* Allow user-mode access to the SRAM123 heap */
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stm32_mpu_uheap(start, size);
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#endif
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/* Colorize the heap for debug */
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up_heap_color((FAR void *)start, size);
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/* Add the SRAM123 user heap region. */
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kumm_addregion((FAR void *)start, size);
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}
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/****************************************************************************
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* Name: up_addregion
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*
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@@ -301,81 +341,51 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
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*
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****************************************************************************/
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#if CONFIG_MM_REGIONS > 1
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void up_addregion(void)
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{
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# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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addregion (SRAM123_START, SRAM123_END - SRAM123_START, "SRAM1,2,3");
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/* Allow user-mode access to the SRAM123 heap */
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unsigned mm_regions = 1;
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stm32_mpu_uheap((uintptr_t)SRAM123_START, SRAM123_END - SRAM123_START);
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if (mm_regions < CONFIG_MM_REGIONS)
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{
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addregion (SRAM4_START, SRAM4_END - SRAM4_START, "SRAM4");
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mm_regions++;
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}
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# endif
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/* Colorize the heap for debug */
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up_heap_color((FAR void *)SRAM123_START, SRAM123_END - SRAM123_START);
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/* Add the SRAM123 user heap region. */
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kumm_addregion((FAR void *)SRAM123_START, SRAM123_END - SRAM123_START);
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# if CONFIG_MM_REGIONS > 2
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# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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/* Allow user-mode access to the SRAM4 user heap memory */
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stm32_mpu_uheap((uintptr_t)SRAM4_START, SRAM4_END - SRAM4_START);
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# endif
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/* Colorize the heap for debug */
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up_heap_color((FAR void *)SRAM4_START, SRAM4_END - SRAM4_START);
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/* Add the external SRAM4 user heap region. */
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kumm_addregion((FAR void *)SRAM4_START, SRAM4_END - SRAM4_START);
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# endif
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# if CONFIG_MM_REGIONS > 3
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# ifdef HAVE_DTCM
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# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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/* Allow user-mode access to the DTCM heap */
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stm32_mpu_uheap((uintptr_t)DTCM_START, DTCM_END - DTCM_START);
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# endif
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/* Colorize the heap for debug */
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up_heap_color((FAR void *)DTCM_START, DTCM_END - DTCM_START);
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/* Add the DTCM user heap region. */
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kumm_addregion((FAR void *)DTCM_START, DTCM_END - DTCM_START);
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# endif
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# endif
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# if CONFIG_MM_REGIONS > 4
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# ifdef CONFIG_ARCH_HAVE_HEAP2
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# if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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/* Allow user-mode access to the FMC RAM user heap memory */
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stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
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# endif
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/* Colorize the heap for debug */
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up_heap_color((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
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/* Add the external FMC RAM user heap region. */
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kumm_addregion((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
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# endif
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# endif
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}
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#ifdef HAVE_DTCM
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if (mm_regions < CONFIG_MM_REGIONS)
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{
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addregion (DTCM_START, DTCM_END - DTCM_START, "DTCM");
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mm_regions++;
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}
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#endif
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#ifdef CONFIG_STM32H7_FMC
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stm32_fmc_init();
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#endif
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#ifdef BOARD_SDRAM1_SIZE
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if (mm_regions < CONFIG_MM_REGIONS)
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{
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addregion (STM32_FMC_BANK5, BOARD_SDRAM1_SIZE, "SDRAM1");
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mm_regions++;
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}
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#endif
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#ifdef BOARD_SDRAM2_SIZE
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if (mm_regions < CONFIG_MM_REGIONS)
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{
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addregion (STM32_FMC_BANK6, BOARD_SDRAM2_SIZE, "SDRAM2");
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mm_regions++;
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}
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#endif
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#ifdef CONFIG_ARCH_HAVE_HEAP2
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if (mm_regions < CONFIG_MM_REGIONS)
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{
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addregion (CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE, "HEAP2");
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mm_regions++;
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}
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#endif
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}
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@@ -39,40 +39,410 @@
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#include <nuttx/config.h>
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#if defined(CONFIG_STM32H7_FMC)
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#include "stm32.h"
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#if defined(CONFIG_STM32H7_FMC)
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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/****************************************************************************
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* To use FMC, you must first enable it in configuration:
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*
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* CONFIG_STM32H7_FMC=y
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*
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* FMC is statically configured at startup. Its configuration is adjusted
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* using BOARD_XXX macros described below, which should be declared
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* in your board.h file.
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*
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* The BOARD_FMC_CLK macro can be defined to select the clock source for FMC.
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* This can be one of RCC_D1CCIPR_FMCSEL_xxx macros, and defaults to
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* RCC_D1CCIPR_FMCSEL_PLL2 (which means PLL2R).
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*
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*
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* To correctly initialize GPIO pins the macro BOARD_FMC_GPIO_CONFIGS should
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* define a list of 32-bit GPIO configuration bitmasks. Example:
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*
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* #define BOARD_FMC_GPIO_CONFIGS GPIO_FMC_A0,GPIO_FMC_A1,\
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* GPIO_FMC_A2,...,GPIO_FMC_D0,...,GPIO_FMC_NBL0,...
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*
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*
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* For SRAM/NOR-Flash memories FMC defines 4 x 64Mb sub-banks at addresses
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* 0x60000000, 0x64000000, 0x68000000, 0x6C000000. The following macros
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* can be defined in board.h to initialize FMC for use with SRAM/NOR-Flash:
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*
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* *** CURRENTLY SRAM/NOR-FLASH SUPPORT IS NOT IMPLEMENTED ***
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*
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* BOARD_FMC_BCR[1..4] - Initial value for control registers
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* for subbanks 1-4.
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* BOARD_FMC_BTR[1..4] - Initial value for SRAM/NOR-Flash timing registers
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* for subbanks 1-4.
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* BOARD_FMC_BWTR[1..4] - Initial value for SRAM/NOR-Flash write timing
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* registers for subbanks 1-4.
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*
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*
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* For NAND flash memories FMC reserves 64Mb at 0x80000000. Define the
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* following macros in your board.h file to initialize FMC for this type
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* of memory:
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*
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* *** CURRENTLY NAND FLASH SUPPORT IS NOT IMPLEMENTED ***
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*
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* BOARD_FMC_PCR - Initial value for NAND flash control register.
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* BOARD_FMC_PMEM - Initial value for NAND flash common memory space timing
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* register.
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* BOARD_FMC_PATT - Initial value for NAND flash attribute memory space
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* timing register.
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*
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*
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* For SDRAM memory FMC reserves 2 x 256Mb address ranges at 0xC0000000
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* and 0xD0000000. Define the following macros to initialize FMC to work
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* with SDRAM:
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*
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* BOARD_FMC_SDCR[1..2] - Initial value for SDRAM control registers for SDRAM
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* bank 1-2. Note that some bits in SDCR1 influence both SDRAM banks and
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* are unused in SDCR2!
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* BOARD_FMC_SDTR[1..2] - Initial value for SDRAM timing registeres for SDRAM
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* bank 1-2. Note that some bits in SDTR1 influence both SDRAM banks and
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* are unused in SDTR2!
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* BOARD_FMC_SDRAM_REFR_PERIOD - The SDRAM refresh rate period in FMC clocks,
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* OR
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* BOARD_FMC_SDRAM_REFR_CYCLES and BOARD_FMC_SDRAM_REFR_PERIOD can be used to
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* automatically compute refresh counter using data from SDRAM datasheet
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* (cycles usually is 4096, 8192 and such, and typical period is 64 ms)
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* and knowing FMC clock frequency.
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* BOARD_FMC_SDRAM_AUTOREFRESH may be defined to a number between 1 and 16 to
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* issue given number of SDRAM auto-refresh cycles before using it. This
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* defaults to 3.
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*
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*
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* Special notes:
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* - FMC bank remapping (FMC_BCR_BMAP*) is not currently supported.
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*
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*
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* Here's a working example of a configured IS42S16320D SDRAM on a particular
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* board:
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*
|
||||
*#define BOARD_SDRAM1_SIZE (64*1024*1024)
|
||||
*
|
||||
*#define BOARD_FMC_SDCR1 \
|
||||
* (FMC_SDCR_COLBITS_10 | FMC_SDCR_ROWBITS_13 | FMC_SDCR_WIDTH_16 |\
|
||||
* FMC_SDCR_BANKS_4 | FMC_SDCR_CASLAT_2 | FMC_SDCR_SDCLK_2X |\
|
||||
* FMC_SDCR_BURST_READ | FMC_SDCR_RPIPE_1)
|
||||
*#define BOARD_FMC_SDTR1 \
|
||||
* (FMC_SDTR_TMRD(2) | FMC_SDTR_TXSR(7) | FMC_SDTR_TRAS(4) | \
|
||||
* FMC_SDTR_TRC(7) | FMC_SDTR_TWR(4) | FMC_SDTR_TRP(2) | \
|
||||
* FMC_SDTR_TRCD(2))
|
||||
*#define BOARD_FMC_SDRAM_REFR_CYCLES 8192
|
||||
*#define BOARD_FMC_SDRAM_REFR_PERIOD 64
|
||||
*#define BOARD_FMC_SDRAM_MODE \
|
||||
* FMC_SDCMR_MRD_BURST_LENGTH_8 | \
|
||||
* FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL | \
|
||||
* FMC_SDCMR_MRD_CAS_LATENCY_2
|
||||
*
|
||||
*#define BOARD_FMC_GPIO_CONFIGS \
|
||||
* GPIO_FMC_A0,GPIO_FMC_A1,GPIO_FMC_A2,GPIO_FMC_A3,GPIO_FMC_A4,\
|
||||
* GPIO_FMC_A5,GPIO_FMC_A6,GPIO_FMC_A7,GPIO_FMC_A8,GPIO_FMC_A9,\
|
||||
* GPIO_FMC_A10,GPIO_FMC_A11,GPIO_FMC_A12,\
|
||||
* GPIO_FMC_D0,GPIO_FMC_D1,GPIO_FMC_D2,GPIO_FMC_D3,GPIO_FMC_D4,\
|
||||
* GPIO_FMC_D5,GPIO_FMC_D6,GPIO_FMC_D7,GPIO_FMC_D8,GPIO_FMC_D9,\
|
||||
* GPIO_FMC_D10,GPIO_FMC_D11,GPIO_FMC_D12,GPIO_FMC_D13,\
|
||||
* GPIO_FMC_D14,GPIO_FMC_D15,\
|
||||
* GPIO_FMC_NBL0,GPIO_FMC_NBL1,GPIO_FMC_BA0,GPIO_FMC_BA1,\
|
||||
* GPIO_FMC_SDNWE_2,GPIO_FMC_SDNCAS,GPIO_FMC_SDNRAS,\
|
||||
* GPIO_FMC_SDNE0_1,GPIO_FMC_SDCKE0_1,GPIO_FMC_SDCLK
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef BOARD_FMC_CLK
|
||||
/* Clock FMC from PLL2R by default */
|
||||
|
||||
# define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_PLL2
|
||||
#endif
|
||||
|
||||
/* A couple of macros to know if user uses SDRAM1 and/or SDRAM2 */
|
||||
|
||||
#if defined BOARD_FMC_SDCR1 && ((BOARD_FMC_SDCR1 & FMC_SDCR_CASLAT_MASK) != 0)
|
||||
# define HAVE_FMC_SDRAM1 1
|
||||
#endif
|
||||
#if defined BOARD_FMC_SDCR2 && ((BOARD_FMC_SDCR2 & FMC_SDCR_CASLAT_MASK) != 0)
|
||||
# define HAVE_FMC_SDRAM2 1
|
||||
#endif
|
||||
|
||||
#if defined HAVE_FMC_SDRAM1 || defined HAVE_FMC_SDRAM2
|
||||
# define HAVE_FMC_SDRAM 1
|
||||
#endif
|
||||
|
||||
/* Number of auto-refresh cycles to issue at SDRAM initialization */
|
||||
|
||||
#ifndef BOARD_FMC_SDRAM_AUTOREFRESH
|
||||
# define BOARD_FMC_SDRAM_AUTOREFRESH 3
|
||||
#endif
|
||||
|
||||
/* Find out the clock frequency for FMC */
|
||||
|
||||
#if BOARD_FMC_CLK == RCC_D1CCIPR_FMCSEL_HCLK
|
||||
# define FMC_CLK_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#elif BOARD_FMC_CLK == RCC_D1CCIPR_FMCSEL_PLL1
|
||||
# define FMC_CLK_FREQUENCY STM32_PLL1Q_FREQUENCY
|
||||
#elif BOARD_FMC_CLK == RCC_D1CCIPR_FMCSEL_PLL2
|
||||
# define FMC_CLK_FREQUENCY STM32_PLL2R_FREQUENCY
|
||||
#elif BOARD_FMC_CLK == RCC_D1CCIPR_FMCSEL_PER
|
||||
# define FMC_CLK_FREQUENCY STM32_PER_FREQUENCY
|
||||
#else
|
||||
# error "BOARD_FMC_CLK has unknown value!"
|
||||
#endif
|
||||
|
||||
/* Compute the refresh rate in clocks */
|
||||
|
||||
#ifndef BOARD_FMC_SDRAM_REFR_PERIOD
|
||||
|
||||
# if !defined(BOARD_FMC_SDRAM_REFR_CYCLES) || !defined(BOARD_FMC_SDRAM_REFR_PERIOD)
|
||||
# error "Both BOARD_FMC_SDRAM_REFR_CYCLES and BOARD_FMC_SDRAM_REFR_PERIOD have to be defined to compute BOARD_FMC_SDRAM_REFR_PERIOD!"
|
||||
# else
|
||||
/* Take care not to overflow on 32-bit arithmetic */
|
||||
|
||||
# define BOARD_FMC_SDRAM_REFR_PERIOD ((uint32_t)((uint64_t)BOARD_FMC_SDRAM_REFR_PERIOD * FMC_CLK_FREQUENCY / BOARD_FMC_SDRAM_REFR_CYCLES - 20))
|
||||
# endif
|
||||
|
||||
#endif /* BOARD_FMC_SDRAM_REFR_PERIOD */
|
||||
|
||||
/* The bits in FMC_SDCR we will alter at initialization */
|
||||
|
||||
#define FMC_SDCR_MASK (FMC_SDCR_COLBITS_MASK | FMC_SDCR_ROWBITS_MASK | \
|
||||
FMC_SDCR_WIDTH_MASK | FMC_SDCR_BANKS_MASK | FMC_SDCR_CASLAT_MASK | FMC_SDCR_WP | \
|
||||
FMC_SDCR_SDCLK_MASK | FMC_SDCR_BURST_READ | FMC_SDCR_RPIPE_MASK)
|
||||
|
||||
/* The bits in FMC_SDTR we will alter at initialization */
|
||||
|
||||
#define FMC_SDTR_MASK (FMC_SDTR_TMRD_MASK | FMC_SDTR_TXSR_MASK | \
|
||||
FMC_SDTR_TRAS_MASK | FMC_SDTR_TRC_MASK | FMC_SDTR_TWR_MASK | FMC_SDTR_TRP_MASK | \
|
||||
FMC_SDTR_TRCD_MASK)
|
||||
|
||||
/* The timeout while waiting for SDRAM controller to initialize, in us */
|
||||
|
||||
#define SDRAM_INIT_TIMEOUT (1000)
|
||||
|
||||
/****************************************************************************
|
||||
* Private data
|
||||
****************************************************************************/
|
||||
|
||||
static uint32_t fmc_gpios[] =
|
||||
{
|
||||
BOARD_FMC_GPIO_CONFIGS
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
static void stm32_fmc_sdram_init(void);
|
||||
static int stm32_fmc_sdram_wait(unsigned timeout);
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_enable
|
||||
* Name: stm32_fmc_init
|
||||
*
|
||||
* Description:
|
||||
* Enable clocking to the FMC.
|
||||
* Initialize the FMC peripherial. Because FMC initialization is highly
|
||||
* dependent on the used parts, definition of the initial values for FMC
|
||||
* registers is mostly left to board designer.
|
||||
*
|
||||
* Typically called from up_addregion().
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_enable_clk(void)
|
||||
void stm32_fmc_init(void)
|
||||
{
|
||||
modifyreg32(STM32_RCC_AHB3ENR, 0, RCC_AHB3ENR_FMCEN);
|
||||
uint32_t regval;
|
||||
|
||||
/* Reset the FMC on the AHB3 bus */
|
||||
|
||||
regval = getreg32(STM32_RCC_AHB3RSTR);
|
||||
regval |= RCC_AHB3RSTR_FMCRST;
|
||||
putreg32(regval, STM32_RCC_AHB3RSTR);
|
||||
|
||||
/* Leave reset state */
|
||||
|
||||
regval &= ~RCC_AHB3RSTR_FMCRST;
|
||||
putreg32(regval, STM32_RCC_AHB3RSTR);
|
||||
|
||||
/* Set FMC clocking */
|
||||
|
||||
modreg32 (BOARD_FMC_CLK, RCC_D1CCIPR_FMCSEL_MASK, STM32_RCC_D1CCIPR);
|
||||
|
||||
/* Set up FMC GPIOs */
|
||||
|
||||
for (regval = 0; regval < ARRAY_SIZE(fmc_gpios); regval++)
|
||||
stm32_configgpio(fmc_gpios[regval]);
|
||||
|
||||
/* Set up FMC registers */
|
||||
|
||||
#ifdef BOARD_FMC_SDCR1
|
||||
modreg32(BOARD_FMC_SDCR1, FMC_SDCR_MASK, STM32_FMC_SDCR1);
|
||||
#endif
|
||||
#ifdef BOARD_FMC_SDCR2
|
||||
modreg32(BOARD_FMC_SDCR2, FMC_SDCR_MASK, STM32_FMC_SDCR2);
|
||||
#endif
|
||||
|
||||
#ifdef BOARD_FMC_SDTR1
|
||||
modreg32(BOARD_FMC_SDTR1, FMC_SDTR_MASK, STM32_FMC_SDTR1);
|
||||
#endif
|
||||
#ifdef BOARD_FMC_SDTR2
|
||||
modreg32(BOARD_FMC_SDTR2, FMC_SDTR_MASK, STM32_FMC_SDTR2);
|
||||
#endif
|
||||
|
||||
/* Enable the FMC peripherial */
|
||||
|
||||
modreg32(FMC_BCR_FMCEN, FMC_BCR_FMCEN, STM32_FMC_BCR1);
|
||||
|
||||
/* Initialize the SDRAM chips themselves */
|
||||
|
||||
#ifdef HAVE_FMC_SDRAM
|
||||
stm32_fmc_sdram_init();
|
||||
#endif
|
||||
|
||||
/* Set up SDRAM refresh timings */
|
||||
|
||||
#ifdef BOARD_FMC_SDRAM_REFR_PERIOD
|
||||
/* ... The programmed COUNT value must not be equal to the sum of the
|
||||
* following timings: TWR+TRP+TRC+TRCD+4 memory clock cycles
|
||||
*/
|
||||
|
||||
#ifdef BOARD_FMC_SDTR1
|
||||
DEBUGASSERT (BOARD_FMC_SDRAM_REFR_PERIOD !=
|
||||
(4 +
|
||||
(1 + ((BOARD_FMC_SDTR1 & FMC_SDTR_TWR_MASK) >> FMC_SDTR_TWR_SHIFT)) +
|
||||
(1 + ((BOARD_FMC_SDTR1 & FMC_SDTR_TRP_MASK) >> FMC_SDTR_TRP_SHIFT)) +
|
||||
(1 + ((BOARD_FMC_SDTR1 & FMC_SDTR_TRC_MASK) >> FMC_SDTR_TRC_SHIFT)) +
|
||||
(1 + ((BOARD_FMC_SDTR1 & FMC_SDTR_TRCD_MASK) >> FMC_SDTR_TRCD_SHIFT))));
|
||||
#endif
|
||||
#ifdef BOARD_FMC_SDTR2
|
||||
DEBUGASSERT (BOARD_FMC_SDRAM_REFR_PERIOD !=
|
||||
(4 +
|
||||
(1 + ((BOARD_FMC_SDTR2 & FMC_SDTR_TWR_MASK) >> FMC_SDTR_TWR_SHIFT)) +
|
||||
(1 + ((BOARD_FMC_SDTR2 & FMC_SDTR_TRP_MASK) >> FMC_SDTR_TRP_SHIFT)) +
|
||||
(1 + ((BOARD_FMC_SDTR2 & FMC_SDTR_TRC_MASK) >> FMC_SDTR_TRC_SHIFT)) +
|
||||
(1 + ((BOARD_FMC_SDTR2 & FMC_SDTR_TRCD_MASK) >> FMC_SDTR_TRCD_SHIFT))));
|
||||
#endif
|
||||
|
||||
stm32_fmc_sdram_set_refresh_rate(BOARD_FMC_SDRAM_REFR_PERIOD);
|
||||
#endif /* BOARD_FMC_SDRTR */
|
||||
}
|
||||
|
||||
#ifdef HAVE_FMC_SDRAM
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_init
|
||||
*
|
||||
* Description:
|
||||
* Initialize the SDRAM chips.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined HAVE_FMC_SDRAM1 && defined HAVE_FMC_SDRAM2
|
||||
# define FMC_SDCMR_CTB FMC_SDCMR_CTB1 | FMC_SDCMR_CTB2
|
||||
#elif defined HAVE_FMC_SDRAM1
|
||||
# define FMC_SDCMR_CTB FMC_SDCMR_CTB1
|
||||
#else
|
||||
# define FMC_SDCMR_CTB FMC_SDCMR_CTB2
|
||||
#endif
|
||||
|
||||
void stm32_fmc_sdram_init(void)
|
||||
{
|
||||
/* What is happening here:
|
||||
* ... A 100μs delay is required prior to issuing any command [...]
|
||||
* a PRECHARGE command should be applied once the 100μs delay has been
|
||||
* satisfied.
|
||||
*
|
||||
* All banks must be precharged. This will leave all banks in an idle
|
||||
* state after which at least two AUTO REFRESH cycles must be performed.
|
||||
* After the AUTO REFRESH cycles are complete, the SDRAM is then ready
|
||||
* for mode register programming.
|
||||
*
|
||||
* The mode register should be loaded prior to applying any operational
|
||||
* command because it will power up in an unknown state.
|
||||
*/
|
||||
|
||||
up_udelay(100);
|
||||
|
||||
/* Clock Configuration Enable */
|
||||
|
||||
stm32_fmc_sdram_command(FMC_SDCMR_CTB | FMC_SDCMR_MODE_CLK_ENABLE);
|
||||
|
||||
/* Wait for clock to stabilize */
|
||||
|
||||
up_mdelay(1);
|
||||
|
||||
/* Precharge all banks */
|
||||
|
||||
stm32_fmc_sdram_wait(SDRAM_INIT_TIMEOUT);
|
||||
stm32_fmc_sdram_command(FMC_SDCMR_CTB | FMC_SDCMR_MODE_PALL);
|
||||
|
||||
/* Auto refresh */
|
||||
|
||||
stm32_fmc_sdram_wait(SDRAM_INIT_TIMEOUT);
|
||||
stm32_fmc_sdram_command(FMC_SDCMR_CTB | FMC_SDCMR_MODE_AUTO_REFRESH |
|
||||
FMC_SDCMR_NRFS(BOARD_FMC_SDRAM_AUTOREFRESH));
|
||||
|
||||
/* Program the SDRAM mode register */
|
||||
|
||||
/* If using two SDRAM chips, this will write same mode for both.
|
||||
* If different mode is required for every chip (why?), it would be
|
||||
* needed to split code into two separate LOAD_MODE commands,
|
||||
* one for every SDRAM chip.
|
||||
*/
|
||||
|
||||
stm32_fmc_sdram_wait(SDRAM_INIT_TIMEOUT);
|
||||
stm32_fmc_sdram_command(FMC_SDCMR_CTB | FMC_SDCMR_MODE_LOAD_MODE |
|
||||
BOARD_FMC_SDRAM_MODE);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_disable
|
||||
* Name: stm32_fmc_sdram_wait
|
||||
*
|
||||
* Description:
|
||||
* Disable clocking to the FMC.
|
||||
* Wait until SDRAM controller is ready for all configured SDRAM banks.
|
||||
*
|
||||
* Parameters:
|
||||
* timeout - number of microseconds before giving up waiting.
|
||||
*
|
||||
* Returns:
|
||||
* 0 if all configured SDRAM banks are ready, -1 on timeout
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_disable(void)
|
||||
int stm32_fmc_sdram_wait(unsigned timeout)
|
||||
{
|
||||
modifyreg32(STM32_RCC_AHB3ENR, RCC_AHB3ENR_FMCEN, 0);
|
||||
/* Wait until the SDRAM controller is ready */
|
||||
|
||||
for (; timeout; timeout--)
|
||||
{
|
||||
uint32_t sdsr = getreg32(STM32_FMC_SDSR);
|
||||
if (1
|
||||
#if defined HAVE_FMC_SDRAM1
|
||||
&& ((sdsr & FMC_SDSR_MODES1_MASK) == FMC_SDSR_MODES1_NORMAL)
|
||||
#endif
|
||||
#if defined HAVE_FMC_SDRAM2
|
||||
&& ((sdsr & FMC_SDSR_MODES2_MASK) == FMC_SDSR_MODES2_NORMAL)
|
||||
#endif
|
||||
)
|
||||
return 0;
|
||||
|
||||
up_udelay(1);
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_write_protect
|
||||
*
|
||||
@@ -92,11 +462,11 @@ void stm32_fmc_sdram_write_protect(int bank, bool state)
|
||||
val = getreg32(sdcr);
|
||||
if (state)
|
||||
{
|
||||
val |= FMC_SDRAM_CR_WRITE_PROTECT; /* wp == 1 */
|
||||
val |= FMC_SDCR_WP; /* wp == 1 */
|
||||
}
|
||||
else
|
||||
{
|
||||
val &= ~FMC_SDRAM_CR_WRITE_PROTECT; /* wp == 0 */
|
||||
val &= ~FMC_SDCR_WP; /* wp == 0 */
|
||||
}
|
||||
|
||||
putreg32(val, sdcr);
|
||||
@@ -112,10 +482,8 @@ void stm32_fmc_sdram_write_protect(int bank, bool state)
|
||||
|
||||
void stm32_fmc_sdram_set_refresh_rate(int count)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
DEBUGASSERT(count <= 0x1fff && count >= 0x29);
|
||||
putreg32(count << 1, STM32_FMC_SDRTR);
|
||||
putreg32(FMC_SDRTR_COUNT(count), STM32_FMC_SDRTR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -132,11 +500,11 @@ void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
|
||||
uint32_t sdtr;
|
||||
|
||||
DEBUGASSERT((bank == 1) || (bank == 2));
|
||||
DEBUGASSERT((timing & FMC_SDRAM_TR_RESERVED) == 0);
|
||||
DEBUGASSERT((timing & FMC_SDTR_RESERVED) == 0);
|
||||
|
||||
sdtr = (bank == 1) ? STM32_FMC_SDTR1 : STM32_FMC_SDTR2;
|
||||
val = getreg32(sdtr);
|
||||
val &= FMC_SDRAM_TR_RESERVED; /* preserve reserved bits */
|
||||
val &= FMC_SDTR_RESERVED; /* preserve reserved bits */
|
||||
val |= timing;
|
||||
putreg32(val, sdtr);
|
||||
}
|
||||
@@ -170,11 +538,11 @@ void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl)
|
||||
uint32_t sdcr;
|
||||
|
||||
DEBUGASSERT((bank == 1) || (bank == 2));
|
||||
DEBUGASSERT((ctrl & FMC_SDRAM_CR_RESERVED) == 0);
|
||||
DEBUGASSERT((ctrl & FMC_SDCR_RESERVED) == 0);
|
||||
|
||||
sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
|
||||
val = getreg32(sdcr);
|
||||
val &= FMC_SDRAM_CR_RESERVED; /* preserve reserved bits */
|
||||
val &= FMC_SDCR_RESERVED; /* preserve reserved bits */
|
||||
val |= ctrl;
|
||||
putreg32(val, sdcr);
|
||||
}
|
||||
@@ -189,7 +557,7 @@ void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl)
|
||||
|
||||
void stm32_fmc_sdram_command(uint32_t cmd)
|
||||
{
|
||||
DEBUGASSERT((cmd & FMC_SDRAM_CMD_RESERVED) == 0);
|
||||
DEBUGASSERT((cmd & FMC_SDCMR_RESERVED) == 0);
|
||||
putreg32(cmd, STM32_FMC_SDCMR);
|
||||
}
|
||||
|
||||
|
||||
@@ -45,10 +45,6 @@
|
||||
#include "chip.h"
|
||||
#include "hardware/stm32_fmc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
@@ -61,14 +57,22 @@ extern "C"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_wait
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_init
|
||||
*
|
||||
* Description:
|
||||
* Wait for the SDRAM controller to be ready.
|
||||
* Initialize the FMC peripherial. Because FMC initialization is highly
|
||||
* dependent on the used parts, definition of the initial values for FMC
|
||||
* registers is mostly left to board designer.
|
||||
*
|
||||
* Typically called from up_addregion().
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_sdram_wait(void);
|
||||
void stm32_fmc_init(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_enable
|
||||
|
||||
@@ -298,6 +298,12 @@ static inline void rcc_enableahb3(void)
|
||||
regval |= RCC_AHB3ENR_SDMMC1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_FMC
|
||||
/* Flexible static memory controller module clock enable */
|
||||
|
||||
regval |= RCC_AHB3ENR_FMCEN;
|
||||
#endif
|
||||
|
||||
/* TODO: ... */
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */
|
||||
@@ -775,7 +781,7 @@ static void stm32_stdclockconfig(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Ww must write the lower byte of the PWR_CR3 register is written once
|
||||
/* We must write the lower byte of the PWR_CR3 register is written once
|
||||
* after POR and it shall be written before changing VOS level or
|
||||
* ck_sys clock frequency. No limitation applies to the upper bytes.
|
||||
*
|
||||
|
||||
@@ -142,8 +142,8 @@ static inline void rcc_reset(void)
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
#if defined(CONFIG_STM32H7_AXI_SRAM_CORRUPTION_WAR)
|
||||
/* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to data
|
||||
* read corruption. See ES0392 Rev 6.
|
||||
/* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to
|
||||
* data read corruption. See ES0392 Rev 6.
|
||||
*/
|
||||
|
||||
putreg32(AXI_TARG_READ_ISS_OVERRIDE, STM32_AXI_TARG7_FN_MOD);
|
||||
@@ -298,6 +298,12 @@ static inline void rcc_enableahb3(void)
|
||||
regval |= RCC_AHB3ENR_SDMMC1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_FMC
|
||||
/* Flexible static memory controller module clock enable */
|
||||
|
||||
regval |= RCC_AHB3ENR_FMCEN;
|
||||
#endif
|
||||
|
||||
/* TODO: ... */
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */
|
||||
@@ -775,16 +781,16 @@ static void stm32_stdclockconfig(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Ww must write the lower byte of the PWR_CR3 register is written once
|
||||
* after POR and it shall be written before changing VOS level or ck_sys
|
||||
* clock frequency. No limitation applies to the upper bytes.
|
||||
/* We must write the lower byte of the PWR_CR3 register is written once
|
||||
* after POR and it shall be written before changing VOS level or
|
||||
* ck_sys clock frequency. No limitation applies to the upper bytes.
|
||||
*
|
||||
* Programming data corresponding to an invalid combination of
|
||||
* LDOEN and BYPASS bits will be ignored: data will not be written,
|
||||
* the written-once mechanism will lock the register and any further
|
||||
* write access will be ignored. The default supply configuration will
|
||||
* be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1)
|
||||
* will go on indicating invalid voltage levels.
|
||||
* be kept and the ACTVOSRDY bit in PWR control status register 1
|
||||
* (PWR_CSR1) will go on indicating invalid voltage levels.
|
||||
*
|
||||
* N.B. The system shall be power cycled before writing a new value.
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user