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bcm2711/spi: Create interrupt-based SPI driver.
This implements an interrupt-based SPI driver for the BCM2711 SPI interfaces (excluding auxiliary SPI interfaces). Only tested on SPI0 since proprietary firmware does not initialize any other SPI interfaces, and doing so will require reverse engineering.
This commit is contained in:
Matteo Golin
committed by
Alan C. Assis
Alan C. Assis
parent
7cb09d96e3
commit
3feb9985a5
@@ -4,6 +4,26 @@ Raspberry Pi 4B
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.. tags:: chip:bcm2711, experimental
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.. warning::
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The board support for this device is experimental. Not all features are
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implemented and they have not been extensively tested by many users.
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Help is wanted if you are interested in supporting a feature or if you've
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found an issue with any of the implementation! See :doc:`the contributing
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guidelines </contributing/index>`.
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.. warning::
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The SPI driver implemented for the :doc:`BCM2711 <../../index>` has only been
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tested on SPI0. It appears that even using the special `overlays
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<https://github.com/raspberrypi/linux/blob/stable/arch/arm/boot/dts/overlays/README>`_
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for the device tree passed to the proprietary firmware does not properly
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initialize the remaining SPI interfaces, and thus they have not been working
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properly. More effort is required to reverse engineer the magic incantations
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required to initialize these interfaces, at which point it is assumed that
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the driver implementation should extend to SPI3-6.
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The `Raspberry Pi 4B <https://www.raspberrypi.com/products/raspberry-pi-4-model-b/specifications/>`_ is an ARM64
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hobbyist board created by Raspberry Pi.
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@@ -139,17 +159,14 @@ Board Peripheral Support
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SMP is currently unsupported.
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To see support for general chip peripherals (I2C, SPI, UART, etc), see the
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:doc:`BCM2711 page <../../index>`
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NuttX for the Raspberry Pi 4 supports these on-board peripherals:
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======================== =======
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Peripheral Support
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======================== =======
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I2C Partial (able to read, that's it)
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UART Mini UART yes, PL011 no
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GPIO Partial
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PWM No
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SPI No
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PCM No
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AV port No
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HDMI No
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WiFi No
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@@ -2,12 +2,38 @@
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BCM2711
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=======
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The `BCM2711 <https://www.raspberrypi.com/documentation/computers/processors.html#bcm2711>`_ is a Broadcom SoC used for
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the Raspberry Pi 4B board.
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.. tags:: chip:bcm2711, experimental
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.. warning::
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The support for this chip is experimental. Not all features are
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implemented and they have not been extensively tested by many users.
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Help is wanted if you are interested in supporting a feature or if you've
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found an issue with any of the implementation! See :doc:`the contributing
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guidelines </contributing/index>`.
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The `BCM2711
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<https://www.raspberrypi.com/documentation/computers/processors.html#bcm2711>`_
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is a Broadcom SoC used for the Raspberry Pi 4B board.
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- **CPU:** Quad-core ARM Cortex-A72
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- **Interrupt Controller:** GIC400
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Supported Peripherals
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=====================
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======================== =======
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Peripheral Support
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======================== =======
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I2C Partial (able to read, that's it)
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UART Mini UART yes, PL011 no
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GPIO Partial
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PWM No
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SPI Interrupt-based driver (no DMA) for all SPI except 1 & 2 (auxiliary)
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PCM No
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======================== =======
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Supported Boards
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================
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@@ -20,8 +20,8 @@
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*
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****************************************************************************/
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#ifndef __ARCH_ARM64_SRC_BCM2711_IRQ_H
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#define __ARCH_ARM64_SRC_BCM2711_IRQ_H
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#ifndef __ARCH_ARM64_INCLUDE_BCM2711_IRQ_H
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#define __ARCH_ARM64_INCLUDE_BCM2711_IRQ_H
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/****************************************************************************
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* Pre-processor Definitions
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@@ -122,8 +122,6 @@
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#define BCM_IRQ_VC_EMMC BCM_IRQ_VC(62)
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#define BCM_IRQ_VC_ETHPCIESEC BCM_IRQ_VC(63)
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/* TODO: what about PACTL_CS address section 6.2.4? */
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/* ETH_PCIe interrupts */
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#define BCM_IRQ_ETH_BASE 160
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@@ -143,4 +141,4 @@
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#define BCM_IRQ_ARMLOCAL_IRQ_SOURCEN_MAILBOX_CORE3_IRQ (1 << 4)
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#define BCM_IRQ_ARMLOCAL_IRQ_SOURCEN_CNT_V_IRQ (1 << 3)
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#endif // __ARCH_ARM64_SRC_BCM2711_IRQ_H
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#endif // __ARCH_ARM64_INCLUDE_BCM2711_IRQ_H
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@@ -103,17 +103,92 @@ config BCM2711_SPI
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if BCM2711_SPI
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config BCM2711_SPI1
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bool "SPI1"
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config BCM2711_SPI0
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bool "SPI0"
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depends on BCM2711_SPI
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default n
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---help---
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Enable the SPI1 interface.
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Enable the SPI0 interface.
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if BCM2711_SPI0
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config BCM2711_SPI0_CE0
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int "CE0 GPIO"
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depends on BCM2711_SPI0
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default 8
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---help---
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The GPIO pin for the chip enable 0 signal (8, 36, 43)
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config BCM2711_SPI0_CE1
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int "CE1 GPIO"
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depends on BCM2711_SPI0
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default 7
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---help---
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The GPIO pin for the chip enable 1 signal (7, 35, 44)
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config BCM2711_SPI0_MISO
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int "MISO GPIO"
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depends on BCM2711_SPI0
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default 9
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---help---
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The GPIO pin for the MISO signal (9, 37, 40)
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config BCM2711_SPI0_MOSI
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int "MOSI GPIO"
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depends on BCM2711_SPI0
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default 10
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---help---
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The GPIO pin for the MOSI signal (10, 38, 41)
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config BCM2711_SPI0_SCLK
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int "SCLK GPIO"
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depends on BCM2711_SPI0
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default 11
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---help---
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The GPIO pin for the SCLK signal (11, 39, 42)
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endif
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config BCM2711_SPI1
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bool "SPI1"
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depends on BCM2711_SPI
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default n
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---help---
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Enable the SPI1 interface (auxiliary).
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config BCM2711_SPI2
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bool "SPI2"
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default n
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---help---
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Enable the SPI2 interface.
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Enable the SPI2 interface (auxiliary).
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config BCM2711_SPI3
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bool "SPI3"
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depends on BCM2711_SPI
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default n
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---help---
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Enable the SPI3 interface.
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config BCM2711_SPI4
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bool "SPI4"
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depends on BCM2711_SPI
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default n
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---help---
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Enable the SPI4 interface.
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config BCM2711_SPI5
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bool "SPI5"
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depends on BCM2711_SPI
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default n
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---help---
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Enable the SPI5 interface.
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config BCM2711_SPI6
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bool "SPI6"
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depends on BCM2711_SPI
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default n
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---help---
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Enable the SPI6 interface.
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endif # BCM2711_SPI
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@@ -327,22 +327,25 @@ void bcm2711_gpio_set_pulls(uint32_t gpio, bool up, bool down)
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if (gpio <= 15)
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{
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value = (direction << (gpio * 2));
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modreg32(value, value, BCM_GPIO_PUP_PDN_CNTRL_REG0);
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modreg32(value, (0x3 << (gpio * 2)), BCM_GPIO_PUP_PDN_CNTRL_REG0);
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}
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else if (gpio <= 31 && gpio > 15)
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{
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value = (direction << ((gpio - 16) * 2));
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modreg32(value, value, BCM_GPIO_PUP_PDN_CNTRL_REG1);
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modreg32(value, (0x3 << ((gpio - 16) * 2)),
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BCM_GPIO_PUP_PDN_CNTRL_REG1);
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}
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else if (gpio <= 47 && gpio > 31)
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{
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value = (direction << ((gpio - 32) * 2));
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modreg32(value, value, BCM_GPIO_PUP_PDN_CNTRL_REG2);
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modreg32(value, (0x3 << ((gpio - 32) * 2)),
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BCM_GPIO_PUP_PDN_CNTRL_REG2);
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}
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else if (gpio <= 57 && gpio > 47)
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{
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value = (direction << ((gpio - 48) * 2));
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modreg32(value, value, BCM_GPIO_PUP_PDN_CNTRL_REG3);
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modreg32(value, (0x3 << ((gpio - 48) * 2)),
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BCM_GPIO_PUP_PDN_CNTRL_REG3);
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}
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}
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File diff suppressed because it is too large
Load Diff
@@ -33,108 +33,6 @@
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* Pre-processor Definitions
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****************************************************************************/
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/* ARM_LOCAL interrupts */
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/* ARMC interrupts */
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#define BCM_IRQ_ARMC_TIMER 0 /* Timer */
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#define BCM_IRQ_ARMC_MAILBOX 1 /* Mailbox */
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#define BCM_IRQ_ARMC_DOORBELL0 2 /* Doorbell 0 */
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#define BCM_IRQ_ARMC_DOORBELL1 3 /* Doorbell 1 */
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#define BCM_IRQ_ARMC_VPU0HALT 4 /* VPU 0 halted */
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#define BCM_IRQ_ARMC_VPU1HALT 5 /* VPU 1 halted */
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#define BCM_IRQ_ARMC_ARMADDRERR 6 /* ARM address error */
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#define BCM_IRQ_ARMC_ARMAXIERR 7 /* ARM AXI error */
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#define BCM_IRQ_ARMC_SWI0 8 /* Software interrupt 0 */
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#define BCM_IRQ_ARMC_SWI1 9 /* Software interrupt 1 */
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#define BCM_IRQ_ARMC_SWI2 10 /* Software interrupt 2 */
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#define BCM_IRQ_ARMC_SWI3 11 /* Software interrupt 3 */
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#define BCM_IRQ_ARMC_SWI4 12 /* Software interrupt 4 */
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#define BCM_IRQ_ARMC_SWI5 13 /* Software interrupt 5 */
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#define BCM_IRQ_ARMC_SWI6 14 /* Software interrupt 6 */
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#define BCM_IRQ_ARMC_SWI7 15 /* Software interrupt 7 */
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/* VideoCore interrupts */
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#define BCM_IRQ_VC_TIMER0 0
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#define BCM_IRQ_VC_TIMER1 1
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#define BCM_IRQ_VC_TIMER2 2
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#define BCM_IRQ_VC_TIMER3 3
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#define BCM_IRQ_VC_H2640 4
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#define BCM_IRQ_VC_H2641 5
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#define BCM_IRQ_VC_H2642 6
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#define BCM_IRQ_VC_JPEG 7
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#define BCM_IRQ_VC_ISP 8
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#define BCM_IRQ_VC_USB 9
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#define BCM_IRQ_VC_V3D 10
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#define BCM_IRQ_VC_TRANSPOSE 11
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#define BCM_IRQ_VC_MCSYNC0 12
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#define BCM_IRQ_VC_MCSYNC1 13
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#define BCM_IRQ_VC_MCSYNC2 14
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#define BCM_IRQ_VC_MCSYNC3 15
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#define BCM_IRQ_VC_DMA0 16
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#define BCM_IRQ_VC_DMA1 17
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#define BCM_IRQ_VC_DMA2 18
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#define BCM_IRQ_VC_DMA3 19
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#define BCM_IRQ_VC_DMA4 20
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#define BCM_IRQ_VC_DMA5 21
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#define BCM_IRQ_VC_DMA6 22
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#define BCM_IRQ_VC_DMA7N8 23
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#define BCM_IRQ_VC_DMA9N10 24
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#define BCM_IRQ_VC_DMA11 25
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#define BCM_IRQ_VC_DMA12 26
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#define BCM_IRQ_VC_DMA13 27
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#define BCM_IRQ_VC_DMA14 28
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#define BCM_IRQ_VC_AUX 29
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#define BCM_IRQ_VC_ARM 30
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#define BCM_IRQ_VC_DMA15 31
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#define BCM_IRQ_VC_HDMICEC 32
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#define BCM_IRQ_VC_HVS 33
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#define BCM_IRQ_VC_RPIVID 34
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#define BCM_IRQ_VC_SDC 35
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#define BCM_IRQ_VC_DSI0 36
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#define BCM_IRQ_VC_PIXVLV2 37
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#define BCM_IRQ_VC_CAM0 38
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#define BCM_IRQ_VC_CAM1 39
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#define BCM_IRQ_VC_HDMI0 40
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#define BCM_IRQ_VC_HDMI1 41
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#define BCM_IRQ_VC_PIXVLV3 42
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#define BCM_IRQ_VC_SPIBSCSLV 43
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#define BCM_IRQ_VC_DSI1 44
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#define BCM_IRQ_VC_PXLVLV0 45
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#define BCM_IRQ_VC_PXLVLV1N4 46
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#define BCM_IRQ_VC_CPR 47
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#define BCM_IRQ_VC_SMI 48
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#define BCM_IRQ_VC_GPIO0 49
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#define BCM_IRQ_VC_GPIO1 50
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#define BCM_IRQ_VC_GPIO2 51
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#define BCM_IRQ_VC_GPIO3 52
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#define BCM_IRQ_VC_I2C 53
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#define BCM_IRQ_VC_SPI 54
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#define BCM_IRQ_VC_PCMI2S 55
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#define BCM_IRQ_VC_SDHOST 56
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#define BCM_IRQ_VC_PL011UART 57
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#define BCM_IRQ_VC_ETHPCIE 58
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#define BCM_IRQ_VC_VEC 59
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#define BCM_IRQ_VC_CPG 60
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#define BCM_IRQ_VC_RNG 61
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#define BCM_IRQ_VC_EMMC 62
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#define BCM_IRQ_VC_ETHPCIESEC 63
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/* TODO: what about PACTL_CS address section 6.2.4? */
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/* ETH_PCIe interrupts */
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#define BCM_IRQ_ETH_AVS 9
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#define BCM_IRQ_ETH_PCIE0_INTA 15
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#define BCM_IRQ_ETH_PCIE0_INTB 16
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#define BCM_IRQ_ETH_PCIE0_INTC 17
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#define BCM_IRQ_ETH_PCIE0_INTD 18
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#define BCM_IRQ_ETH_PCIE0_MSI 20
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#define BCM_IRQ_ETH_GENET0_A 29
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#define BCM_IRQ_ETH_GENET0_B 30
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#define BCM_IRQ_ETH_USB0_XHCI0 48
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/* ARM_LOCAL interrupt register offsets */
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#define BCM_IRQ_ARMLOCAL_ARM_CONTROL_OFFSET 0x00
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@@ -605,4 +503,29 @@
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#define BCM_IRQ_ARMC_SWIRQ_SET_SW_INT (0xff)
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#define BCM_IRQ_ARMC_SWIRQ_CLEAR_SW_INT (0xff)
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/* PACTL_CS register bit definitions */
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#define BCM_PACTL_CS_SPI0 (1 << 0)
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#define BCM_PACTL_CS_SPI1 (1 << 1)
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#define BCM_PACTL_CS_SPI2 (1 << 2)
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#define BCM_PACTL_CS_SPI3 (1 << 3)
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#define BCM_PACTL_CS_SPI4 (1 << 4)
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#define BCM_PACTL_CS_SPI5 (1 << 5)
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#define BCM_PACTL_CS_SPI6 (1 << 6)
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#define BCM_PACTL_CS_I2C0 (1 << 8)
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#define BCM_PACTL_CS_I2C1 (1 << 9)
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#define BCM_PACTL_CS_I2C2 (1 << 10)
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#define BCM_PACTL_CS_I2C3 (1 << 11)
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#define BCM_PACTL_CS_I2C4 (1 << 12)
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#define BCM_PACTL_CS_I2C5 (1 << 13)
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#define BCM_PACTL_CS_I2C6 (1 << 14)
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#define BCM_PACTL_CS_I2C7 (1 << 15)
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#define BCM_PACTL_CS_UART5 (1 << 16)
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#define BCM_PACTL_CS_UART4 (1 << 17)
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#define BCM_PACTL_CS_UART3 (1 << 18)
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#define BCM_PACTL_CS_UART2 (1 << 19)
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#define BCM_PACTL_CS_UART0 (1 << 20)
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#endif /* __ARCH_ARM64_SRC_BCM2711_IRQ_H */
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@@ -103,6 +103,10 @@
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#define BCM_DMA15_BASE \
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(BCM_PERIPHERAL_BASEADDR + 0x000e05000) /* DMA Channel 15 */
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/* PACTL register address */
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#define BCM_PACTL_CS (BCM_PERIPHERAL_BASEADDR + 0x204e00)
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/* ARM_LOCAL base address */
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#if defined(CONFIG_BCM2711_LOW_PERIPHERAL)
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@@ -44,40 +44,12 @@
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/* SPI register addresses */
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#define BCM_SPI0_CS (BCM_SPI0_BASEADDR + BCM_SPI_CS_OFFSET)
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#define BCM_SPI0_FIFO (BCM_SPI0_BASEADDR + BCM_SPI_FIFO_OFFSET)
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#define BCM_SPI0_CLK (BCM_SPI0_BASEADDR + BCM_SPI_CLK_OFFSET)
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#define BCM_SPI0_DLEN (BCM_SPI0_BASEADDR + BCM_SPI_DLEN_OFFSET)
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#define BCM_SPI0_LTOH (BCM_SPI0_BASEADDR + BCM_SPI_LTOH_OFFSET)
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#define BCM_SPI0_DC (BCM_SPI0_BASEADDR + BCM_SPI_DC_OFFSET)
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#define BCM_SPI3_CS (BCM_SPI3_BASEADDR + BCM_SPI_CS_OFFSET)
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#define BCM_SPI3_FIFO (BCM_SPI3_BASEADDR + BCM_SPI_FIFO_OFFSET)
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#define BCM_SPI3_CLK (BCM_SPI3_BASEADDR + BCM_SPI_CLK_OFFSET)
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#define BCM_SPI3_DLEN (BCM_SPI3_BASEADDR + BCM_SPI_DLEN_OFFSET)
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#define BCM_SPI3_LTOH (BCM_SPI3_BASEADDR + BCM_SPI_LTOH_OFFSET)
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#define BCM_SPI3_DC (BCM_SPI3_BASEADDR + BCM_SPI_DC_OFFSET)
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#define BCM_SPI4_CS (BCM_SPI4_BASEADDR + BCM_SPI_CS_OFFSET)
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#define BCM_SPI4_FIFO (BCM_SPI4_BASEADDR + BCM_SPI_FIFO_OFFSET)
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#define BCM_SPI4_CLK (BCM_SPI4_BASEADDR + BCM_SPI_CLK_OFFSET)
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#define BCM_SPI4_DLEN (BCM_SPI4_BASEADDR + BCM_SPI_DLEN_OFFSET)
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#define BCM_SPI4_LTOH (BCM_SPI4_BASEADDR + BCM_SPI_LTOH_OFFSET)
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#define BCM_SPI4_DC (BCM_SPI4_BASEADDR + BCM_SPI_DC_OFFSET)
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#define BCM_SPI5_CS (BCM_SPI5_BASEADDR + BCM_SPI_CS_OFFSET)
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#define BCM_SPI5_FIFO (BCM_SPI5_BASEADDR + BCM_SPI_FIFO_OFFSET)
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#define BCM_SPI5_CLK (BCM_SPI5_BASEADDR + BCM_SPI_CLK_OFFSET)
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#define BCM_SPI5_DLEN (BCM_SPI5_BASEADDR + BCM_SPI_DLEN_OFFSET)
|
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#define BCM_SPI5_LTOH (BCM_SPI5_BASEADDR + BCM_SPI_LTOH_OFFSET)
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#define BCM_SPI5_DC (BCM_SPI5_BASEADDR + BCM_SPI_DC_OFFSET)
|
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|
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#define BCM_SPI6_CS (BCM_SPI6_BASEADDR + BCM_SPI_CS_OFFSET)
|
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#define BCM_SPI6_FIFO (BCM_SPI6_BASEADDR + BCM_SPI_FIFO_OFFSET)
|
||||
#define BCM_SPI6_CLK (BCM_SPI6_BASEADDR + BCM_SPI_CLK_OFFSET)
|
||||
#define BCM_SPI6_DLEN (BCM_SPI6_BASEADDR + BCM_SPI_DLEN_OFFSET)
|
||||
#define BCM_SPI6_LTOH (BCM_SPI6_BASEADDR + BCM_SPI_LTOH_OFFSET)
|
||||
#define BCM_SPI6_DC (BCM_SPI6_BASEADDR + BCM_SPI_DC_OFFSET)
|
||||
#define BCM_SPI_CS(base) ((base) + BCM_SPI_CS_OFFSET)
|
||||
#define BCM_SPI_FIFO(base) ((base) + BCM_SPI_FIFO_OFFSET)
|
||||
#define BCM_SPI_CLK(base) ((base) + BCM_SPI_CLK_OFFSET)
|
||||
#define BCM_SPI_DLEN(base) ((base) + BCM_SPI_DLEN_OFFSET)
|
||||
#define BCM_SPI_LTOH(base) ((base) + BCM_SPI_LTOH_OFFSET)
|
||||
#define BCM_SPI_DC(base) ((base) + BCM_SPI_DC_OFFSET)
|
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|
||||
/* SPI register bit definitions */
|
||||
|
||||
@@ -123,4 +95,8 @@
|
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#define BCM_SPI_DC_TPANIC (0xff << 8)
|
||||
#define BCM_SPI_DC_TDREQ (0xff << 0)
|
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|
||||
/* Informational constants */
|
||||
|
||||
#define BCM_SPI_FIFO_DEPTH 16
|
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|
||||
#endif /* __ARCH_ARM64_SRC_BCM2711_SPI_H */
|
||||
|
||||
Reference in New Issue
Block a user