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Merge remote-tracking branch 'origin/master' into bas24

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This commit is contained in:
Gregory Nutt
2014-11-01 13:48:54 -06:00
parent fa6d130f95 cc679cc902
commit 3d34ce9266
34 changed files with 15263 additions and 16 deletions
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arch/arm/src/armv7-m/etm.h
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arch/arm/src/efm32/chip/efm32_acmp.h
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/*******************************************************************************************************************************
* arch/arm/src/efm32/chip/efm32_acmp.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Authors: Pierre-noel Bouteville <pnb990@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ACMP_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ACMP_H
/*******************************************************************************************************************************
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG)
# warning This is the EFM32GG header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* ACMP Register Offsets *******************************************************************************************************/
#define EFM32_ACMP_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_ACMP_INPUTSEL_OFFSET 0x0004 /* Input Selection Register */
#define EFM32_ACMP_STATUS_OFFSET 0x0008 /* Status Register */
#define EFM32_ACMP_IEN_OFFSET 0x000c /* Interrupt Enable Register */
#define EFM32_ACMP_IF_OFFSET 0x0010 /* Interrupt Flag Register */
#define EFM32_ACMP_IFS_OFFSET 0x0014 /* Interrupt Flag Set Register */
#define EFM32_ACMP_IFC_OFFSET 0x0018 /* Interrupt Flag Clear Register */
#define EFM32_ACMP_ROUTE_OFFSET 0x001c /* I/O Routing Register */
/* ACMP Register Addresses *****************************************************************************************************/
#define EFM32_ACMP0_CTRL (EFM32_ACMP0_BASE+EFM32_ACMP_CTRL_OFFSET)
#define EFM32_ACMP0_INPUTSEL (EFM32_ACMP0_BASE+EFM32_ACMP_INPUTSEL_OFFSET)
#define EFM32_ACMP0_STATUS (EFM32_ACMP0_BASE+EFM32_ACMP_STATUS_OFFSET)
#define EFM32_ACMP0_IEN (EFM32_ACMP0_BASE+EFM32_ACMP_IEN_OFFSET)
#define EFM32_ACMP0_IF (EFM32_ACMP0_BASE+EFM32_ACMP_IF_OFFSET)
#define EFM32_ACMP0_IFS (EFM32_ACMP0_BASE+EFM32_ACMP_IFS_OFFSET)
#define EFM32_ACMP0_IFC (EFM32_ACMP0_BASE+EFM32_ACMP_IFC_OFFSET)
#define EFM32_ACMP0_ROUTE (EFM32_ACMP0_BASE+EFM32_ACMP_ROUTE_OFFSET)
#define EFM32_ACMP1_CTRL (EFM32_ACMP1_BASE+EFM32_ACMP_CTRL_OFFSET)
#define EFM32_ACMP1_INPUTSEL (EFM32_ACMP1_BASE+EFM32_ACMP_INPUTSEL_OFFSET)
#define EFM32_ACMP1_STATUS (EFM32_ACMP1_BASE+EFM32_ACMP_STATUS_OFFSET)
#define EFM32_ACMP1_IEN (EFM32_ACMP1_BASE+EFM32_ACMP_IEN_OFFSET)
#define EFM32_ACMP1_IF (EFM32_ACMP1_BASE+EFM32_ACMP_IF_OFFSET)
#define EFM32_ACMP1_IFS (EFM32_ACMP1_BASE+EFM32_ACMP_IFS_OFFSET)
#define EFM32_ACMP1_IFC (EFM32_ACMP1_BASE+EFM32_ACMP_IFC_OFFSET)
#define EFM32_ACMP1_ROUTE (EFM32_ACMP1_BASE+EFM32_ACMP_ROUTE_OFFSET)
/* ACMP Register Bit Field Definitions *****************************************************************************************/
/* Bit fields for ACMP CTRL */
#define _ACMP_CTRL_RESETVALUE 0x47000000UL /* Default value for ACMP_CTRL */
#define _ACMP_CTRL_MASK 0xCF03077FUL /* Mask for ACMP_CTRL */
#define ACMP_CTRL_EN (0x1UL << 0) /* Analog Comparator Enable */
#define _ACMP_CTRL_EN_SHIFT 0 /* Shift value for ACMP_EN */
#define _ACMP_CTRL_EN_MASK 0x1UL /* Bit mask for ACMP_EN */
#define _ACMP_CTRL_EN_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_EN_DEFAULT (_ACMP_CTRL_EN_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_MUXEN (0x1UL << 1) /* Input Mux Enable */
#define _ACMP_CTRL_MUXEN_SHIFT 1 /* Shift value for ACMP_MUXEN */
#define _ACMP_CTRL_MUXEN_MASK 0x2UL /* Bit mask for ACMP_MUXEN */
#define _ACMP_CTRL_MUXEN_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_MUXEN_DEFAULT (_ACMP_CTRL_MUXEN_DEFAULT << 1) /* Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_INACTVAL (0x1UL << 2) /* Inactive Value */
#define _ACMP_CTRL_INACTVAL_SHIFT 2 /* Shift value for ACMP_INACTVAL */
#define _ACMP_CTRL_INACTVAL_MASK 0x4UL /* Bit mask for ACMP_INACTVAL */
#define _ACMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */
#define _ACMP_CTRL_INACTVAL_LOW 0x00000000UL /* Mode LOW for ACMP_CTRL */
#define _ACMP_CTRL_INACTVAL_HIGH 0x00000001UL /* Mode HIGH for ACMP_CTRL */
#define ACMP_CTRL_INACTVAL_DEFAULT (_ACMP_CTRL_INACTVAL_DEFAULT << 2) /* Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_INACTVAL_LOW (_ACMP_CTRL_INACTVAL_LOW << 2) /* Shifted mode LOW for ACMP_CTRL */
#define ACMP_CTRL_INACTVAL_HIGH (_ACMP_CTRL_INACTVAL_HIGH << 2) /* Shifted mode HIGH for ACMP_CTRL */
#define ACMP_CTRL_GPIOINV (0x1UL << 3) /* Comparator GPIO Output Invert */
#define _ACMP_CTRL_GPIOINV_SHIFT 3 /* Shift value for ACMP_GPIOINV */
#define _ACMP_CTRL_GPIOINV_MASK 0x8UL /* Bit mask for ACMP_GPIOINV */
#define _ACMP_CTRL_GPIOINV_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */
#define _ACMP_CTRL_GPIOINV_NOTINV 0x00000000UL /* Mode NOTINV for ACMP_CTRL */
#define _ACMP_CTRL_GPIOINV_INV 0x00000001UL /* Mode INV for ACMP_CTRL */
#define ACMP_CTRL_GPIOINV_DEFAULT (_ACMP_CTRL_GPIOINV_DEFAULT << 3) /* Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_GPIOINV_NOTINV (_ACMP_CTRL_GPIOINV_NOTINV << 3) /* Shifted mode NOTINV for ACMP_CTRL */
#define ACMP_CTRL_GPIOINV_INV (_ACMP_CTRL_GPIOINV_INV << 3) /* Shifted mode INV for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_SHIFT 4 /* Shift value for ACMP_HYSTSEL */
#define _ACMP_CTRL_HYSTSEL_MASK 0x70UL /* Bit mask for ACMP_HYSTSEL */
#define _ACMP_CTRL_HYSTSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST0 0x00000000UL /* Mode HYST0 for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST1 0x00000001UL /* Mode HYST1 for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST2 0x00000002UL /* Mode HYST2 for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST3 0x00000003UL /* Mode HYST3 for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST4 0x00000004UL /* Mode HYST4 for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST5 0x00000005UL /* Mode HYST5 for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST6 0x00000006UL /* Mode HYST6 for ACMP_CTRL */
#define _ACMP_CTRL_HYSTSEL_HYST7 0x00000007UL /* Mode HYST7 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_DEFAULT (_ACMP_CTRL_HYSTSEL_DEFAULT << 4) /* Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST0 (_ACMP_CTRL_HYSTSEL_HYST0 << 4) /* Shifted mode HYST0 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST1 (_ACMP_CTRL_HYSTSEL_HYST1 << 4) /* Shifted mode HYST1 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST2 (_ACMP_CTRL_HYSTSEL_HYST2 << 4) /* Shifted mode HYST2 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST3 (_ACMP_CTRL_HYSTSEL_HYST3 << 4) /* Shifted mode HYST3 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST4 (_ACMP_CTRL_HYSTSEL_HYST4 << 4) /* Shifted mode HYST4 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST5 (_ACMP_CTRL_HYSTSEL_HYST5 << 4) /* Shifted mode HYST5 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST6 (_ACMP_CTRL_HYSTSEL_HYST6 << 4) /* Shifted mode HYST6 for ACMP_CTRL */
#define ACMP_CTRL_HYSTSEL_HYST7 (_ACMP_CTRL_HYSTSEL_HYST7 << 4) /* Shifted mode HYST7 for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_SHIFT 8 /* Shift value for ACMP_WARMTIME */
#define _ACMP_CTRL_WARMTIME_MASK 0x700UL /* Bit mask for ACMP_WARMTIME */
#define _ACMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /* Mode 4CYCLES for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /* Mode 8CYCLES for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /* Mode 16CYCLES for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /* Mode 32CYCLES for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /* Mode 64CYCLES for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /* Mode 128CYCLES for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /* Mode 256CYCLES for ACMP_CTRL */
#define _ACMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /* Mode 512CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_DEFAULT (_ACMP_CTRL_WARMTIME_DEFAULT << 8) /* Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_4CYCLES (_ACMP_CTRL_WARMTIME_4CYCLES << 8) /* Shifted mode 4CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_8CYCLES (_ACMP_CTRL_WARMTIME_8CYCLES << 8) /* Shifted mode 8CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_16CYCLES (_ACMP_CTRL_WARMTIME_16CYCLES << 8) /* Shifted mode 16CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_32CYCLES (_ACMP_CTRL_WARMTIME_32CYCLES << 8) /* Shifted mode 32CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_64CYCLES (_ACMP_CTRL_WARMTIME_64CYCLES << 8) /* Shifted mode 64CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_128CYCLES (_ACMP_CTRL_WARMTIME_128CYCLES << 8) /* Shifted mode 128CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_256CYCLES (_ACMP_CTRL_WARMTIME_256CYCLES << 8) /* Shifted mode 256CYCLES for ACMP_CTRL */
#define ACMP_CTRL_WARMTIME_512CYCLES (_ACMP_CTRL_WARMTIME_512CYCLES << 8) /* Shifted mode 512CYCLES for ACMP_CTRL */
#define ACMP_CTRL_IRISE (0x1UL << 16) /* Rising Edge Interrupt Sense */
#define _ACMP_CTRL_IRISE_SHIFT 16 /* Shift value for ACMP_IRISE */
#define _ACMP_CTRL_IRISE_MASK 0x10000UL /* Bit mask for ACMP_IRISE */
#define _ACMP_CTRL_IRISE_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */
#define _ACMP_CTRL_IRISE_DISABLED 0x00000000UL /* Mode DISABLED for ACMP_CTRL */
#define _ACMP_CTRL_IRISE_ENABLED 0x00000001UL /* Mode ENABLED for ACMP_CTRL */
#define ACMP_CTRL_IRISE_DEFAULT (_ACMP_CTRL_IRISE_DEFAULT << 16) /* Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_IRISE_DISABLED (_ACMP_CTRL_IRISE_DISABLED << 16) /* Shifted mode DISABLED for ACMP_CTRL */
#define ACMP_CTRL_IRISE_ENABLED (_ACMP_CTRL_IRISE_ENABLED << 16) /* Shifted mode ENABLED for ACMP_CTRL */
#define ACMP_CTRL_IFALL (0x1UL << 17) /* Falling Edge Interrupt Sense */
#define _ACMP_CTRL_IFALL_SHIFT 17 /* Shift value for ACMP_IFALL */
#define _ACMP_CTRL_IFALL_MASK 0x20000UL /* Bit mask for ACMP_IFALL */
#define _ACMP_CTRL_IFALL_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */
#define _ACMP_CTRL_IFALL_DISABLED 0x00000000UL /* Mode DISABLED for ACMP_CTRL */
#define _ACMP_CTRL_IFALL_ENABLED 0x00000001UL /* Mode ENABLED for ACMP_CTRL */
#define ACMP_CTRL_IFALL_DEFAULT (_ACMP_CTRL_IFALL_DEFAULT << 17) /* Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_IFALL_DISABLED (_ACMP_CTRL_IFALL_DISABLED << 17) /* Shifted mode DISABLED for ACMP_CTRL */
#define ACMP_CTRL_IFALL_ENABLED (_ACMP_CTRL_IFALL_ENABLED << 17) /* Shifted mode ENABLED for ACMP_CTRL */
#define _ACMP_CTRL_BIASPROG_SHIFT 24 /* Shift value for ACMP_BIASPROG */
#define _ACMP_CTRL_BIASPROG_MASK 0xF000000UL /* Bit mask for ACMP_BIASPROG */
#define _ACMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /* Mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_BIASPROG_DEFAULT (_ACMP_CTRL_BIASPROG_DEFAULT << 24) /* Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_HALFBIAS (0x1UL << 30) /* Half Bias Current */
#define _ACMP_CTRL_HALFBIAS_SHIFT 30 /* Shift value for ACMP_HALFBIAS */
#define _ACMP_CTRL_HALFBIAS_MASK 0x40000000UL /* Bit mask for ACMP_HALFBIAS */
#define _ACMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /* Mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_HALFBIAS_DEFAULT (_ACMP_CTRL_HALFBIAS_DEFAULT << 30) /* Shifted mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_FULLBIAS (0x1UL << 31) /* Full Bias Current */
#define _ACMP_CTRL_FULLBIAS_SHIFT 31 /* Shift value for ACMP_FULLBIAS */
#define _ACMP_CTRL_FULLBIAS_MASK 0x80000000UL /* Bit mask for ACMP_FULLBIAS */
#define _ACMP_CTRL_FULLBIAS_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_CTRL */
#define ACMP_CTRL_FULLBIAS_DEFAULT (_ACMP_CTRL_FULLBIAS_DEFAULT << 31) /* Shifted mode DEFAULT for ACMP_CTRL */
/* Bit fields for ACMP INPUTSEL */
#define _ACMP_INPUTSEL_RESETVALUE 0x00010080UL /* Default value for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_MASK 0x31013FF7UL /* Mask for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_SHIFT 0 /* Shift value for ACMP_POSSEL */
#define _ACMP_INPUTSEL_POSSEL_MASK 0x7UL /* Bit mask for ACMP_POSSEL */
#define _ACMP_INPUTSEL_POSSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH0 0x00000000UL /* Mode CH0 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH1 0x00000001UL /* Mode CH1 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH2 0x00000002UL /* Mode CH2 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH3 0x00000003UL /* Mode CH3 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH4 0x00000004UL /* Mode CH4 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH5 0x00000005UL /* Mode CH5 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH6 0x00000006UL /* Mode CH6 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_POSSEL_CH7 0x00000007UL /* Mode CH7 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_DEFAULT (_ACMP_INPUTSEL_POSSEL_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH0 (_ACMP_INPUTSEL_POSSEL_CH0 << 0) /* Shifted mode CH0 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH1 (_ACMP_INPUTSEL_POSSEL_CH1 << 0) /* Shifted mode CH1 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH2 (_ACMP_INPUTSEL_POSSEL_CH2 << 0) /* Shifted mode CH2 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH3 (_ACMP_INPUTSEL_POSSEL_CH3 << 0) /* Shifted mode CH3 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH4 (_ACMP_INPUTSEL_POSSEL_CH4 << 0) /* Shifted mode CH4 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH5 (_ACMP_INPUTSEL_POSSEL_CH5 << 0) /* Shifted mode CH5 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH6 (_ACMP_INPUTSEL_POSSEL_CH6 << 0) /* Shifted mode CH6 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_POSSEL_CH7 (_ACMP_INPUTSEL_POSSEL_CH7 << 0) /* Shifted mode CH7 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_SHIFT 4 /* Shift value for ACMP_NEGSEL */
#define _ACMP_INPUTSEL_NEGSEL_MASK 0xF0UL /* Bit mask for ACMP_NEGSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH0 0x00000000UL /* Mode CH0 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH1 0x00000001UL /* Mode CH1 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH2 0x00000002UL /* Mode CH2 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH3 0x00000003UL /* Mode CH3 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH4 0x00000004UL /* Mode CH4 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH5 0x00000005UL /* Mode CH5 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH6 0x00000006UL /* Mode CH6 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CH7 0x00000007UL /* Mode CH7 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_DEFAULT 0x00000008UL /* Mode DEFAULT for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_1V25 0x00000008UL /* Mode 1V25 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_2V5 0x00000009UL /* Mode 2V5 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_VDD 0x0000000AUL /* Mode VDD for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_CAPSENSE 0x0000000BUL /* Mode CAPSENSE for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_DAC0CH0 0x0000000CUL /* Mode DAC0CH0 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_NEGSEL_DAC0CH1 0x0000000DUL /* Mode DAC0CH1 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH0 (_ACMP_INPUTSEL_NEGSEL_CH0 << 4) /* Shifted mode CH0 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH1 (_ACMP_INPUTSEL_NEGSEL_CH1 << 4) /* Shifted mode CH1 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH2 (_ACMP_INPUTSEL_NEGSEL_CH2 << 4) /* Shifted mode CH2 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH3 (_ACMP_INPUTSEL_NEGSEL_CH3 << 4) /* Shifted mode CH3 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH4 (_ACMP_INPUTSEL_NEGSEL_CH4 << 4) /* Shifted mode CH4 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH5 (_ACMP_INPUTSEL_NEGSEL_CH5 << 4) /* Shifted mode CH5 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH6 (_ACMP_INPUTSEL_NEGSEL_CH6 << 4) /* Shifted mode CH6 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CH7 (_ACMP_INPUTSEL_NEGSEL_CH7 << 4) /* Shifted mode CH7 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_DEFAULT (_ACMP_INPUTSEL_NEGSEL_DEFAULT << 4) /* Shifted mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_1V25 (_ACMP_INPUTSEL_NEGSEL_1V25 << 4) /* Shifted mode 1V25 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_2V5 (_ACMP_INPUTSEL_NEGSEL_2V5 << 4) /* Shifted mode 2V5 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_VDD (_ACMP_INPUTSEL_NEGSEL_VDD << 4) /* Shifted mode VDD for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_CAPSENSE (_ACMP_INPUTSEL_NEGSEL_CAPSENSE << 4) /* Shifted mode CAPSENSE for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_DAC0CH0 (_ACMP_INPUTSEL_NEGSEL_DAC0CH0 << 4) /* Shifted mode DAC0CH0 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_NEGSEL_DAC0CH1 (_ACMP_INPUTSEL_NEGSEL_DAC0CH1 << 4) /* Shifted mode DAC0CH1 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_VDDLEVEL_SHIFT 8 /* Shift value for ACMP_VDDLEVEL */
#define _ACMP_INPUTSEL_VDDLEVEL_MASK 0x3F00UL /* Bit mask for ACMP_VDDLEVEL */
#define _ACMP_INPUTSEL_VDDLEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_VDDLEVEL_DEFAULT (_ACMP_INPUTSEL_VDDLEVEL_DEFAULT << 8) /* Shifted mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_LPREF (0x1UL << 16) /* Low Power Reference Mode */
#define _ACMP_INPUTSEL_LPREF_SHIFT 16 /* Shift value for ACMP_LPREF */
#define _ACMP_INPUTSEL_LPREF_MASK 0x10000UL /* Bit mask for ACMP_LPREF */
#define _ACMP_INPUTSEL_LPREF_DEFAULT 0x00000001UL /* Mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_LPREF_DEFAULT (_ACMP_INPUTSEL_LPREF_DEFAULT << 16) /* Shifted mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_CSRESEN (0x1UL << 24) /* Capacitive Sense Mode Internal Resistor Enable */
#define _ACMP_INPUTSEL_CSRESEN_SHIFT 24 /* Shift value for ACMP_CSRESEN */
#define _ACMP_INPUTSEL_CSRESEN_MASK 0x1000000UL /* Bit mask for ACMP_CSRESEN */
#define _ACMP_INPUTSEL_CSRESEN_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_CSRESEN_DEFAULT (_ACMP_INPUTSEL_CSRESEN_DEFAULT << 24) /* Shifted mode DEFAULT for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_CSRESSEL_SHIFT 28 /* Shift value for ACMP_CSRESSEL */
#define _ACMP_INPUTSEL_CSRESSEL_MASK 0x30000000UL /* Bit mask for ACMP_CSRESSEL */
#define _ACMP_INPUTSEL_CSRESSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_CSRESSEL_RES0 0x00000000UL /* Mode RES0 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_CSRESSEL_RES1 0x00000001UL /* Mode RES1 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_CSRESSEL_RES2 0x00000002UL /* Mode RES2 for ACMP_INPUTSEL */
#define _ACMP_INPUTSEL_CSRESSEL_RES3 0x00000003UL /* Mode RES3 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_CSRESSEL_DEFAULT (_ACMP_INPUTSEL_CSRESSEL_DEFAULT << 28) /* Shifted mode DEFAULT for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_CSRESSEL_RES0 (_ACMP_INPUTSEL_CSRESSEL_RES0 << 28) /* Shifted mode RES0 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_CSRESSEL_RES1 (_ACMP_INPUTSEL_CSRESSEL_RES1 << 28) /* Shifted mode RES1 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_CSRESSEL_RES2 (_ACMP_INPUTSEL_CSRESSEL_RES2 << 28) /* Shifted mode RES2 for ACMP_INPUTSEL */
#define ACMP_INPUTSEL_CSRESSEL_RES3 (_ACMP_INPUTSEL_CSRESSEL_RES3 << 28) /* Shifted mode RES3 for ACMP_INPUTSEL */
/* Bit fields for ACMP STATUS */
#define _ACMP_STATUS_RESETVALUE 0x00000000UL /* Default value for ACMP_STATUS */
#define _ACMP_STATUS_MASK 0x00000003UL /* Mask for ACMP_STATUS */
#define ACMP_STATUS_ACMPACT (0x1UL << 0) /* Analog Comparator Active */
#define _ACMP_STATUS_ACMPACT_SHIFT 0 /* Shift value for ACMP_ACMPACT */
#define _ACMP_STATUS_ACMPACT_MASK 0x1UL /* Bit mask for ACMP_ACMPACT */
#define _ACMP_STATUS_ACMPACT_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_STATUS */
#define ACMP_STATUS_ACMPACT_DEFAULT (_ACMP_STATUS_ACMPACT_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_STATUS */
#define ACMP_STATUS_ACMPOUT (0x1UL << 1) /* Analog Comparator Output */
#define _ACMP_STATUS_ACMPOUT_SHIFT 1 /* Shift value for ACMP_ACMPOUT */
#define _ACMP_STATUS_ACMPOUT_MASK 0x2UL /* Bit mask for ACMP_ACMPOUT */
#define _ACMP_STATUS_ACMPOUT_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_STATUS */
#define ACMP_STATUS_ACMPOUT_DEFAULT (_ACMP_STATUS_ACMPOUT_DEFAULT << 1) /* Shifted mode DEFAULT for ACMP_STATUS */
/* Bit fields for ACMP IEN */
#define _ACMP_IEN_RESETVALUE 0x00000000UL /* Default value for ACMP_IEN */
#define _ACMP_IEN_MASK 0x00000003UL /* Mask for ACMP_IEN */
#define ACMP_IEN_EDGE (0x1UL << 0) /* Edge Trigger Interrupt Enable */
#define _ACMP_IEN_EDGE_SHIFT 0 /* Shift value for ACMP_EDGE */
#define _ACMP_IEN_EDGE_MASK 0x1UL /* Bit mask for ACMP_EDGE */
#define _ACMP_IEN_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IEN */
#define ACMP_IEN_EDGE_DEFAULT (_ACMP_IEN_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_IEN */
#define ACMP_IEN_WARMUP (0x1UL << 1) /* Warm-up Interrupt Enable */
#define _ACMP_IEN_WARMUP_SHIFT 1 /* Shift value for ACMP_WARMUP */
#define _ACMP_IEN_WARMUP_MASK 0x2UL /* Bit mask for ACMP_WARMUP */
#define _ACMP_IEN_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IEN */
#define ACMP_IEN_WARMUP_DEFAULT (_ACMP_IEN_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for ACMP_IEN */
/* Bit fields for ACMP IF */
#define _ACMP_IF_RESETVALUE 0x00000000UL /* Default value for ACMP_IF */
#define _ACMP_IF_MASK 0x00000003UL /* Mask for ACMP_IF */
#define ACMP_IF_EDGE (0x1UL << 0) /* Edge Triggered Interrupt Flag */
#define _ACMP_IF_EDGE_SHIFT 0 /* Shift value for ACMP_EDGE */
#define _ACMP_IF_EDGE_MASK 0x1UL /* Bit mask for ACMP_EDGE */
#define _ACMP_IF_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IF */
#define ACMP_IF_EDGE_DEFAULT (_ACMP_IF_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_IF */
#define ACMP_IF_WARMUP (0x1UL << 1) /* Warm-up Interrupt Flag */
#define _ACMP_IF_WARMUP_SHIFT 1 /* Shift value for ACMP_WARMUP */
#define _ACMP_IF_WARMUP_MASK 0x2UL /* Bit mask for ACMP_WARMUP */
#define _ACMP_IF_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IF */
#define ACMP_IF_WARMUP_DEFAULT (_ACMP_IF_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for ACMP_IF */
/* Bit fields for ACMP IFS */
#define _ACMP_IFS_RESETVALUE 0x00000000UL /* Default value for ACMP_IFS */
#define _ACMP_IFS_MASK 0x00000003UL /* Mask for ACMP_IFS */
#define ACMP_IFS_EDGE (0x1UL << 0) /* Edge Triggered Interrupt Flag Set */
#define _ACMP_IFS_EDGE_SHIFT 0 /* Shift value for ACMP_EDGE */
#define _ACMP_IFS_EDGE_MASK 0x1UL /* Bit mask for ACMP_EDGE */
#define _ACMP_IFS_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IFS */
#define ACMP_IFS_EDGE_DEFAULT (_ACMP_IFS_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_IFS */
#define ACMP_IFS_WARMUP (0x1UL << 1) /* Warm-up Interrupt Flag Set */
#define _ACMP_IFS_WARMUP_SHIFT 1 /* Shift value for ACMP_WARMUP */
#define _ACMP_IFS_WARMUP_MASK 0x2UL /* Bit mask for ACMP_WARMUP */
#define _ACMP_IFS_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IFS */
#define ACMP_IFS_WARMUP_DEFAULT (_ACMP_IFS_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for ACMP_IFS */
/* Bit fields for ACMP IFC */
#define _ACMP_IFC_RESETVALUE 0x00000000UL /* Default value for ACMP_IFC */
#define _ACMP_IFC_MASK 0x00000003UL /* Mask for ACMP_IFC */
#define ACMP_IFC_EDGE (0x1UL << 0) /* Edge Triggered Interrupt Flag Clear */
#define _ACMP_IFC_EDGE_SHIFT 0 /* Shift value for ACMP_EDGE */
#define _ACMP_IFC_EDGE_MASK 0x1UL /* Bit mask for ACMP_EDGE */
#define _ACMP_IFC_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IFC */
#define ACMP_IFC_EDGE_DEFAULT (_ACMP_IFC_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_IFC */
#define ACMP_IFC_WARMUP (0x1UL << 1) /* Warm-up Interrupt Flag Clear */
#define _ACMP_IFC_WARMUP_SHIFT 1 /* Shift value for ACMP_WARMUP */
#define _ACMP_IFC_WARMUP_MASK 0x2UL /* Bit mask for ACMP_WARMUP */
#define _ACMP_IFC_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_IFC */
#define ACMP_IFC_WARMUP_DEFAULT (_ACMP_IFC_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for ACMP_IFC */
/* Bit fields for ACMP ROUTE */
#define _ACMP_ROUTE_RESETVALUE 0x00000000UL /* Default value for ACMP_ROUTE */
#define _ACMP_ROUTE_MASK 0x00000701UL /* Mask for ACMP_ROUTE */
#define ACMP_ROUTE_ACMPPEN (0x1UL << 0) /* ACMP Output Pin Enable */
#define _ACMP_ROUTE_ACMPPEN_SHIFT 0 /* Shift value for ACMP_ACMPPEN */
#define _ACMP_ROUTE_ACMPPEN_MASK 0x1UL /* Bit mask for ACMP_ACMPPEN */
#define _ACMP_ROUTE_ACMPPEN_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_ROUTE */
#define ACMP_ROUTE_ACMPPEN_DEFAULT (_ACMP_ROUTE_ACMPPEN_DEFAULT << 0) /* Shifted mode DEFAULT for ACMP_ROUTE */
#define _ACMP_ROUTE_LOCATION_SHIFT 8 /* Shift value for ACMP_LOCATION */
#define _ACMP_ROUTE_LOCATION_MASK 0x700UL /* Bit mask for ACMP_LOCATION */
#define _ACMP_ROUTE_LOCATION_LOC0 0x00000000UL /* Mode LOC0 for ACMP_ROUTE */
#define _ACMP_ROUTE_LOCATION_DEFAULT 0x00000000UL /* Mode DEFAULT for ACMP_ROUTE */
#define _ACMP_ROUTE_LOCATION_LOC1 0x00000001UL /* Mode LOC1 for ACMP_ROUTE */
#define _ACMP_ROUTE_LOCATION_LOC2 0x00000002UL /* Mode LOC2 for ACMP_ROUTE */
#define ACMP_ROUTE_LOCATION_LOC0 (_ACMP_ROUTE_LOCATION_LOC0 << 8) /* Shifted mode LOC0 for ACMP_ROUTE */
#define ACMP_ROUTE_LOCATION_DEFAULT (_ACMP_ROUTE_LOCATION_DEFAULT << 8) /* Shifted mode DEFAULT for ACMP_ROUTE */
#define ACMP_ROUTE_LOCATION_LOC1 (_ACMP_ROUTE_LOCATION_LOC1 << 8) /* Shifted mode LOC1 for ACMP_ROUTE */
#define ACMP_ROUTE_LOCATION_LOC2 (_ACMP_ROUTE_LOCATION_LOC2 << 8) /* Shifted mode LOC2 for ACMP_ROUTE */
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ACMP_H */
arch/arm/src/efm32/chip/efm32_adc.h
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arch/arm/src/efm32/chip/efm32_aes.h
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/*******************************************************************************************************************************
* arch/arm/src/efm32/chip/efm32_aes.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Authors: Pierre-noel Bouteville <pnb990@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_AES_H_
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_AES_H_
/*******************************************************************************************************************************
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG)
# warning This is the EFM32GG header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* AES Register Offsets ********************************************************************************************************/
#define EFM32_AES_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_AES_CMD_OFFSET 0x0004 /* Command Register */
#define EFM32_AES_STATUS_OFFSET 0x0008 /* Status Register */
#define EFM32_AES_IEN_OFFSET 0x000c /* Interrupt Enable Register */
#define EFM32_AES_IF_OFFSET 0x0010 /* Interrupt Flag Register */
#define EFM32_AES_IFS_OFFSET 0x0014 /* Interrupt Flag Set Register */
#define EFM32_AES_IFC_OFFSET 0x0018 /* Interrupt Flag Clear Register */
#define EFM32_AES_DATA_OFFSET 0x001c /* DATA Register */
#define EFM32_AES_XORDATA_OFFSET 0x0020 /* XORDATA Register */
#define EFM32_AES_KEYLA_OFFSET 0x0030 /* KEY Low Register */
#define EFM32_AES_KEYLB_OFFSET 0x0034 /* KEY Low Register */
#define EFM32_AES_KEYLC_OFFSET 0x0038 /* KEY Low Register */
#define EFM32_AES_KEYLD_OFFSET 0x003c /* KEY Low Register */
#define EFM32_AES_KEYHA_OFFSET 0x0040 /* KEY High Register */
#define EFM32_AES_KEYHB_OFFSET 0x0044 /* KEY High Register */
#define EFM32_AES_KEYHC_OFFSET 0x0048 /* KEY High Register */
#define EFM32_AES_KEYHD_OFFSET 0x004c /* KEY High Register */
/* AES Register Addresses ******************************************************************************************************/
#define EFM32_AES_CTRL (EFM32_AES_BASE+EFM32_AES_CTRL_OFFSET)
#define EFM32_AES_CMD (EFM32_AES_BASE+EFM32_AES_CMD_OFFSET)
#define EFM32_AES_STATUS (EFM32_AES_BASE+EFM32_AES_STATUS_OFFSET)
#define EFM32_AES_IEN (EFM32_AES_BASE+EFM32_AES_IEN_OFFSET)
#define EFM32_AES_IF (EFM32_AES_BASE+EFM32_AES_IF_OFFSET)
#define EFM32_AES_IFS (EFM32_AES_BASE+EFM32_AES_IFS_OFFSET)
#define EFM32_AES_IFC (EFM32_AES_BASE+EFM32_AES_IFC_OFFSET)
#define EFM32_AES_DATA (EFM32_AES_BASE+EFM32_AES_DATA_OFFSET)
#define EFM32_AES_XORDATA (EFM32_AES_BASE+EFM32_AES_XORDATA_OFFSET)
#define EFM32_AES_KEYLA (EFM32_AES_BASE+EFM32_AES_KEYLA_OFFSET)
#define EFM32_AES_KEYLB (EFM32_AES_BASE+EFM32_AES_KEYLB_OFFSET)
#define EFM32_AES_KEYLC (EFM32_AES_BASE+EFM32_AES_KEYLC_OFFSET)
#define EFM32_AES_KEYLD (EFM32_AES_BASE+EFM32_AES_KEYLD_OFFSET)
#define EFM32_AES_KEYHA (EFM32_AES_BASE+EFM32_AES_KEYHA_OFFSET)
#define EFM32_AES_KEYHB (EFM32_AES_BASE+EFM32_AES_KEYHB_OFFSET)
#define EFM32_AES_KEYHC (EFM32_AES_BASE+EFM32_AES_KEYHC_OFFSET)
#define EFM32_AES_KEYHD (EFM32_AES_BASE+EFM32_AES_KEYHD_OFFSET)
/* AES Register Bit Field Definitions ******************************************************************************************/
/* Bit fields for AES CTRL */
#define _AES_CTRL_RESETVALUE 0x00000000UL /* Default value for AES_CTRL */
#define _AES_CTRL_MASK 0x00000077UL /* Mask for AES_CTRL */
#define AES_CTRL_DECRYPT (0x1UL << 0) /* Decryption/Encryption Mode */
#define _AES_CTRL_DECRYPT_SHIFT 0 /* Shift value for AES_DECRYPT */
#define _AES_CTRL_DECRYPT_MASK 0x1UL /* Bit mask for AES_DECRYPT */
#define _AES_CTRL_DECRYPT_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CTRL */
#define AES_CTRL_DECRYPT_DEFAULT (_AES_CTRL_DECRYPT_DEFAULT << 0) /* Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_AES256 (0x1UL << 1) /* AES-256 Mode */
#define _AES_CTRL_AES256_SHIFT 1 /* Shift value for AES_AES256 */
#define _AES_CTRL_AES256_MASK 0x2UL /* Bit mask for AES_AES256 */
#define _AES_CTRL_AES256_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CTRL */
#define AES_CTRL_AES256_DEFAULT (_AES_CTRL_AES256_DEFAULT << 1) /* Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_KEYBUFEN (0x1UL << 2) /* Key Buffer Enable */
#define _AES_CTRL_KEYBUFEN_SHIFT 2 /* Shift value for AES_KEYBUFEN */
#define _AES_CTRL_KEYBUFEN_MASK 0x4UL /* Bit mask for AES_KEYBUFEN */
#define _AES_CTRL_KEYBUFEN_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CTRL */
#define AES_CTRL_KEYBUFEN_DEFAULT (_AES_CTRL_KEYBUFEN_DEFAULT << 2) /* Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_DATASTART (0x1UL << 4) /* AES_DATA Write Start */
#define _AES_CTRL_DATASTART_SHIFT 4 /* Shift value for AES_DATASTART */
#define _AES_CTRL_DATASTART_MASK 0x10UL /* Bit mask for AES_DATASTART */
#define _AES_CTRL_DATASTART_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CTRL */
#define AES_CTRL_DATASTART_DEFAULT (_AES_CTRL_DATASTART_DEFAULT << 4) /* Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_XORSTART (0x1UL << 5) /* AES_XORDATA Write Start */
#define _AES_CTRL_XORSTART_SHIFT 5 /* Shift value for AES_XORSTART */
#define _AES_CTRL_XORSTART_MASK 0x20UL /* Bit mask for AES_XORSTART */
#define _AES_CTRL_XORSTART_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CTRL */
#define AES_CTRL_XORSTART_DEFAULT (_AES_CTRL_XORSTART_DEFAULT << 5) /* Shifted mode DEFAULT for AES_CTRL */
#define AES_CTRL_BYTEORDER (0x1UL << 6) /* Configure byte order in data and key registers */
#define _AES_CTRL_BYTEORDER_SHIFT 6 /* Shift value for AES_BYTEORDER */
#define _AES_CTRL_BYTEORDER_MASK 0x40UL /* Bit mask for AES_BYTEORDER */
#define _AES_CTRL_BYTEORDER_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CTRL */
#define AES_CTRL_BYTEORDER_DEFAULT (_AES_CTRL_BYTEORDER_DEFAULT << 6) /* Shifted mode DEFAULT for AES_CTRL */
/* Bit fields for AES CMD */
#define _AES_CMD_RESETVALUE 0x00000000UL /* Default value for AES_CMD */
#define _AES_CMD_MASK 0x00000003UL /* Mask for AES_CMD */
#define AES_CMD_START (0x1UL << 0) /* Encryption/Decryption Start */
#define _AES_CMD_START_SHIFT 0 /* Shift value for AES_START */
#define _AES_CMD_START_MASK 0x1UL /* Bit mask for AES_START */
#define _AES_CMD_START_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CMD */
#define AES_CMD_START_DEFAULT (_AES_CMD_START_DEFAULT << 0) /* Shifted mode DEFAULT for AES_CMD */
#define AES_CMD_STOP (0x1UL << 1) /* Encryption/Decryption Stop */
#define _AES_CMD_STOP_SHIFT 1 /* Shift value for AES_STOP */
#define _AES_CMD_STOP_MASK 0x2UL /* Bit mask for AES_STOP */
#define _AES_CMD_STOP_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_CMD */
#define AES_CMD_STOP_DEFAULT (_AES_CMD_STOP_DEFAULT << 1) /* Shifted mode DEFAULT for AES_CMD */
/* Bit fields for AES STATUS */
#define _AES_STATUS_RESETVALUE 0x00000000UL /* Default value for AES_STATUS */
#define _AES_STATUS_MASK 0x00000001UL /* Mask for AES_STATUS */
#define AES_STATUS_RUNNING (0x1UL << 0) /* AES Running */
#define _AES_STATUS_RUNNING_SHIFT 0 /* Shift value for AES_RUNNING */
#define _AES_STATUS_RUNNING_MASK 0x1UL /* Bit mask for AES_RUNNING */
#define _AES_STATUS_RUNNING_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_STATUS */
#define AES_STATUS_RUNNING_DEFAULT (_AES_STATUS_RUNNING_DEFAULT << 0) /* Shifted mode DEFAULT for AES_STATUS */
/* Bit fields for AES IEN */
#define _AES_IEN_RESETVALUE 0x00000000UL /* Default value for AES_IEN */
#define _AES_IEN_MASK 0x00000001UL /* Mask for AES_IEN */
#define AES_IEN_DONE (0x1UL << 0) /* Encryption/Decryption Done Interrupt Enable */
#define _AES_IEN_DONE_SHIFT 0 /* Shift value for AES_DONE */
#define _AES_IEN_DONE_MASK 0x1UL /* Bit mask for AES_DONE */
#define _AES_IEN_DONE_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_IEN */
#define AES_IEN_DONE_DEFAULT (_AES_IEN_DONE_DEFAULT << 0) /* Shifted mode DEFAULT for AES_IEN */
/* Bit fields for AES IF */
#define _AES_IF_RESETVALUE 0x00000000UL /* Default value for AES_IF */
#define _AES_IF_MASK 0x00000001UL /* Mask for AES_IF */
#define AES_IF_DONE (0x1UL << 0) /* Encryption/Decryption Done Interrupt Flag */
#define _AES_IF_DONE_SHIFT 0 /* Shift value for AES_DONE */
#define _AES_IF_DONE_MASK 0x1UL /* Bit mask for AES_DONE */
#define _AES_IF_DONE_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_IF */
#define AES_IF_DONE_DEFAULT (_AES_IF_DONE_DEFAULT << 0) /* Shifted mode DEFAULT for AES_IF */
/* Bit fields for AES IFS */
#define _AES_IFS_RESETVALUE 0x00000000UL /* Default value for AES_IFS */
#define _AES_IFS_MASK 0x00000001UL /* Mask for AES_IFS */
#define AES_IFS_DONE (0x1UL << 0) /* Encryption/Decryption Done Interrupt Flag Set */
#define _AES_IFS_DONE_SHIFT 0 /* Shift value for AES_DONE */
#define _AES_IFS_DONE_MASK 0x1UL /* Bit mask for AES_DONE */
#define _AES_IFS_DONE_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_IFS */
#define AES_IFS_DONE_DEFAULT (_AES_IFS_DONE_DEFAULT << 0) /* Shifted mode DEFAULT for AES_IFS */
/* Bit fields for AES IFC */
#define _AES_IFC_RESETVALUE 0x00000000UL /* Default value for AES_IFC */
#define _AES_IFC_MASK 0x00000001UL /* Mask for AES_IFC */
#define AES_IFC_DONE (0x1UL << 0) /* Encryption/Decryption Done Interrupt Flag Clear */
#define _AES_IFC_DONE_SHIFT 0 /* Shift value for AES_DONE */
#define _AES_IFC_DONE_MASK 0x1UL /* Bit mask for AES_DONE */
#define _AES_IFC_DONE_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_IFC */
#define AES_IFC_DONE_DEFAULT (_AES_IFC_DONE_DEFAULT << 0) /* Shifted mode DEFAULT for AES_IFC */
/* Bit fields for AES DATA */
#define _AES_DATA_RESETVALUE 0x00000000UL /* Default value for AES_DATA */
#define _AES_DATA_MASK 0xFFFFFFFFUL /* Mask for AES_DATA */
#define _AES_DATA_DATA_SHIFT 0 /* Shift value for AES_DATA */
#define _AES_DATA_DATA_MASK 0xFFFFFFFFUL /* Bit mask for AES_DATA */
#define _AES_DATA_DATA_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_DATA */
#define AES_DATA_DATA_DEFAULT (_AES_DATA_DATA_DEFAULT << 0) /* Shifted mode DEFAULT for AES_DATA */
/* Bit fields for AES XORDATA */
#define _AES_XORDATA_RESETVALUE 0x00000000UL /* Default value for AES_XORDATA */
#define _AES_XORDATA_MASK 0xFFFFFFFFUL /* Mask for AES_XORDATA */
#define _AES_XORDATA_XORDATA_SHIFT 0 /* Shift value for AES_XORDATA */
#define _AES_XORDATA_XORDATA_MASK 0xFFFFFFFFUL /* Bit mask for AES_XORDATA */
#define _AES_XORDATA_XORDATA_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_XORDATA */
#define AES_XORDATA_XORDATA_DEFAULT (_AES_XORDATA_XORDATA_DEFAULT << 0) /* Shifted mode DEFAULT for AES_XORDATA */
/* Bit fields for AES KEYLA */
#define _AES_KEYLA_RESETVALUE 0x00000000UL /* Default value for AES_KEYLA */
#define _AES_KEYLA_MASK 0xFFFFFFFFUL /* Mask for AES_KEYLA */
#define _AES_KEYLA_KEYLA_SHIFT 0 /* Shift value for AES_KEYLA */
#define _AES_KEYLA_KEYLA_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYLA */
#define _AES_KEYLA_KEYLA_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYLA */
#define AES_KEYLA_KEYLA_DEFAULT (_AES_KEYLA_KEYLA_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYLA */
/* Bit fields for AES KEYLB */
#define _AES_KEYLB_RESETVALUE 0x00000000UL /* Default value for AES_KEYLB */
#define _AES_KEYLB_MASK 0xFFFFFFFFUL /* Mask for AES_KEYLB */
#define _AES_KEYLB_KEYLB_SHIFT 0 /* Shift value for AES_KEYLB */
#define _AES_KEYLB_KEYLB_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYLB */
#define _AES_KEYLB_KEYLB_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYLB */
#define AES_KEYLB_KEYLB_DEFAULT (_AES_KEYLB_KEYLB_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYLB */
/* Bit fields for AES KEYLC */
#define _AES_KEYLC_RESETVALUE 0x00000000UL /* Default value for AES_KEYLC */
#define _AES_KEYLC_MASK 0xFFFFFFFFUL /* Mask for AES_KEYLC */
#define _AES_KEYLC_KEYLC_SHIFT 0 /* Shift value for AES_KEYLC */
#define _AES_KEYLC_KEYLC_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYLC */
#define _AES_KEYLC_KEYLC_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYLC */
#define AES_KEYLC_KEYLC_DEFAULT (_AES_KEYLC_KEYLC_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYLC */
/* Bit fields for AES KEYLD */
#define _AES_KEYLD_RESETVALUE 0x00000000UL /* Default value for AES_KEYLD */
#define _AES_KEYLD_MASK 0xFFFFFFFFUL /* Mask for AES_KEYLD */
#define _AES_KEYLD_KEYLD_SHIFT 0 /* Shift value for AES_KEYLD */
#define _AES_KEYLD_KEYLD_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYLD */
#define _AES_KEYLD_KEYLD_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYLD */
#define AES_KEYLD_KEYLD_DEFAULT (_AES_KEYLD_KEYLD_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYLD */
/* Bit fields for AES KEYHA */
#define _AES_KEYHA_RESETVALUE 0x00000000UL /* Default value for AES_KEYHA */
#define _AES_KEYHA_MASK 0xFFFFFFFFUL /* Mask for AES_KEYHA */
#define _AES_KEYHA_KEYHA_SHIFT 0 /* Shift value for AES_KEYHA */
#define _AES_KEYHA_KEYHA_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYHA */
#define _AES_KEYHA_KEYHA_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYHA */
#define AES_KEYHA_KEYHA_DEFAULT (_AES_KEYHA_KEYHA_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYHA */
/* Bit fields for AES KEYHB */
#define _AES_KEYHB_RESETVALUE 0x00000000UL /* Default value for AES_KEYHB */
#define _AES_KEYHB_MASK 0xFFFFFFFFUL /* Mask for AES_KEYHB */
#define _AES_KEYHB_KEYHB_SHIFT 0 /* Shift value for AES_KEYHB */
#define _AES_KEYHB_KEYHB_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYHB */
#define _AES_KEYHB_KEYHB_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYHB */
#define AES_KEYHB_KEYHB_DEFAULT (_AES_KEYHB_KEYHB_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYHB */
/* Bit fields for AES KEYHC */
#define _AES_KEYHC_RESETVALUE 0x00000000UL /* Default value for AES_KEYHC */
#define _AES_KEYHC_MASK 0xFFFFFFFFUL /* Mask for AES_KEYHC */
#define _AES_KEYHC_KEYHC_SHIFT 0 /* Shift value for AES_KEYHC */
#define _AES_KEYHC_KEYHC_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYHC */
#define _AES_KEYHC_KEYHC_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYHC */
#define AES_KEYHC_KEYHC_DEFAULT (_AES_KEYHC_KEYHC_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYHC */
/* Bit fields for AES KEYHD */
#define _AES_KEYHD_RESETVALUE 0x00000000UL /* Default value for AES_KEYHD */
#define _AES_KEYHD_MASK 0xFFFFFFFFUL /* Mask for AES_KEYHD */
#define _AES_KEYHD_KEYHD_SHIFT 0 /* Shift value for AES_KEYHD */
#define _AES_KEYHD_KEYHD_MASK 0xFFFFFFFFUL /* Bit mask for AES_KEYHD */
#define _AES_KEYHD_KEYHD_DEFAULT 0x00000000UL /* Mode DEFAULT for AES_KEYHD */
#define AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0) /* Shifted mode DEFAULT for AES_KEYHD */
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_AES_H_ */
arch/arm/src/efm32/chip/efm32_burtc.h
+471
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@@ -0,0 +1,471 @@
/*******************************************************************************************************************************
* arch/arm/src/efm32/chip/efm32_burtc.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Authors: Pierre-noel Bouteville <pnb990@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_BURTC_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_BURTC_H
/*******************************************************************************************************************************
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG)
# warning This is the EFM32GG header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
#define EFM32_BURTC_NREGS 128 /* Number of backup retention registers */
/* BURTC Register Offsets ******************************************************************************************************/
#define EFM32_BURTC_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_BURTC_LPMODE_OFFSET 0x0004 /* Low power mode configuration */
#define EFM32_BURTC_CNT_OFFSET 0x0008 /* Counter Value Register */
#define EFM32_BURTC_COMP0_OFFSET 0x000c /* Counter Compare Value */
#define EFM32_BURTC_TIMESTAMP_OFFSET 0x0010 /* Backup mode timestamp */
#define EFM32_BURTC_LFXOFDET_OFFSET 0x0014 /* LFXO */
#define EFM32_BURTC_STATUS_OFFSET 0x0018 /* Backup domain status */
#define EFM32_BURTC_CMD_OFFSET 0x001c /* Command Register */
#define EFM32_BURTC_POWERDOWN_OFFSET 0x0020 /* Retention RAM power-down resgister */
#define EFM32_BURTC_LOCK_OFFSET 0x0024 /* Configuration Lock Register */
#define EFM32_BURTC_IF_OFFSET 0x0028 /* Interrupt Flag Register */
#define EFM32_BURTC_IFS_OFFSET 0x002c /* Interrupt Flag Set Register */
#define EFM32_BURTC_IFC_OFFSET 0x0030 /* Interrupt Flag Clear Register */
#define EFM32_BURTC_IEN_OFFSET 0x0034 /* Interrupt Enable Register */
#define EFM32_BURTC_FREEZE_OFFSET 0x0038 /* Freeze Register */
#define EFM32_BURTC_SYNCBUSY_OFFSET 0x003c /* Synchronization Busy Register */
/* Backup retention register */
#define EFM32_BURTC_RET_REG_OFFSET(n) (0x0100 + ((n) << 2))
/* BURTC Register Addresses ****************************************************************************************************/
#define EFM32_BURTC_CTRL (EFM32_BCKRTC_BASE+EFM32_BURTC_CTRL_OFFSET)
#define EFM32_BURTC_LPMODE (EFM32_BCKRTC_BASE+EFM32_BURTC_LPMODE_OFFSET)
#define EFM32_BURTC_CNT (EFM32_BCKRTC_BASE+EFM32_BURTC_CNT_OFFSET)
#define EFM32_BURTC_COMP0 (EFM32_BCKRTC_BASE+EFM32_BURTC_COMP0_OFFSET)
#define EFM32_BURTC_TIMESTAMP (EFM32_BCKRTC_BASE+EFM32_BURTC_TIMESTAMP_OFFSET)
#define EFM32_BURTC_LFXOFDET (EFM32_BCKRTC_BASE+EFM32_BURTC_LFXOFDET_OFFSET)
#define EFM32_BURTC_STATUS (EFM32_BCKRTC_BASE+EFM32_BURTC_STATUS_OFFSET)
#define EFM32_BURTC_CMD (EFM32_BCKRTC_BASE+EFM32_BURTC_CMD_OFFSET)
#define EFM32_BURTC_POWERDOWN (EFM32_BCKRTC_BASE+EFM32_BURTC_POWERDOWN_OFFSET)
#define EFM32_BURTC_LOCK (EFM32_BCKRTC_BASE+EFM32_BURTC_LOCK_OFFSET)
#define EFM32_BURTC_IF (EFM32_BCKRTC_BASE+EFM32_BURTC_IF_OFFSET)
#define EFM32_BURTC_IFS (EFM32_BCKRTC_BASE+EFM32_BURTC_IFS_OFFSET)
#define EFM32_BURTC_IFC (EFM32_BCKRTC_BASE+EFM32_BURTC_IFC_OFFSET)
#define EFM32_BURTC_IEN (EFM32_BCKRTC_BASE+EFM32_BURTC_IEN_OFFSET)
#define EFM32_BURTC_FREEZE (EFM32_BCKRTC_BASE+EFM32_BURTC_FREEZE_OFFSET)
#define EFM32_BURTC_SYNCBUSY (EFM32_BCKRTC_BASE+EFM32_BURTC_SYNCBUSY_OFFSET)
/* Backup retention register */
#define EFM32_BURTC_RET_REG(n) (EFM32_BCKRTC_BASE+EFM32_BURTC_RET_REG_OFFSET(n))
/* BURTC Register Bit Field Definitions ****************************************************************************************/
/* Bit fields for BURTC CTRL */
#define _BURTC_CTRL_RESETVALUE 0x00000008UL /* Default value for BURTC_CTRL */
#define _BURTC_CTRL_MASK 0x000077FFUL /* Mask for BURTC_CTRL */
#define _BURTC_CTRL_MODE_SHIFT 0 /* Shift value for BURTC_MODE */
#define _BURTC_CTRL_MODE_MASK 0x3UL /* Bit mask for BURTC_MODE */
#define _BURTC_CTRL_MODE_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CTRL */
#define _BURTC_CTRL_MODE_DISABLE 0x00000000UL /* Mode DISABLE for BURTC_CTRL */
#define _BURTC_CTRL_MODE_EM2EN 0x00000001UL /* Mode EM2EN for BURTC_CTRL */
#define _BURTC_CTRL_MODE_EM3EN 0x00000002UL /* Mode EM3EN for BURTC_CTRL */
#define _BURTC_CTRL_MODE_EM4EN 0x00000003UL /* Mode EM4EN for BURTC_CTRL */
#define BURTC_CTRL_MODE_DEFAULT (_BURTC_CTRL_MODE_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_MODE_DISABLE (_BURTC_CTRL_MODE_DISABLE << 0) /* Shifted mode DISABLE for BURTC_CTRL */
#define BURTC_CTRL_MODE_EM2EN (_BURTC_CTRL_MODE_EM2EN << 0) /* Shifted mode EM2EN for BURTC_CTRL */
#define BURTC_CTRL_MODE_EM3EN (_BURTC_CTRL_MODE_EM3EN << 0) /* Shifted mode EM3EN for BURTC_CTRL */
#define BURTC_CTRL_MODE_EM4EN (_BURTC_CTRL_MODE_EM4EN << 0) /* Shifted mode EM4EN for BURTC_CTRL */
#define BURTC_CTRL_DEBUGRUN (0x1UL << 2) /* Debug Mode Run Enable */
#define _BURTC_CTRL_DEBUGRUN_SHIFT 2 /* Shift value for BURTC_DEBUGRUN */
#define _BURTC_CTRL_DEBUGRUN_MASK 0x4UL /* Bit mask for BURTC_DEBUGRUN */
#define _BURTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_DEBUGRUN_DEFAULT (_BURTC_CTRL_DEBUGRUN_DEFAULT << 2) /* Shifted mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_RSTEN (0x1UL << 3) /* Enable BURTC reset */
#define _BURTC_CTRL_RSTEN_SHIFT 3 /* Shift value for BURTC_RSTEN */
#define _BURTC_CTRL_RSTEN_MASK 0x8UL /* Bit mask for BURTC_RSTEN */
#define _BURTC_CTRL_RSTEN_DEFAULT 0x00000001UL /* Mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_RSTEN_DEFAULT (_BURTC_CTRL_RSTEN_DEFAULT << 3) /* Shifted mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_COMP0TOP (0x1UL << 4) /* Compare clear enable */
#define _BURTC_CTRL_COMP0TOP_SHIFT 4 /* Shift value for BURTC_COMP0TOP */
#define _BURTC_CTRL_COMP0TOP_MASK 0x10UL /* Bit mask for BURTC_COMP0TOP */
#define _BURTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_COMP0TOP_DEFAULT (_BURTC_CTRL_COMP0TOP_DEFAULT << 4) /* Shifted mode DEFAULT for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_SHIFT 5 /* Shift value for BURTC_LPCOMP */
#define _BURTC_CTRL_LPCOMP_MASK 0xE0UL /* Bit mask for BURTC_LPCOMP */
#define _BURTC_CTRL_LPCOMP_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN0LSB 0x00000000UL /* Mode IGN0LSB for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN1LSB 0x00000001UL /* Mode IGN1LSB for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN2LSB 0x00000002UL /* Mode IGN2LSB for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN3LSB 0x00000003UL /* Mode IGN3LSB for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN4LSB 0x00000004UL /* Mode IGN4LSB for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN5LSB 0x00000005UL /* Mode IGN5LSB for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN6LSB 0x00000006UL /* Mode IGN6LSB for BURTC_CTRL */
#define _BURTC_CTRL_LPCOMP_IGN7LSB 0x00000007UL /* Mode IGN7LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_DEFAULT (_BURTC_CTRL_LPCOMP_DEFAULT << 5) /* Shifted mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN0LSB (_BURTC_CTRL_LPCOMP_IGN0LSB << 5) /* Shifted mode IGN0LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN1LSB (_BURTC_CTRL_LPCOMP_IGN1LSB << 5) /* Shifted mode IGN1LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN2LSB (_BURTC_CTRL_LPCOMP_IGN2LSB << 5) /* Shifted mode IGN2LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN3LSB (_BURTC_CTRL_LPCOMP_IGN3LSB << 5) /* Shifted mode IGN3LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN4LSB (_BURTC_CTRL_LPCOMP_IGN4LSB << 5) /* Shifted mode IGN4LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN5LSB (_BURTC_CTRL_LPCOMP_IGN5LSB << 5) /* Shifted mode IGN5LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN6LSB (_BURTC_CTRL_LPCOMP_IGN6LSB << 5) /* Shifted mode IGN6LSB for BURTC_CTRL */
#define BURTC_CTRL_LPCOMP_IGN7LSB (_BURTC_CTRL_LPCOMP_IGN7LSB << 5) /* Shifted mode IGN7LSB for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_SHIFT 8 /* Shift value for BURTC_PRESC */
#define _BURTC_CTRL_PRESC_MASK 0x700UL /* Bit mask for BURTC_PRESC */
#define _BURTC_CTRL_PRESC_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV1 0x00000000UL /* Mode DIV1 for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV2 0x00000001UL /* Mode DIV2 for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV4 0x00000002UL /* Mode DIV4 for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV8 0x00000003UL /* Mode DIV8 for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV16 0x00000004UL /* Mode DIV16 for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV32 0x00000005UL /* Mode DIV32 for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV64 0x00000006UL /* Mode DIV64 for BURTC_CTRL */
#define _BURTC_CTRL_PRESC_DIV128 0x00000007UL /* Mode DIV128 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DEFAULT (_BURTC_CTRL_PRESC_DEFAULT << 8) /* Shifted mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV1 (_BURTC_CTRL_PRESC_DIV1 << 8) /* Shifted mode DIV1 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV2 (_BURTC_CTRL_PRESC_DIV2 << 8) /* Shifted mode DIV2 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV4 (_BURTC_CTRL_PRESC_DIV4 << 8) /* Shifted mode DIV4 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV8 (_BURTC_CTRL_PRESC_DIV8 << 8) /* Shifted mode DIV8 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV16 (_BURTC_CTRL_PRESC_DIV16 << 8) /* Shifted mode DIV16 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV32 (_BURTC_CTRL_PRESC_DIV32 << 8) /* Shifted mode DIV32 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV64 (_BURTC_CTRL_PRESC_DIV64 << 8) /* Shifted mode DIV64 for BURTC_CTRL */
#define BURTC_CTRL_PRESC_DIV128 (_BURTC_CTRL_PRESC_DIV128 << 8) /* Shifted mode DIV128 for BURTC_CTRL */
#define _BURTC_CTRL_CLKSEL_SHIFT 12 /* Shift value for BURTC_CLKSEL */
#define _BURTC_CTRL_CLKSEL_MASK 0x3000UL /* Bit mask for BURTC_CLKSEL */
#define _BURTC_CTRL_CLKSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CTRL */
#define _BURTC_CTRL_CLKSEL_NONE 0x00000000UL /* Mode NONE for BURTC_CTRL */
#define _BURTC_CTRL_CLKSEL_LFRCO 0x00000001UL /* Mode LFRCO for BURTC_CTRL */
#define _BURTC_CTRL_CLKSEL_LFXO 0x00000002UL /* Mode LFXO for BURTC_CTRL */
#define _BURTC_CTRL_CLKSEL_ULFRCO 0x00000003UL /* Mode ULFRCO for BURTC_CTRL */
#define BURTC_CTRL_CLKSEL_DEFAULT (_BURTC_CTRL_CLKSEL_DEFAULT << 12) /* Shifted mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_CLKSEL_NONE (_BURTC_CTRL_CLKSEL_NONE << 12) /* Shifted mode NONE for BURTC_CTRL */
#define BURTC_CTRL_CLKSEL_LFRCO (_BURTC_CTRL_CLKSEL_LFRCO << 12) /* Shifted mode LFRCO for BURTC_CTRL */
#define BURTC_CTRL_CLKSEL_LFXO (_BURTC_CTRL_CLKSEL_LFXO << 12) /* Shifted mode LFXO for BURTC_CTRL */
#define BURTC_CTRL_CLKSEL_ULFRCO (_BURTC_CTRL_CLKSEL_ULFRCO << 12) /* Shifted mode ULFRCO for BURTC_CTRL */
#define BURTC_CTRL_BUMODETSEN (0x1UL << 14) /* Backup mode timestamp enable */
#define _BURTC_CTRL_BUMODETSEN_SHIFT 14 /* Shift value for BURTC_BUMODETSEN */
#define _BURTC_CTRL_BUMODETSEN_MASK 0x4000UL /* Bit mask for BURTC_BUMODETSEN */
#define _BURTC_CTRL_BUMODETSEN_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CTRL */
#define BURTC_CTRL_BUMODETSEN_DEFAULT (_BURTC_CTRL_BUMODETSEN_DEFAULT << 14) /* Shifted mode DEFAULT for BURTC_CTRL */
/* Bit fields for BURTC LPMODE */
#define _BURTC_LPMODE_RESETVALUE 0x00000000UL /* Default value for BURTC_LPMODE */
#define _BURTC_LPMODE_MASK 0x00000003UL /* Mask for BURTC_LPMODE */
#define _BURTC_LPMODE_LPMODE_SHIFT 0 /* Shift value for BURTC_LPMODE */
#define _BURTC_LPMODE_LPMODE_MASK 0x3UL /* Bit mask for BURTC_LPMODE */
#define _BURTC_LPMODE_LPMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_LPMODE */
#define _BURTC_LPMODE_LPMODE_DISABLE 0x00000000UL /* Mode DISABLE for BURTC_LPMODE */
#define _BURTC_LPMODE_LPMODE_ENABLE 0x00000001UL /* Mode ENABLE for BURTC_LPMODE */
#define _BURTC_LPMODE_LPMODE_BUEN 0x00000002UL /* Mode BUEN for BURTC_LPMODE */
#define BURTC_LPMODE_LPMODE_DEFAULT (_BURTC_LPMODE_LPMODE_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_LPMODE */
#define BURTC_LPMODE_LPMODE_DISABLE (_BURTC_LPMODE_LPMODE_DISABLE << 0) /* Shifted mode DISABLE for BURTC_LPMODE */
#define BURTC_LPMODE_LPMODE_ENABLE (_BURTC_LPMODE_LPMODE_ENABLE << 0) /* Shifted mode ENABLE for BURTC_LPMODE */
#define BURTC_LPMODE_LPMODE_BUEN (_BURTC_LPMODE_LPMODE_BUEN << 0) /* Shifted mode BUEN for BURTC_LPMODE */
/* Bit fields for BURTC CNT */
#define _BURTC_CNT_RESETVALUE 0x00000000UL /* Default value for BURTC_CNT */
#define _BURTC_CNT_MASK 0xFFFFFFFFUL /* Mask for BURTC_CNT */
#define _BURTC_CNT_CNT_SHIFT 0 /* Shift value for BURTC_CNT */
#define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /* Bit mask for BURTC_CNT */
#define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CNT */
#define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_CNT */
/* Bit fields for BURTC COMP0 */
#define _BURTC_COMP0_RESETVALUE 0x00000000UL /* Default value for BURTC_COMP0 */
#define _BURTC_COMP0_MASK 0xFFFFFFFFUL /* Mask for BURTC_COMP0 */
#define _BURTC_COMP0_COMP0_SHIFT 0 /* Shift value for BURTC_COMP0 */
#define _BURTC_COMP0_COMP0_MASK 0xFFFFFFFFUL /* Bit mask for BURTC_COMP0 */
#define _BURTC_COMP0_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_COMP0 */
#define BURTC_COMP0_COMP0_DEFAULT (_BURTC_COMP0_COMP0_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_COMP0 */
/* Bit fields for BURTC TIMESTAMP */
#define _BURTC_TIMESTAMP_RESETVALUE 0x00000000UL /* Default value for BURTC_TIMESTAMP */
#define _BURTC_TIMESTAMP_MASK 0xFFFFFFFFUL /* Mask for BURTC_TIMESTAMP */
#define _BURTC_TIMESTAMP_TIMESTAMP_SHIFT 0 /* Shift value for BURTC_TIMESTAMP */
#define _BURTC_TIMESTAMP_TIMESTAMP_MASK 0xFFFFFFFFUL /* Bit mask for BURTC_TIMESTAMP */
#define _BURTC_TIMESTAMP_TIMESTAMP_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_TIMESTAMP */
#define BURTC_TIMESTAMP_TIMESTAMP_DEFAULT (_BURTC_TIMESTAMP_TIMESTAMP_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_TIMESTAMP */
/* Bit fields for BURTC LFXOFDET */
#define _BURTC_LFXOFDET_RESETVALUE 0x00000000UL /* Default value for BURTC_LFXOFDET */
#define _BURTC_LFXOFDET_MASK 0x000001F3UL /* Mask for BURTC_LFXOFDET */
#define _BURTC_LFXOFDET_OSC_SHIFT 0 /* Shift value for BURTC_OSC */
#define _BURTC_LFXOFDET_OSC_MASK 0x3UL /* Bit mask for BURTC_OSC */
#define _BURTC_LFXOFDET_OSC_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_LFXOFDET */
#define _BURTC_LFXOFDET_OSC_DISABLE 0x00000000UL /* Mode DISABLE for BURTC_LFXOFDET */
#define _BURTC_LFXOFDET_OSC_LFRCO 0x00000001UL /* Mode LFRCO for BURTC_LFXOFDET */
#define _BURTC_LFXOFDET_OSC_ULFRCO 0x00000002UL /* Mode ULFRCO for BURTC_LFXOFDET */
#define BURTC_LFXOFDET_OSC_DEFAULT (_BURTC_LFXOFDET_OSC_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_LFXOFDET */
#define BURTC_LFXOFDET_OSC_DISABLE (_BURTC_LFXOFDET_OSC_DISABLE << 0) /* Shifted mode DISABLE for BURTC_LFXOFDET */
#define BURTC_LFXOFDET_OSC_LFRCO (_BURTC_LFXOFDET_OSC_LFRCO << 0) /* Shifted mode LFRCO for BURTC_LFXOFDET */
#define BURTC_LFXOFDET_OSC_ULFRCO (_BURTC_LFXOFDET_OSC_ULFRCO << 0) /* Shifted mode ULFRCO for BURTC_LFXOFDET */
#define _BURTC_LFXOFDET_TOP_SHIFT 4 /* Shift value for BURTC_TOP */
#define _BURTC_LFXOFDET_TOP_MASK 0x1F0UL /* Bit mask for BURTC_TOP */
#define _BURTC_LFXOFDET_TOP_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_LFXOFDET */
#define BURTC_LFXOFDET_TOP_DEFAULT (_BURTC_LFXOFDET_TOP_DEFAULT << 4) /* Shifted mode DEFAULT for BURTC_LFXOFDET */
/* Bit fields for BURTC STATUS */
#define _BURTC_STATUS_RESETVALUE 0x00000000UL /* Default value for BURTC_STATUS */
#define _BURTC_STATUS_MASK 0x00000007UL /* Mask for BURTC_STATUS */
#define BURTC_STATUS_LPMODEACT (0x1UL << 0) /* Low power mode active */
#define _BURTC_STATUS_LPMODEACT_SHIFT 0 /* Shift value for BURTC_LPMODEACT */
#define _BURTC_STATUS_LPMODEACT_MASK 0x1UL /* Bit mask for BURTC_LPMODEACT */
#define _BURTC_STATUS_LPMODEACT_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_STATUS */
#define BURTC_STATUS_LPMODEACT_DEFAULT (_BURTC_STATUS_LPMODEACT_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_STATUS */
#define BURTC_STATUS_BUMODETS (0x1UL << 1) /* Timestamp for backup mode entry stored. */
#define _BURTC_STATUS_BUMODETS_SHIFT 1 /* Shift value for BURTC_BUMODETS */
#define _BURTC_STATUS_BUMODETS_MASK 0x2UL /* Bit mask for BURTC_BUMODETS */
#define _BURTC_STATUS_BUMODETS_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_STATUS */
#define BURTC_STATUS_BUMODETS_DEFAULT (_BURTC_STATUS_BUMODETS_DEFAULT << 1) /* Shifted mode DEFAULT for BURTC_STATUS */
#define BURTC_STATUS_RAMWERR (0x1UL << 2) /* RAM write error. */
#define _BURTC_STATUS_RAMWERR_SHIFT 2 /* Shift value for BURTC_RAMWERR */
#define _BURTC_STATUS_RAMWERR_MASK 0x4UL /* Bit mask for BURTC_RAMWERR */
#define _BURTC_STATUS_RAMWERR_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_STATUS */
#define BURTC_STATUS_RAMWERR_DEFAULT (_BURTC_STATUS_RAMWERR_DEFAULT << 2) /* Shifted mode DEFAULT for BURTC_STATUS */
/* Bit fields for BURTC CMD */
#define _BURTC_CMD_RESETVALUE 0x00000000UL /* Default value for BURTC_CMD */
#define _BURTC_CMD_MASK 0x00000001UL /* Mask for BURTC_CMD */
#define BURTC_CMD_CLRSTATUS (0x1UL << 0) /* Clear BURTC_STATUS register. */
#define _BURTC_CMD_CLRSTATUS_SHIFT 0 /* Shift value for BURTC_CLRSTATUS */
#define _BURTC_CMD_CLRSTATUS_MASK 0x1UL /* Bit mask for BURTC_CLRSTATUS */
#define _BURTC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_CMD */
#define BURTC_CMD_CLRSTATUS_DEFAULT (_BURTC_CMD_CLRSTATUS_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_CMD */
/* Bit fields for BURTC POWERDOWN */
#define _BURTC_POWERDOWN_RESETVALUE 0x00000000UL /* Default value for BURTC_POWERDOWN */
#define _BURTC_POWERDOWN_MASK 0x00000001UL /* Mask for BURTC_POWERDOWN */
#define BURTC_POWERDOWN_RAM (0x1UL << 0) /* Retention RAM power-down */
#define _BURTC_POWERDOWN_RAM_SHIFT 0 /* Shift value for BURTC_RAM */
#define _BURTC_POWERDOWN_RAM_MASK 0x1UL /* Bit mask for BURTC_RAM */
#define _BURTC_POWERDOWN_RAM_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_POWERDOWN */
#define BURTC_POWERDOWN_RAM_DEFAULT (_BURTC_POWERDOWN_RAM_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_POWERDOWN */
/* Bit fields for BURTC LOCK */
#define _BURTC_LOCK_RESETVALUE 0x00000000UL /* Default value for BURTC_LOCK */
#define _BURTC_LOCK_MASK 0x0000FFFFUL /* Mask for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_SHIFT 0 /* Shift value for BURTC_LOCKKEY */
#define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /* Bit mask for BURTC_LOCKKEY */
#define _BURTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_LOCK 0x00000000UL /* Mode LOCK for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /* Mode UNLOCKED for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_LOCKED 0x00000001UL /* Mode LOCKED for BURTC_LOCK */
#define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /* Mode UNLOCK for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_LOCK (_BURTC_LOCK_LOCKKEY_LOCK << 0) /* Shifted mode LOCK for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_UNLOCKED (_BURTC_LOCK_LOCKKEY_UNLOCKED << 0) /* Shifted mode UNLOCKED for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_LOCKED (_BURTC_LOCK_LOCKKEY_LOCKED << 0) /* Shifted mode LOCKED for BURTC_LOCK */
#define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /* Shifted mode UNLOCK for BURTC_LOCK */
/* Bit fields for BURTC IF */
#define _BURTC_IF_RESETVALUE 0x00000000UL /* Default value for BURTC_IF */
#define _BURTC_IF_MASK 0x00000007UL /* Mask for BURTC_IF */
#define BURTC_IF_OF (0x1UL << 0) /* Overflow Interrupt Flag */
#define _BURTC_IF_OF_SHIFT 0 /* Shift value for BURTC_OF */
#define _BURTC_IF_OF_MASK 0x1UL /* Bit mask for BURTC_OF */
#define _BURTC_IF_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IF */
#define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_IF */
#define BURTC_IF_COMP0 (0x1UL << 1) /* Compare match Interrupt Flag */
#define _BURTC_IF_COMP0_SHIFT 1 /* Shift value for BURTC_COMP0 */
#define _BURTC_IF_COMP0_MASK 0x2UL /* Bit mask for BURTC_COMP0 */
#define _BURTC_IF_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IF */
#define BURTC_IF_COMP0_DEFAULT (_BURTC_IF_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for BURTC_IF */
#define BURTC_IF_LFXOFAIL (0x1UL << 2) /* LFXO failure Interrupt Flag */
#define _BURTC_IF_LFXOFAIL_SHIFT 2 /* Shift value for BURTC_LFXOFAIL */
#define _BURTC_IF_LFXOFAIL_MASK 0x4UL /* Bit mask for BURTC_LFXOFAIL */
#define _BURTC_IF_LFXOFAIL_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IF */
#define BURTC_IF_LFXOFAIL_DEFAULT (_BURTC_IF_LFXOFAIL_DEFAULT << 2) /* Shifted mode DEFAULT for BURTC_IF */
/* Bit fields for BURTC IFS */
#define _BURTC_IFS_RESETVALUE 0x00000000UL /* Default value for BURTC_IFS */
#define _BURTC_IFS_MASK 0x00000007UL /* Mask for BURTC_IFS */
#define BURTC_IFS_OF (0x1UL << 0) /* Set Overflow Interrupt Flag */
#define _BURTC_IFS_OF_SHIFT 0 /* Shift value for BURTC_OF */
#define _BURTC_IFS_OF_MASK 0x1UL /* Bit mask for BURTC_OF */
#define _BURTC_IFS_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IFS */
#define BURTC_IFS_OF_DEFAULT (_BURTC_IFS_OF_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_IFS */
#define BURTC_IFS_COMP0 (0x1UL << 1) /* Set compare match Interrupt Flag */
#define _BURTC_IFS_COMP0_SHIFT 1 /* Shift value for BURTC_COMP0 */
#define _BURTC_IFS_COMP0_MASK 0x2UL /* Bit mask for BURTC_COMP0 */
#define _BURTC_IFS_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IFS */
#define BURTC_IFS_COMP0_DEFAULT (_BURTC_IFS_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for BURTC_IFS */
#define BURTC_IFS_LFXOFAIL (0x1UL << 2) /* Set LFXO fail Interrupt Flag */
#define _BURTC_IFS_LFXOFAIL_SHIFT 2 /* Shift value for BURTC_LFXOFAIL */
#define _BURTC_IFS_LFXOFAIL_MASK 0x4UL /* Bit mask for BURTC_LFXOFAIL */
#define _BURTC_IFS_LFXOFAIL_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IFS */
#define BURTC_IFS_LFXOFAIL_DEFAULT (_BURTC_IFS_LFXOFAIL_DEFAULT << 2) /* Shifted mode DEFAULT for BURTC_IFS */
/* Bit fields for BURTC IFC */
#define _BURTC_IFC_RESETVALUE 0x00000000UL /* Default value for BURTC_IFC */
#define _BURTC_IFC_MASK 0x00000007UL /* Mask for BURTC_IFC */
#define BURTC_IFC_OF (0x1UL << 0) /* Clear Overflow Interrupt Flag */
#define _BURTC_IFC_OF_SHIFT 0 /* Shift value for BURTC_OF */
#define _BURTC_IFC_OF_MASK 0x1UL /* Bit mask for BURTC_OF */
#define _BURTC_IFC_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IFC */
#define BURTC_IFC_OF_DEFAULT (_BURTC_IFC_OF_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_IFC */
#define BURTC_IFC_COMP0 (0x1UL << 1) /* Clear compare match Interrupt Flag */
#define _BURTC_IFC_COMP0_SHIFT 1 /* Shift value for BURTC_COMP0 */
#define _BURTC_IFC_COMP0_MASK 0x2UL /* Bit mask for BURTC_COMP0 */
#define _BURTC_IFC_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IFC */
#define BURTC_IFC_COMP0_DEFAULT (_BURTC_IFC_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for BURTC_IFC */
#define BURTC_IFC_LFXOFAIL (0x1UL << 2) /* Clear LFXO failure Interrupt Flag */
#define _BURTC_IFC_LFXOFAIL_SHIFT 2 /* Shift value for BURTC_LFXOFAIL */
#define _BURTC_IFC_LFXOFAIL_MASK 0x4UL /* Bit mask for BURTC_LFXOFAIL */
#define _BURTC_IFC_LFXOFAIL_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IFC */
#define BURTC_IFC_LFXOFAIL_DEFAULT (_BURTC_IFC_LFXOFAIL_DEFAULT << 2) /* Shifted mode DEFAULT for BURTC_IFC */
/* Bit fields for BURTC IEN */
#define _BURTC_IEN_RESETVALUE 0x00000000UL /* Default value for BURTC_IEN */
#define _BURTC_IEN_MASK 0x00000007UL /* Mask for BURTC_IEN */
#define BURTC_IEN_OF (0x1UL << 0) /* Overflow Interrupt Enable */
#define _BURTC_IEN_OF_SHIFT 0 /* Shift value for BURTC_OF */
#define _BURTC_IEN_OF_MASK 0x1UL /* Bit mask for BURTC_OF */
#define _BURTC_IEN_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IEN */
#define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_IEN */
#define BURTC_IEN_COMP0 (0x1UL << 1) /* Compare match Interrupt Enable */
#define _BURTC_IEN_COMP0_SHIFT 1 /* Shift value for BURTC_COMP0 */
#define _BURTC_IEN_COMP0_MASK 0x2UL /* Bit mask for BURTC_COMP0 */
#define _BURTC_IEN_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IEN */
#define BURTC_IEN_COMP0_DEFAULT (_BURTC_IEN_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for BURTC_IEN */
#define BURTC_IEN_LFXOFAIL (0x1UL << 2) /* LFXO failure Interrupt Enable */
#define _BURTC_IEN_LFXOFAIL_SHIFT 2 /* Shift value for BURTC_LFXOFAIL */
#define _BURTC_IEN_LFXOFAIL_MASK 0x4UL /* Bit mask for BURTC_LFXOFAIL */
#define _BURTC_IEN_LFXOFAIL_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_IEN */
#define BURTC_IEN_LFXOFAIL_DEFAULT (_BURTC_IEN_LFXOFAIL_DEFAULT << 2) /* Shifted mode DEFAULT for BURTC_IEN */
/* Bit fields for BURTC FREEZE */
#define _BURTC_FREEZE_RESETVALUE 0x00000000UL /* Default value for BURTC_FREEZE */
#define _BURTC_FREEZE_MASK 0x00000001UL /* Mask for BURTC_FREEZE */
#define BURTC_FREEZE_REGFREEZE (0x1UL << 0) /* Register Update Freeze */
#define _BURTC_FREEZE_REGFREEZE_SHIFT 0 /* Shift value for BURTC_REGFREEZE */
#define _BURTC_FREEZE_REGFREEZE_MASK 0x1UL /* Bit mask for BURTC_REGFREEZE */
#define _BURTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_FREEZE */
#define _BURTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /* Mode UPDATE for BURTC_FREEZE */
#define _BURTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /* Mode FREEZE for BURTC_FREEZE */
#define BURTC_FREEZE_REGFREEZE_DEFAULT (_BURTC_FREEZE_REGFREEZE_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_FREEZE */
#define BURTC_FREEZE_REGFREEZE_UPDATE (_BURTC_FREEZE_REGFREEZE_UPDATE << 0) /* Shifted mode UPDATE for BURTC_FREEZE */
#define BURTC_FREEZE_REGFREEZE_FREEZE (_BURTC_FREEZE_REGFREEZE_FREEZE << 0) /* Shifted mode FREEZE for BURTC_FREEZE */
/* Bit fields for BURTC SYNCBUSY */
#define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /* Default value for BURTC_SYNCBUSY */
#define _BURTC_SYNCBUSY_MASK 0x00000003UL /* Mask for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_LPMODE (0x1UL << 0) /* LPMODE Register Busy */
#define _BURTC_SYNCBUSY_LPMODE_SHIFT 0 /* Shift value for BURTC_LPMODE */
#define _BURTC_SYNCBUSY_LPMODE_MASK 0x1UL /* Bit mask for BURTC_LPMODE */
#define _BURTC_SYNCBUSY_LPMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_LPMODE_DEFAULT (_BURTC_SYNCBUSY_LPMODE_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_COMP0 (0x1UL << 1) /* COMP0 Register Busy */
#define _BURTC_SYNCBUSY_COMP0_SHIFT 1 /* Shift value for BURTC_COMP0 */
#define _BURTC_SYNCBUSY_COMP0_MASK 0x2UL /* Bit mask for BURTC_COMP0 */
#define _BURTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_SYNCBUSY */
#define BURTC_SYNCBUSY_COMP0_DEFAULT (_BURTC_SYNCBUSY_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for BURTC_SYNCBUSY */
/* Bit fields for BURTC RET_REG */
#define _BURTC_RET_REG_RESETVALUE 0x00000000UL /* Default value for BURTC_RET_REG */
#define _BURTC_RET_REG_MASK 0xFFFFFFFFUL /* Mask for BURTC_RET_REG */
#define _BURTC_RET_REG_REG_SHIFT 0 /* Shift value for REG */
#define _BURTC_RET_REG_REG_MASK 0xFFFFFFFFUL /* Bit mask for REG */
#define _BURTC_RET_REG_REG_DEFAULT 0x00000000UL /* Mode DEFAULT for BURTC_RET_REG */
#define BURTC_RET_REG_REG_DEFAULT (_BURTC_RET_REG_REG_DEFAULT << 0) /* Shifted mode DEFAULT for BURTC_RET_REG */
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_BURTC_H */
arch/arm/src/efm32/chip/efm32_calibrate.h
+93
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@@ -0,0 +1,93 @@
/*******************************************************************************************************************************
* arch/arm/src/efm32/chip/efm32_calibrate.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Authors: Pierre-noel Bouteville <pnb990@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CALIBRATE_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CALIBRATE_H
/*******************************************************************************************************************************
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG)
# warning This is the EFM32GG header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
#define CALIBRATE_MAX_REGISTERS 50 /* Max number of address/value pairs for calibration */
#define CALIBRATE ((const struct efm32_calibrate_s *)EFM32_CALIBRATE_BASE)
/*******************************************************************************************************************************
* Public Type Definitions
*******************************************************************************************************************************/
struct efm32_calibrate_s
{
const uint32_t address; /* Address of calibration register */
const uint32_t value; /* Default value for calibration register */
};
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_CALIBRATE_H */
arch/arm/src/efm32/chip/efm32_cmu.h
+5
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@@ -65,8 +65,13 @@
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG) && !defined(CONFIG_EFM32_EFM32G)
# warning This is the EFM32GG/G header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
arch/arm/src/efm32/chip/efm32_dac.h
+883
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arch/arm/src/efm32/chip/efm32_devinfo.h
+213
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@@ -0,0 +1,213 @@
/*******************************************************************************************************************************
* arch/arm/src/efm32/chip/efm32_devinfo.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Authors: Pierre-noel Bouteville <pnb990@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DEVINFO_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DEVINFO_H
/*******************************************************************************************************************************
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG)
# warning This is the EFM32GG header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
#define DEVINFO ((const struct efm32_devinfo_s *)EFM32_DEVINFO_BASE)
/* Bit fields for struct efm32_devinfo_s */
#define _DEVINFO_CAL_CRC_MASK 0x0000FFFFUL /* Integrity CRC checksum mask */
#define _DEVINFO_CAL_CRC_SHIFT 0 /* Integrity CRC checksum shift */
#define _DEVINFO_CAL_TEMP_MASK 0x00FF0000UL /* Calibration temperature, DegC, mask */
#define _DEVINFO_CAL_TEMP_SHIFT 16 /* Calibration temperature shift */
#define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK 0x00007F00UL /* Gain for 1V25 reference, mask */
#define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT 8 /* Gain for 1V25 reference, shift */
#define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK 0x0000007FUL /* Offset for 1V25 reference, mask */
#define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT 0 /* Offset for 1V25 reference, shift */
#define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK 0x7F000000UL /* Gain for 2V5 reference, mask */
#define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT 24 /* Gain for 2V5 reference, shift */
#define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK 0x007F0000UL /* Offset for 2V5 reference, mask */
#define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT 16 /* Offset for 2V5 reference, shift */
#define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK 0x00007F00UL /* Gain for VDD reference, mask */
#define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT 8 /* Gain for VDD reference, shift */
#define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK 0x0000007FUL /* Offset for VDD reference, mask */
#define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT 0 /* Offset for VDD reference, shift */
#define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK 0x7F000000UL /* Gain 5VDIFF for 5VDIFF reference, mask */
#define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT 24 /* Gain for 5VDIFF reference, mask */
#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK 0x007F0000UL /* Offset for 5VDIFF reference, mask */
#define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT 16 /* Offset for 5VDIFF reference, shift */
#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK 0x0000007FUL /* Offset for 2XVDDVSS reference, mask */
#define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT 0 /* Offset for 2XVDDVSS reference, shift */
#define _DEVINFO_ADC0CAL2_TEMP1V25_MASK 0xFFF00000UL /* Temperature reading at 1V25 reference, mask */
#define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT 20 /* Temperature reading at 1V25 reference, DegC */
#define _DEVINFO_DAC0CAL0_1V25_GAIN_MASK 0x007F0000UL /* Gain for 1V25 reference, mask */
#define _DEVINFO_DAC0CAL0_1V25_GAIN_SHIFT 16 /* Gain for 1V25 reference, shift */
#define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_MASK 0x00003F00UL /* Channel 1 offset for 1V25 reference, mask */
#define _DEVINFO_DAC0CAL0_1V25_CH1_OFFSET_SHIFT 8 /* Channel 1 offset for 1V25 reference, shift */
#define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_MASK 0x0000003FUL /* Channel 0 offset for 1V25 reference, mask */
#define _DEVINFO_DAC0CAL0_1V25_CH0_OFFSET_SHIFT 0 /* Channel 0 offset for 1V25 reference, shift */
#define _DEVINFO_DAC0CAL1_2V5_GAIN_MASK 0x007F0000UL /* Gain for 2V5 reference, mask */
#define _DEVINFO_DAC0CAL1_2V5_GAIN_SHIFT 16 /* Gain for 2V5 reference, shift */
#define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_MASK 0x00003F00UL /* Channel 1 offset for 2V5 reference, mask */
#define _DEVINFO_DAC0CAL1_2V5_CH1_OFFSET_SHIFT 8 /* Channel 1 offset for 2V5 reference, shift */
#define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_MASK 0x0000003FUL /* Channel 0 offset for 2V5 reference, mask */
#define _DEVINFO_DAC0CAL1_2V5_CH0_OFFSET_SHIFT 0 /* Channel 0 offset for 2V5 reference, shift */
#define _DEVINFO_DAC0CAL2_VDD_GAIN_MASK 0x007F0000UL /* Gain for VDD reference, mask */
#define _DEVINFO_DAC0CAL2_VDD_GAIN_SHIFT 16 /* Gain for VDD reference, shift */
#define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_MASK 0x00003F00UL /* Channel 1 offset for VDD reference, mask */
#define _DEVINFO_DAC0CAL2_VDD_CH1_OFFSET_SHIFT 8 /* Channel 1 offset for VDD reference, shift */
#define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_MASK 0x0000003FUL /* Channel 0 offset for VDD reference, mask */
#define _DEVINFO_DAC0CAL2_VDD_CH0_OFFSET_SHIFT 0 /* Channel 0 offset for VDD reference, shift*/
#define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK 0x000000FFUL /* 1MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT 0 /* 1MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK 0x0000FF00UL /* 7MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT 8 /* 7MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK 0x00FF0000UL /* 11MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT 16 /* 11MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK 0xFF000000UL /* 14MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT 24 /* 14MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK 0x000000FFUL /* 21MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT 0 /* 21MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL1_BAND28_MASK 0x0000FF00UL /* 28MHz tuning value for AUXHFRCO, shift */
#define _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT 8 /* 28MHz tuning value for AUXHFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND1_MASK 0x000000FFUL /* 1MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND1_SHIFT 0 /* 1MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL0_BAND7_MASK 0x0000FF00UL /* 7MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND7_SHIFT 8 /* 7MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL0_BAND11_MASK 0x00FF0000UL /* 11MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND11_SHIFT 16 /* 11MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL0_BAND14_MASK 0xFF000000UL /* 14MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL0_BAND14_SHIFT 24 /* 14MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL1_BAND21_MASK 0x000000FFUL /* 21MHz tuning value for HFRCO, mask */
#define _DEVINFO_HFRCOCAL1_BAND21_SHIFT 0 /* 21MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL1_BAND28_MASK 0x0000FF00UL /* 28MHz tuning value for HFRCO, shift */
#define _DEVINFO_HFRCOCAL1_BAND28_SHIFT 8 /* 28MHz tuning value for HFRCO, mask */
#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /* Flash page size (refer to ref.man for encoding) mask */
#define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /* Flash page size shift */
#define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /* Lower part of 64-bit device unique number */
#define _DEVINFO_UNIQUEL_SHIFT 0 /* Unique Low 32-bit shift */
#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /* High part of 64-bit device unique number */
#define _DEVINFO_UNIQUEH_SHIFT 0 /* Unique High 32-bit shift */
#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /* Flash size in kilobytes */
#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /* Bit position for flash size */
#define _DEVINFO_MSIZE_FLASH_MASK 0x0000FFFFUL /* SRAM size in kilobytes */
#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /* Bit position for SRAM size */
#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /* Production revision */
#define _DEVINFO_PART_PROD_REV_SHIFT 24 /* Bit position for production revision */
#define _DEVINFO_PART_DEVICE_FAMILY_MASK 0x00FF0000UL /* Device Family, 0x47 for Gecko */
#define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /* Bit position for device family */
#define _DEVINFO_PART_DEVICE_FAMILY_G 71 /* Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_GG 72 /* Giant Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_TG 73 /* Tiny Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_LG 74 /* Leopard Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_WG 75 /* Wonder Gecko Device Family */
#define _DEVINFO_PART_DEVICE_FAMILY_ZG 76 /* Zero Gecko Device Family */
#define _DEVINFO_PART_DEVICE_NUMBER_MASK 0x0000FFFFUL /* Device number */
#define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /* Bit position for device number */
/*******************************************************************************************************************************
* Public Type Definitions
*******************************************************************************************************************************/
struct efm32_devinfo_s
{
const uint32_t cal; /* Calibration temperature and checksum */
const uint32_t adc0cal0; /* ADC0 Calibration register 0 */
const uint32_t adc0cal1; /* ADC0 Calibration register 1 */
const uint32_t adc0cal2; /* ADC0 Calibration register 2 */
uint32_t reserved0[2]; /* Reserved */
const uint32_t dac0cal0; /* DAC calibration register 0 */
const uint32_t dac0cal1; /* DAC calibration register 1 */
const uint32_t dac0cal2; /* DAC calibration register 2 */
const uint32_t auxhfrcocal0; /* AUXHFRCO calibration register 0 */
const uint32_t auxhfrcocal1; /* AUXHFRCO calibration register 1 */
const uint32_t hfrcocal0; /* HFRCO calibration register 0 */
const uint32_t hfrcocal1; /* HFRCO calibration register 1 */
const uint32_t meminfo; /* Memory information */
uint32_t reserved2[2]; /* Reserved */
const uint32_t uniquel; /* Low 32 bits of device unique number */
const uint32_t uniqueh; /* High 32 bits of device unique number */
const uint32_t msize; /* Flash and SRAM Memory size in KiloBytes */
const uint32_t part; /* Part description */
};
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DEVINFO_H */
arch/arm/src/efm32/chip/efm32_dma.h
+5
View File
@@ -65,8 +65,13 @@
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG) && !defined(CONFIG_EFM32_EFM32G)
# warning This is the EFM32GG/G header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
arch/arm/src/efm32/chip/efm32_emu.h
+442
View File
@@ -0,0 +1,442 @@
/*******************************************************************************************************************************
* arch/arm/src/efm32/chip/efm32_emu.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Authors: Pierre-noel Bouteville <pnb990@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_EMU_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_EMU_H
/*******************************************************************************************************************************
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG)
# warning This is the EFM32GG header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* EMU Register Offsets ********************************************************************************************************/
#define EFM32_EMU_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_EMU_MEMCTRL_OFFSET 0x0004 /* Memory Control Register */
#define EFM32_EMU_LOCK_OFFSET 0x0008 /* Configuration Lock Register */
#define EFM32_EMU_AUXCTRL_OFFSET 0x0024 /* Auxiliary Control Register */
#define EFM32_EMU_EM4CONF_OFFSET 0x002c /* Energy mode 4 configuration register */
#define EFM32_EMU_BUCTRL_OFFSET 0x0030 /* Backup Power configuration register */
#define EFM32_EMU_PWRCONF_OFFSET 0x0034 /* Power connection configuration register */
#define EFM32_EMU_BUINACT_OFFSET 0x0038 /* Backup mode inactive configuration register */
#define EFM32_EMU_BUACT_OFFSET 0x003c /* Backup mode active configuration register */
#define EFM32_EMU_STATUS_OFFSET 0x0040 /* status register */
#define EFM32_EMU_ROUTE_OFFSET 0x0044 /* I/O Routing Register */
#define EFM32_EMU_IF_OFFSET 0x0048 /* Interrupt Flag Register */
#define EFM32_EMU_IFS_OFFSET 0x004c /* Interrupt Flag Set Register */
#define EFM32_EMU_IFC_OFFSET 0x0050 /* Interrupt Flag Clear Register */
#define EFM32_EMU_IEN_OFFSET 0x0054 /* Interrupt Enable Register */
#define EFM32_EMU_BUBODBUVINCAL_OFFSET 0x0058 /* BU_VIN Backup BOD calibration */
#define EFM32_EMU_BUBODUNREGCAL_OFFSET 0x005c /* Unregulated power Backup BOD calibration */
/* EMU Register Addresses ******************************************************************************************************/
#define EFM32_EMU_CTRL (EFM32_EMU_BASE+EFM32_EMU_CTRL_OFFSET)
#define EFM32_EMU_MEMCTRL (EFM32_EMU_BASE+EFM32_EMU_MEMCTRL_OFFSET)
#define EFM32_EMU_LOCK (EFM32_EMU_BASE+EFM32_EMU_LOCK_OFFSET)
#define EFM32_EMU_AUXCTRL (EFM32_EMU_BASE+EFM32_EMU_AUXCTRL_OFFSET)
#define EFM32_EMU_EM4CONF (EFM32_EMU_BASE+EFM32_EMU_EM4CONF_OFFSET)
#define EFM32_EMU_BUCTRL (EFM32_EMU_BASE+EFM32_EMU_BUCTRL_OFFSET)
#define EFM32_EMU_PWRCONF (EFM32_EMU_BASE+EFM32_EMU_PWRCONF_OFFSET)
#define EFM32_EMU_BUINACT (EFM32_EMU_BASE+EFM32_EMU_BUINACT_OFFSET)
#define EFM32_EMU_BUACT (EFM32_EMU_BASE+EFM32_EMU_BUACT_OFFSET)
#define EFM32_EMU_STATUS (EFM32_EMU_BASE+EFM32_EMU_STATUS_OFFSET)
#define EFM32_EMU_ROUTE (EFM32_EMU_BASE+EFM32_EMU_ROUTE_OFFSET)
#define EFM32_EMU_IF (EFM32_EMU_BASE+EFM32_EMU_IF_OFFSET)
#define EFM32_EMU_IFS (EFM32_EMU_BASE+EFM32_EMU_IFS_OFFSET)
#define EFM32_EMU_IFC (EFM32_EMU_BASE+EFM32_EMU_IFC_OFFSET)
#define EFM32_EMU_IEN (EFM32_EMU_BASE+EFM32_EMU_IEN_OFFSET)
#define EFM32_EMU_BUBODBUVINCAL (EFM32_EMU_BASE+EFM32_EMU_BUBODBUVINCAL_OFFSET)
#define EFM32_EMU_BUBODUNREGCAL (EFM32_EMU_BASE+EFM32_EMU_BUBODUNREGCAL_OFFSET)
/* EMU Register Bit Field Definitions ******************************************************************************************/
/* Bit fields for EMU CTRL */
#define _EMU_CTRL_RESETVALUE 0x00000000UL /* Default value for EMU_CTRL */
#define _EMU_CTRL_MASK 0x0000000FUL /* Mask for EMU_CTRL */
#define EMU_CTRL_EMVREG (0x1UL << 0) /* Energy Mode Voltage Regulator Control */
#define _EMU_CTRL_EMVREG_SHIFT 0 /* Shift value for EMU_EMVREG */
#define _EMU_CTRL_EMVREG_MASK 0x1UL /* Bit mask for EMU_EMVREG */
#define _EMU_CTRL_EMVREG_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_CTRL */
#define _EMU_CTRL_EMVREG_REDUCED 0x00000000UL /* Mode REDUCED for EMU_CTRL */
#define _EMU_CTRL_EMVREG_FULL 0x00000001UL /* Mode FULL for EMU_CTRL */
#define EMU_CTRL_EMVREG_DEFAULT (_EMU_CTRL_EMVREG_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_EMVREG_REDUCED (_EMU_CTRL_EMVREG_REDUCED << 0) /* Shifted mode REDUCED for EMU_CTRL */
#define EMU_CTRL_EMVREG_FULL (_EMU_CTRL_EMVREG_FULL << 0) /* Shifted mode FULL for EMU_CTRL */
#define EMU_CTRL_EM2BLOCK (0x1UL << 1) /* Energy Mode 2 Block */
#define _EMU_CTRL_EM2BLOCK_SHIFT 1 /* Shift value for EMU_EM2BLOCK */
#define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /* Bit mask for EMU_EM2BLOCK */
#define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /* Shifted mode DEFAULT for EMU_CTRL */
#define _EMU_CTRL_EM4CTRL_SHIFT 2 /* Shift value for EMU_EM4CTRL */
#define _EMU_CTRL_EM4CTRL_MASK 0xCUL /* Bit mask for EMU_EM4CTRL */
#define _EMU_CTRL_EM4CTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_CTRL */
#define EMU_CTRL_EM4CTRL_DEFAULT (_EMU_CTRL_EM4CTRL_DEFAULT << 2) /* Shifted mode DEFAULT for EMU_CTRL */
/* Bit fields for EMU MEMCTRL */
#define _EMU_MEMCTRL_RESETVALUE 0x00000000UL /* Default value for EMU_MEMCTRL */
#define _EMU_MEMCTRL_MASK 0x00000007UL /* Mask for EMU_MEMCTRL */
#define _EMU_MEMCTRL_POWERDOWN_SHIFT 0 /* Shift value for EMU_POWERDOWN */
#define _EMU_MEMCTRL_POWERDOWN_MASK 0x7UL /* Bit mask for EMU_POWERDOWN */
#define _EMU_MEMCTRL_POWERDOWN_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_MEMCTRL */
#define _EMU_MEMCTRL_POWERDOWN_BLK3 0x00000004UL /* Mode BLK3 for EMU_MEMCTRL */
#define _EMU_MEMCTRL_POWERDOWN_BLK23 0x00000006UL /* Mode BLK23 for EMU_MEMCTRL */
#define _EMU_MEMCTRL_POWERDOWN_BLK123 0x00000007UL /* Mode BLK123 for EMU_MEMCTRL */
#define EMU_MEMCTRL_POWERDOWN_DEFAULT (_EMU_MEMCTRL_POWERDOWN_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_MEMCTRL */
#define EMU_MEMCTRL_POWERDOWN_BLK3 (_EMU_MEMCTRL_POWERDOWN_BLK3 << 0) /* Shifted mode BLK3 for EMU_MEMCTRL */
#define EMU_MEMCTRL_POWERDOWN_BLK23 (_EMU_MEMCTRL_POWERDOWN_BLK23 << 0) /* Shifted mode BLK23 for EMU_MEMCTRL */
#define EMU_MEMCTRL_POWERDOWN_BLK123 (_EMU_MEMCTRL_POWERDOWN_BLK123 << 0) /* Shifted mode BLK123 for EMU_MEMCTRL */
/* Bit fields for EMU LOCK */
#define _EMU_LOCK_RESETVALUE 0x00000000UL /* Default value for EMU_LOCK */
#define _EMU_LOCK_MASK 0x0000FFFFUL /* Mask for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_SHIFT 0 /* Shift value for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /* Bit mask for EMU_LOCKKEY */
#define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /* Mode LOCK for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /* Mode UNLOCKED for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /* Mode LOCKED for EMU_LOCK */
#define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /* Mode UNLOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /* Shifted mode LOCK for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /* Shifted mode UNLOCKED for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /* Shifted mode LOCKED for EMU_LOCK */
#define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /* Shifted mode UNLOCK for EMU_LOCK */
/* Bit fields for EMU AUXCTRL */
#define _EMU_AUXCTRL_RESETVALUE 0x00000000UL /* Default value for EMU_AUXCTRL */
#define _EMU_AUXCTRL_MASK 0x00000101UL /* Mask for EMU_AUXCTRL */
#define EMU_AUXCTRL_HRCCLR (0x1UL << 0) /* Hard Reset Cause Clear */
#define _EMU_AUXCTRL_HRCCLR_SHIFT 0 /* Shift value for EMU_HRCCLR */
#define _EMU_AUXCTRL_HRCCLR_MASK 0x1UL /* Bit mask for EMU_HRCCLR */
#define _EMU_AUXCTRL_HRCCLR_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_AUXCTRL */
#define EMU_AUXCTRL_HRCCLR_DEFAULT (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_AUXCTRL */
#define EMU_AUXCTRL_REDLFXOBOOST (0x1UL << 8) /* Reduce LFXO Start-up Boost Current */
#define _EMU_AUXCTRL_REDLFXOBOOST_SHIFT 8 /* Shift value for EMU_REDLFXOBOOST */
#define _EMU_AUXCTRL_REDLFXOBOOST_MASK 0x100UL /* Bit mask for EMU_REDLFXOBOOST */
#define _EMU_AUXCTRL_REDLFXOBOOST_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_AUXCTRL */
#define EMU_AUXCTRL_REDLFXOBOOST_DEFAULT (_EMU_AUXCTRL_REDLFXOBOOST_DEFAULT << 8) /* Shifted mode DEFAULT for EMU_AUXCTRL */
/* Bit fields for EMU EM4CONF */
#define _EMU_EM4CONF_RESETVALUE 0x00000000UL /* Default value for EMU_EM4CONF */
#define _EMU_EM4CONF_MASK 0x0001001FUL /* Mask for EMU_EM4CONF */
#define EMU_EM4CONF_VREGEN (0x1UL << 0) /* EM4 voltage regulator enable */
#define _EMU_EM4CONF_VREGEN_SHIFT 0 /* Shift value for EMU_VREGEN */
#define _EMU_EM4CONF_VREGEN_MASK 0x1UL /* Bit mask for EMU_VREGEN */
#define _EMU_EM4CONF_VREGEN_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_EM4CONF */
#define EMU_EM4CONF_VREGEN_DEFAULT (_EMU_EM4CONF_VREGEN_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_EM4CONF */
#define EMU_EM4CONF_BURTCWU (0x1UL << 1) /* Backup RTC EM4 wakeup enable */
#define _EMU_EM4CONF_BURTCWU_SHIFT 1 /* Shift value for EMU_BURTCWU */
#define _EMU_EM4CONF_BURTCWU_MASK 0x2UL /* Bit mask for EMU_BURTCWU */
#define _EMU_EM4CONF_BURTCWU_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_EM4CONF */
#define EMU_EM4CONF_BURTCWU_DEFAULT (_EMU_EM4CONF_BURTCWU_DEFAULT << 1) /* Shifted mode DEFAULT for EMU_EM4CONF */
#define _EMU_EM4CONF_OSC_SHIFT 2 /* Shift value for EMU_OSC */
#define _EMU_EM4CONF_OSC_MASK 0xCUL /* Bit mask for EMU_OSC */
#define _EMU_EM4CONF_OSC_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_EM4CONF */
#define _EMU_EM4CONF_OSC_ULFRCO 0x00000000UL /* Mode ULFRCO for EMU_EM4CONF */
#define _EMU_EM4CONF_OSC_LFRCO 0x00000001UL /* Mode LFRCO for EMU_EM4CONF */
#define _EMU_EM4CONF_OSC_LFXO 0x00000002UL /* Mode LFXO for EMU_EM4CONF */
#define EMU_EM4CONF_OSC_DEFAULT (_EMU_EM4CONF_OSC_DEFAULT << 2) /* Shifted mode DEFAULT for EMU_EM4CONF */
#define EMU_EM4CONF_OSC_ULFRCO (_EMU_EM4CONF_OSC_ULFRCO << 2) /* Shifted mode ULFRCO for EMU_EM4CONF */
#define EMU_EM4CONF_OSC_LFRCO (_EMU_EM4CONF_OSC_LFRCO << 2) /* Shifted mode LFRCO for EMU_EM4CONF */
#define EMU_EM4CONF_OSC_LFXO (_EMU_EM4CONF_OSC_LFXO << 2) /* Shifted mode LFXO for EMU_EM4CONF */
#define EMU_EM4CONF_BUBODRSTDIS (0x1UL << 4) /* Disable reset from Backup BOD in EM4 */
#define _EMU_EM4CONF_BUBODRSTDIS_SHIFT 4 /* Shift value for EMU_BUBODRSTDIS */
#define _EMU_EM4CONF_BUBODRSTDIS_MASK 0x10UL /* Bit mask for EMU_BUBODRSTDIS */
#define _EMU_EM4CONF_BUBODRSTDIS_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_EM4CONF */
#define EMU_EM4CONF_BUBODRSTDIS_DEFAULT (_EMU_EM4CONF_BUBODRSTDIS_DEFAULT << 4) /* Shifted mode DEFAULT for EMU_EM4CONF */
#define EMU_EM4CONF_LOCKCONF (0x1UL << 16) /* EM4 configuration lock enable */
#define _EMU_EM4CONF_LOCKCONF_SHIFT 16 /* Shift value for EMU_LOCKCONF */
#define _EMU_EM4CONF_LOCKCONF_MASK 0x10000UL /* Bit mask for EMU_LOCKCONF */
#define _EMU_EM4CONF_LOCKCONF_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_EM4CONF */
#define EMU_EM4CONF_LOCKCONF_DEFAULT (_EMU_EM4CONF_LOCKCONF_DEFAULT << 16) /* Shifted mode DEFAULT for EMU_EM4CONF */
/* Bit fields for EMU BUCTRL */
#define _EMU_BUCTRL_RESETVALUE 0x00000000UL /* Default value for EMU_BUCTRL */
#define _EMU_BUCTRL_MASK 0x00000067UL /* Mask for EMU_BUCTRL */
#define EMU_BUCTRL_EN (0x1UL << 0) /* Enable backup mode */
#define _EMU_BUCTRL_EN_SHIFT 0 /* Shift value for EMU_EN */
#define _EMU_BUCTRL_EN_MASK 0x1UL /* Bit mask for EMU_EN */
#define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_BUCTRL */
#define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_BUCTRL */
#define EMU_BUCTRL_STATEN (0x1UL << 1) /* Enable backup mode status export */
#define _EMU_BUCTRL_STATEN_SHIFT 1 /* Shift value for EMU_STATEN */
#define _EMU_BUCTRL_STATEN_MASK 0x2UL /* Bit mask for EMU_STATEN */
#define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_BUCTRL */
#define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /* Shifted mode DEFAULT for EMU_BUCTRL */
#define EMU_BUCTRL_BODCAL (0x1UL << 2) /* Enable BOD calibration mode */
#define _EMU_BUCTRL_BODCAL_SHIFT 2 /* Shift value for EMU_BODCAL */
#define _EMU_BUCTRL_BODCAL_MASK 0x4UL /* Bit mask for EMU_BODCAL */
#define _EMU_BUCTRL_BODCAL_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_BUCTRL */
#define EMU_BUCTRL_BODCAL_DEFAULT (_EMU_BUCTRL_BODCAL_DEFAULT << 2) /* Shifted mode DEFAULT for EMU_BUCTRL */
#define _EMU_BUCTRL_PROBE_SHIFT 5 /* Shift value for EMU_PROBE */
#define _EMU_BUCTRL_PROBE_MASK 0x60UL /* Bit mask for EMU_PROBE */
#define _EMU_BUCTRL_PROBE_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_BUCTRL */
#define _EMU_BUCTRL_PROBE_DISABLE 0x00000000UL /* Mode DISABLE for EMU_BUCTRL */
#define _EMU_BUCTRL_PROBE_VDDDREG 0x00000001UL /* Mode VDDDREG for EMU_BUCTRL */
#define _EMU_BUCTRL_PROBE_BUIN 0x00000002UL /* Mode BUIN for EMU_BUCTRL */
#define _EMU_BUCTRL_PROBE_BUOUT 0x00000003UL /* Mode BUOUT for EMU_BUCTRL */
#define EMU_BUCTRL_PROBE_DEFAULT (_EMU_BUCTRL_PROBE_DEFAULT << 5) /* Shifted mode DEFAULT for EMU_BUCTRL */
#define EMU_BUCTRL_PROBE_DISABLE (_EMU_BUCTRL_PROBE_DISABLE << 5) /* Shifted mode DISABLE for EMU_BUCTRL */
#define EMU_BUCTRL_PROBE_VDDDREG (_EMU_BUCTRL_PROBE_VDDDREG << 5) /* Shifted mode VDDDREG for EMU_BUCTRL */
#define EMU_BUCTRL_PROBE_BUIN (_EMU_BUCTRL_PROBE_BUIN << 5) /* Shifted mode BUIN for EMU_BUCTRL */
#define EMU_BUCTRL_PROBE_BUOUT (_EMU_BUCTRL_PROBE_BUOUT << 5) /* Shifted mode BUOUT for EMU_BUCTRL */
/* Bit fields for EMU PWRCONF */
#define _EMU_PWRCONF_RESETVALUE 0x00000000UL /* Default value for EMU_PWRCONF */
#define _EMU_PWRCONF_MASK 0x0000001FUL /* Mask for EMU_PWRCONF */
#define EMU_PWRCONF_VOUTWEAK (0x1UL << 0) /* BU_VOUT weak enable */
#define _EMU_PWRCONF_VOUTWEAK_SHIFT 0 /* Shift value for EMU_VOUTWEAK */
#define _EMU_PWRCONF_VOUTWEAK_MASK 0x1UL /* Bit mask for EMU_VOUTWEAK */
#define _EMU_PWRCONF_VOUTWEAK_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_PWRCONF */
#define EMU_PWRCONF_VOUTWEAK_DEFAULT (_EMU_PWRCONF_VOUTWEAK_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_PWRCONF */
#define EMU_PWRCONF_VOUTMED (0x1UL << 1) /* BU_VOUT medium enable */
#define _EMU_PWRCONF_VOUTMED_SHIFT 1 /* Shift value for EMU_VOUTMED */
#define _EMU_PWRCONF_VOUTMED_MASK 0x2UL /* Bit mask for EMU_VOUTMED */
#define _EMU_PWRCONF_VOUTMED_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_PWRCONF */
#define EMU_PWRCONF_VOUTMED_DEFAULT (_EMU_PWRCONF_VOUTMED_DEFAULT << 1) /* Shifted mode DEFAULT for EMU_PWRCONF */
#define EMU_PWRCONF_VOUTSTRONG (0x1UL << 2) /* BU_VOUT strong enable */
#define _EMU_PWRCONF_VOUTSTRONG_SHIFT 2 /* Shift value for EMU_VOUTSTRONG */
#define _EMU_PWRCONF_VOUTSTRONG_MASK 0x4UL /* Bit mask for EMU_VOUTSTRONG */
#define _EMU_PWRCONF_VOUTSTRONG_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_PWRCONF */
#define EMU_PWRCONF_VOUTSTRONG_DEFAULT (_EMU_PWRCONF_VOUTSTRONG_DEFAULT << 2) /* Shifted mode DEFAULT for EMU_PWRCONF */
#define _EMU_PWRCONF_PWRRES_SHIFT 3 /* Shift value for EMU_PWRRES */
#define _EMU_PWRCONF_PWRRES_MASK 0x18UL /* Bit mask for EMU_PWRRES */
#define _EMU_PWRCONF_PWRRES_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_PWRCONF */
#define _EMU_PWRCONF_PWRRES_RES0 0x00000000UL /* Mode RES0 for EMU_PWRCONF */
#define _EMU_PWRCONF_PWRRES_RES1 0x00000001UL /* Mode RES1 for EMU_PWRCONF */
#define _EMU_PWRCONF_PWRRES_RES2 0x00000002UL /* Mode RES2 for EMU_PWRCONF */
#define _EMU_PWRCONF_PWRRES_RES3 0x00000003UL /* Mode RES3 for EMU_PWRCONF */
#define EMU_PWRCONF_PWRRES_DEFAULT (_EMU_PWRCONF_PWRRES_DEFAULT << 3) /* Shifted mode DEFAULT for EMU_PWRCONF */
#define EMU_PWRCONF_PWRRES_RES0 (_EMU_PWRCONF_PWRRES_RES0 << 3) /* Shifted mode RES0 for EMU_PWRCONF */
#define EMU_PWRCONF_PWRRES_RES1 (_EMU_PWRCONF_PWRRES_RES1 << 3) /* Shifted mode RES1 for EMU_PWRCONF */
#define EMU_PWRCONF_PWRRES_RES2 (_EMU_PWRCONF_PWRRES_RES2 << 3) /* Shifted mode RES2 for EMU_PWRCONF */
#define EMU_PWRCONF_PWRRES_RES3 (_EMU_PWRCONF_PWRRES_RES3 << 3) /* Shifted mode RES3 for EMU_PWRCONF */
/* Bit fields for EMU BUINACT */
#define _EMU_BUINACT_RESETVALUE 0x0000000BUL /* Default value for EMU_BUINACT */
#define _EMU_BUINACT_MASK 0x0000007FUL /* Mask for EMU_BUINACT */
#define _EMU_BUINACT_BUENTHRES_SHIFT 0 /* Shift value for EMU_BUENTHRES */
#define _EMU_BUINACT_BUENTHRES_MASK 0x7UL /* Bit mask for EMU_BUENTHRES */
#define _EMU_BUINACT_BUENTHRES_DEFAULT 0x00000003UL /* Mode DEFAULT for EMU_BUINACT */
#define EMU_BUINACT_BUENTHRES_DEFAULT (_EMU_BUINACT_BUENTHRES_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_BUINACT */
#define _EMU_BUINACT_BUENRANGE_SHIFT 3 /* Shift value for EMU_BUENRANGE */
#define _EMU_BUINACT_BUENRANGE_MASK 0x18UL /* Bit mask for EMU_BUENRANGE */
#define _EMU_BUINACT_BUENRANGE_DEFAULT 0x00000001UL /* Mode DEFAULT for EMU_BUINACT */
#define EMU_BUINACT_BUENRANGE_DEFAULT (_EMU_BUINACT_BUENRANGE_DEFAULT << 3) /* Shifted mode DEFAULT for EMU_BUINACT */
#define _EMU_BUINACT_PWRCON_SHIFT 5 /* Shift value for EMU_PWRCON */
#define _EMU_BUINACT_PWRCON_MASK 0x60UL /* Bit mask for EMU_PWRCON */
#define _EMU_BUINACT_PWRCON_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_BUINACT */
#define _EMU_BUINACT_PWRCON_NONE 0x00000000UL /* Mode NONE for EMU_BUINACT */
#define _EMU_BUINACT_PWRCON_BUMAIN 0x00000001UL /* Mode BUMAIN for EMU_BUINACT */
#define _EMU_BUINACT_PWRCON_MAINBU 0x00000002UL /* Mode MAINBU for EMU_BUINACT */
#define _EMU_BUINACT_PWRCON_NODIODE 0x00000003UL /* Mode NODIODE for EMU_BUINACT */
#define EMU_BUINACT_PWRCON_DEFAULT (_EMU_BUINACT_PWRCON_DEFAULT << 5) /* Shifted mode DEFAULT for EMU_BUINACT */
#define EMU_BUINACT_PWRCON_NONE (_EMU_BUINACT_PWRCON_NONE << 5) /* Shifted mode NONE for EMU_BUINACT */
#define EMU_BUINACT_PWRCON_BUMAIN (_EMU_BUINACT_PWRCON_BUMAIN << 5) /* Shifted mode BUMAIN for EMU_BUINACT */
#define EMU_BUINACT_PWRCON_MAINBU (_EMU_BUINACT_PWRCON_MAINBU << 5) /* Shifted mode MAINBU for EMU_BUINACT */
#define EMU_BUINACT_PWRCON_NODIODE (_EMU_BUINACT_PWRCON_NODIODE << 5) /* Shifted mode NODIODE for EMU_BUINACT */
/* Bit fields for EMU BUACT */
#define _EMU_BUACT_RESETVALUE 0x0000000BUL /* Default value for EMU_BUACT */
#define _EMU_BUACT_MASK 0x0000007FUL /* Mask for EMU_BUACT */
#define _EMU_BUACT_BUEXTHRES_SHIFT 0 /* Shift value for EMU_BUEXTHRES */
#define _EMU_BUACT_BUEXTHRES_MASK 0x7UL /* Bit mask for EMU_BUEXTHRES */
#define _EMU_BUACT_BUEXTHRES_DEFAULT 0x00000003UL /* Mode DEFAULT for EMU_BUACT */
#define EMU_BUACT_BUEXTHRES_DEFAULT (_EMU_BUACT_BUEXTHRES_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_BUACT */
#define _EMU_BUACT_BUEXRANGE_SHIFT 3 /* Shift value for EMU_BUEXRANGE */
#define _EMU_BUACT_BUEXRANGE_MASK 0x18UL /* Bit mask for EMU_BUEXRANGE */
#define _EMU_BUACT_BUEXRANGE_DEFAULT 0x00000001UL /* Mode DEFAULT for EMU_BUACT */
#define EMU_BUACT_BUEXRANGE_DEFAULT (_EMU_BUACT_BUEXRANGE_DEFAULT << 3) /* Shifted mode DEFAULT for EMU_BUACT */
#define _EMU_BUACT_PWRCON_SHIFT 5 /* Shift value for EMU_PWRCON */
#define _EMU_BUACT_PWRCON_MASK 0x60UL /* Bit mask for EMU_PWRCON */
#define _EMU_BUACT_PWRCON_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_BUACT */
#define _EMU_BUACT_PWRCON_NONE 0x00000000UL /* Mode NONE for EMU_BUACT */
#define _EMU_BUACT_PWRCON_BUMAIN 0x00000001UL /* Mode BUMAIN for EMU_BUACT */
#define _EMU_BUACT_PWRCON_MAINBU 0x00000002UL /* Mode MAINBU for EMU_BUACT */
#define _EMU_BUACT_PWRCON_NODIODE 0x00000003UL /* Mode NODIODE for EMU_BUACT */
#define EMU_BUACT_PWRCON_DEFAULT (_EMU_BUACT_PWRCON_DEFAULT << 5) /* Shifted mode DEFAULT for EMU_BUACT */
#define EMU_BUACT_PWRCON_NONE (_EMU_BUACT_PWRCON_NONE << 5) /* Shifted mode NONE for EMU_BUACT */
#define EMU_BUACT_PWRCON_BUMAIN (_EMU_BUACT_PWRCON_BUMAIN << 5) /* Shifted mode BUMAIN for EMU_BUACT */
#define EMU_BUACT_PWRCON_MAINBU (_EMU_BUACT_PWRCON_MAINBU << 5) /* Shifted mode MAINBU for EMU_BUACT */
#define EMU_BUACT_PWRCON_NODIODE (_EMU_BUACT_PWRCON_NODIODE << 5) /* Shifted mode NODIODE for EMU_BUACT */
/* Bit fields for EMU STATUS */
#define _EMU_STATUS_RESETVALUE 0x00000000UL /* Default value for EMU_STATUS */
#define _EMU_STATUS_MASK 0x00000001UL /* Mask for EMU_STATUS */
#define EMU_STATUS_BURDY (0x1UL << 0) /* Backup mode ready */
#define _EMU_STATUS_BURDY_SHIFT 0 /* Shift value for EMU_BURDY */
#define _EMU_STATUS_BURDY_MASK 0x1UL /* Bit mask for EMU_BURDY */
#define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_STATUS */
#define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_STATUS */
/* Bit fields for EMU ROUTE */
#define _EMU_ROUTE_RESETVALUE 0x00000001UL /* Default value for EMU_ROUTE */
#define _EMU_ROUTE_MASK 0x00000001UL /* Mask for EMU_ROUTE */
#define EMU_ROUTE_BUVINPEN (0x1UL << 0) /* BU_VIN Pin Enable */
#define _EMU_ROUTE_BUVINPEN_SHIFT 0 /* Shift value for EMU_BUVINPEN */
#define _EMU_ROUTE_BUVINPEN_MASK 0x1UL /* Bit mask for EMU_BUVINPEN */
#define _EMU_ROUTE_BUVINPEN_DEFAULT 0x00000001UL /* Mode DEFAULT for EMU_ROUTE */
#define EMU_ROUTE_BUVINPEN_DEFAULT (_EMU_ROUTE_BUVINPEN_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_ROUTE */
/* Bit fields for EMU IF */
#define _EMU_IF_RESETVALUE 0x00000000UL /* Default value for EMU_IF */
#define _EMU_IF_MASK 0x00000001UL /* Mask for EMU_IF */
#define EMU_IF_BURDY (0x1UL << 0) /* Backup functionality ready Interrupt Flag */
#define _EMU_IF_BURDY_SHIFT 0 /* Shift value for EMU_BURDY */
#define _EMU_IF_BURDY_MASK 0x1UL /* Bit mask for EMU_BURDY */
#define _EMU_IF_BURDY_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_IF */
#define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_IF */
/* Bit fields for EMU IFS */
#define _EMU_IFS_RESETVALUE 0x00000000UL /* Default value for EMU_IFS */
#define _EMU_IFS_MASK 0x00000001UL /* Mask for EMU_IFS */
#define EMU_IFS_BURDY (0x1UL << 0) /* Set Backup functionality ready Interrupt Flag */
#define _EMU_IFS_BURDY_SHIFT 0 /* Shift value for EMU_BURDY */
#define _EMU_IFS_BURDY_MASK 0x1UL /* Bit mask for EMU_BURDY */
#define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_IFS */
#define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_IFS */
/* Bit fields for EMU IFC */
#define _EMU_IFC_RESETVALUE 0x00000000UL /* Default value for EMU_IFC */
#define _EMU_IFC_MASK 0x00000001UL /* Mask for EMU_IFC */
#define EMU_IFC_BURDY (0x1UL << 0) /* Clear Backup functionality ready Interrupt Flag */
#define _EMU_IFC_BURDY_SHIFT 0 /* Shift value for EMU_BURDY */
#define _EMU_IFC_BURDY_MASK 0x1UL /* Bit mask for EMU_BURDY */
#define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_IFC */
#define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_IFC */
/* Bit fields for EMU IEN */
#define _EMU_IEN_RESETVALUE 0x00000000UL /* Default value for EMU_IEN */
#define _EMU_IEN_MASK 0x00000001UL /* Mask for EMU_IEN */
#define EMU_IEN_BURDY (0x1UL << 0) /* Backup functionality ready Interrupt Enable */
#define _EMU_IEN_BURDY_SHIFT 0 /* Shift value for EMU_BURDY */
#define _EMU_IEN_BURDY_MASK 0x1UL /* Bit mask for EMU_BURDY */
#define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /* Mode DEFAULT for EMU_IEN */
#define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_IEN */
/* Bit fields for EMU BUBODBUVINCAL */
#define _EMU_BUBODBUVINCAL_RESETVALUE 0x0000000BUL /* Default value for EMU_BUBODBUVINCAL */
#define _EMU_BUBODBUVINCAL_MASK 0x0000001FUL /* Mask for EMU_BUBODBUVINCAL */
#define _EMU_BUBODBUVINCAL_THRES_SHIFT 0 /* Shift value for EMU_THRES */
#define _EMU_BUBODBUVINCAL_THRES_MASK 0x7UL /* Bit mask for EMU_THRES */
#define _EMU_BUBODBUVINCAL_THRES_DEFAULT 0x00000003UL /* Mode DEFAULT for EMU_BUBODBUVINCAL */
#define EMU_BUBODBUVINCAL_THRES_DEFAULT (_EMU_BUBODBUVINCAL_THRES_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_BUBODBUVINCAL */
#define _EMU_BUBODBUVINCAL_RANGE_SHIFT 3 /* Shift value for EMU_RANGE */
#define _EMU_BUBODBUVINCAL_RANGE_MASK 0x18UL /* Bit mask for EMU_RANGE */
#define _EMU_BUBODBUVINCAL_RANGE_DEFAULT 0x00000001UL /* Mode DEFAULT for EMU_BUBODBUVINCAL */
#define EMU_BUBODBUVINCAL_RANGE_DEFAULT (_EMU_BUBODBUVINCAL_RANGE_DEFAULT << 3) /* Shifted mode DEFAULT for EMU_BUBODBUVINCAL */
/* Bit fields for EMU BUBODUNREGCAL */
#define _EMU_BUBODUNREGCAL_RESETVALUE 0x0000000BUL /* Default value for EMU_BUBODUNREGCAL */
#define _EMU_BUBODUNREGCAL_MASK 0x0000001FUL /* Mask for EMU_BUBODUNREGCAL */
#define _EMU_BUBODUNREGCAL_THRES_SHIFT 0 /* Shift value for EMU_THRES */
#define _EMU_BUBODUNREGCAL_THRES_MASK 0x7UL /* Bit mask for EMU_THRES */
#define _EMU_BUBODUNREGCAL_THRES_DEFAULT 0x00000003UL /* Mode DEFAULT for EMU_BUBODUNREGCAL */
#define EMU_BUBODUNREGCAL_THRES_DEFAULT (_EMU_BUBODUNREGCAL_THRES_DEFAULT << 0) /* Shifted mode DEFAULT for EMU_BUBODUNREGCAL */
#define _EMU_BUBODUNREGCAL_RANGE_SHIFT 3 /* Shift value for EMU_RANGE */
#define _EMU_BUBODUNREGCAL_RANGE_MASK 0x18UL /* Bit mask for EMU_RANGE */
#define _EMU_BUBODUNREGCAL_RANGE_DEFAULT 0x00000001UL /* Mode DEFAULT for EMU_BUBODUNREGCAL */
#define EMU_BUBODUNREGCAL_RANGE_DEFAULT (_EMU_BUBODUNREGCAL_RANGE_DEFAULT << 3) /* Shifted mode DEFAULT for EMU_BUBODUNREGCAL */
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_EMU_H */
arch/arm/src/efm32/chip/efm32_gpio.h
+5
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@@ -65,8 +65,13 @@
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG) && !defined(CONFIG_EFM32_EFM32G)
# warning This is the EFM32GG/G header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
arch/arm/src/efm32/chip/efm32_i2c.h
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arch/arm/src/efm32/chip/efm32_lcd.h
+714
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arch/arm/src/efm32/chip/efm32_lesense.h
+2160
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arch/arm/src/efm32/chip/efm32_letimer.h
+488
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@@ -0,0 +1,488 @@
/*******************************************************************************************************************************
* arch/arm/src/efm32/chip/efm32_letimer.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Authors: Pierre-noel Bouteville <pnb990@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LETIMER_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LETIMER_H
/*******************************************************************************************************************************
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG)
# warning This is the EFM32GG header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* LETIMER Register Offsets ****************************************************************************************************/
#define EFM32_LETIMER_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_LETIMER_CMD_OFFSET 0x0004 /* Command Register */
#define EFM32_LETIMER_STATUS_OFFSET 0x0008 /* Status Register */
#define EFM32_LETIMER_CNT_OFFSET 0x000c /* Counter Value Register */
#define EFM32_LETIMER_COMP0_OFFSET 0x0010 /* Compare Value Register */ 0
#define EFM32_LETIMER_COMP1_OFFSET 0x0014 /* Compare Value Register */ 1
#define EFM32_LETIMER_REP0_OFFSET 0x0018 /* Repeat Counter Register 0 */
#define EFM32_LETIMER_REP1_OFFSET 0x001c /* Repeat Counter Register 1 */
#define EFM32_LETIMER_IF_OFFSET 0x0020 /* Interrupt Flag Register */
#define EFM32_LETIMER_IFS_OFFSET 0x0024 /* Interrupt Flag Set Register */
#define EFM32_LETIMER_IFC_OFFSET 0x0028 /* Interrupt Flag Clear Register */
#define EFM32_LETIMER_IEN_OFFSET 0x002c /* Interrupt Enable Register */
#define EFM32_LETIMER_FREEZE_OFFSET 0x0030 /* Freeze Register */
#define EFM32_LETIMER_SYNCBUSY_OFFSET 0x0034 /* Synchronization Busy Register */
#define EFM32_LETIMER_ROUTE_OFFSET 0x0040 /* I/O Routing Register */
/* LETIMER Register Addresses **************************************************************************************************/
#define EFM32_LETIMER0_CTRL (EFM32_LETIMER0_BASE+EFM32_LETIMER0_CTRL_OFFSET)
#define EFM32_LETIMER0_CMD (EFM32_LETIMER0_BASE+EFM32_LETIMER0_CMD_OFFSET)
#define EFM32_LETIMER0_STATUS (EFM32_LETIMER0_BASE+EFM32_LETIMER0_STATUS_OFFSET)
#define EFM32_LETIMER0_CNT (EFM32_LETIMER0_BASE+EFM32_LETIMER0_CNT_OFFSET)
#define EFM32_LETIMER0_COMP0 (EFM32_LETIMER0_BASE+EFM32_LETIMER0_COMP0_OFFSET)
#define EFM32_LETIMER0_COMP1 (EFM32_LETIMER0_BASE+EFM32_LETIMER0_COMP1_OFFSET)
#define EFM32_LETIMER0_REP0 (EFM32_LETIMER0_BASE+EFM32_LETIMER0_REP0_OFFSET)
#define EFM32_LETIMER0_REP1 (EFM32_LETIMER0_BASE+EFM32_LETIMER0_REP1_OFFSET)
#define EFM32_LETIMER0_IF (EFM32_LETIMER0_BASE+EFM32_LETIMER0_IF_OFFSET)
#define EFM32_LETIMER0_IFS (EFM32_LETIMER0_BASE+EFM32_LETIMER0_IFS_OFFSET)
#define EFM32_LETIMER0_IFC (EFM32_LETIMER0_BASE+EFM32_LETIMER0_IFC_OFFSET)
#define EFM32_LETIMER0_IEN (EFM32_LETIMER0_BASE+EFM32_LETIMER0_IEN_OFFSET)
#define EFM32_LETIMER0_FREEZE (EFM32_LETIMER0_BASE+EFM32_LETIMER0_FREEZE_OFFSET)
#define EFM32_LETIMER0_SYNCBUSY (EFM32_LETIMER0_BASE+EFM32_LETIMER0_SYNCBUSY_OFFSET)
#define EFM32_LETIMER0_ROUTE (EFM32_LETIMER0_BASE+EFM32_LETIMER0_ROUTE_OFFSET)
/* LETIMER Register Bit Field Definitions **************************************************************************************/
/* Bit fields for LETIMER CTRL */
#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /* Default value for LETIMER_CTRL */
#define _LETIMER_CTRL_MASK 0x00001FFFUL /* Mask for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_SHIFT 0 /* Shift value for LETIMER_REPMODE */
#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /* Bit mask for LETIMER_REPMODE */
#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /* Mode FREE for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /* Mode ONESHOT for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /* Mode BUFFERED for LETIMER_CTRL */
#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /* Mode DOUBLE for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /* Shifted mode FREE for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /* Shifted mode ONESHOT for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /* Shifted mode BUFFERED for LETIMER_CTRL */
#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /* Shifted mode DOUBLE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_SHIFT 2 /* Shift value for LETIMER_UFOA0 */
#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /* Bit mask for LETIMER_UFOA0 */
#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /* Mode NONE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /* Mode TOGGLE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /* Mode PULSE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /* Mode PWM for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /* Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /* Shifted mode NONE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /* Shifted mode TOGGLE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /* Shifted mode PULSE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /* Shifted mode PWM for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_SHIFT 4 /* Shift value for LETIMER_UFOA1 */
#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /* Bit mask for LETIMER_UFOA1 */
#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /* Mode NONE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /* Mode TOGGLE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /* Mode PULSE for LETIMER_CTRL */
#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /* Mode PWM for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /* Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /* Shifted mode NONE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /* Shifted mode TOGGLE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /* Shifted mode PULSE for LETIMER_CTRL */
#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /* Shifted mode PWM for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /* Output 0 Polarity */
#define _LETIMER_CTRL_OPOL0_SHIFT 6 /* Shift value for LETIMER_OPOL0 */
#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /* Bit mask for LETIMER_OPOL0 */
#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /* Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /* Output 1 Polarity */
#define _LETIMER_CTRL_OPOL1_SHIFT 7 /* Shift value for LETIMER_OPOL1 */
#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /* Bit mask for LETIMER_OPOL1 */
#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /* Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /* Buffered Top */
#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /* Shift value for LETIMER_BUFTOP */
#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /* Bit mask for LETIMER_BUFTOP */
#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /* Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /* Compare Value 0 Is Top Value */
#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /* Shift value for LETIMER_COMP0TOP */
#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /* Bit mask for LETIMER_COMP0TOP */
#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) /* Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_RTCC0TEN (0x1UL << 10) /* RTC Compare 0 Trigger Enable */
#define _LETIMER_CTRL_RTCC0TEN_SHIFT 10 /* Shift value for LETIMER_RTCC0TEN */
#define _LETIMER_CTRL_RTCC0TEN_MASK 0x400UL /* Bit mask for LETIMER_RTCC0TEN */
#define _LETIMER_CTRL_RTCC0TEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_RTCC0TEN_DEFAULT (_LETIMER_CTRL_RTCC0TEN_DEFAULT << 10) /* Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_RTCC1TEN (0x1UL << 11) /* RTC Compare 1 Trigger Enable */
#define _LETIMER_CTRL_RTCC1TEN_SHIFT 11 /* Shift value for LETIMER_RTCC1TEN */
#define _LETIMER_CTRL_RTCC1TEN_MASK 0x800UL /* Bit mask for LETIMER_RTCC1TEN */
#define _LETIMER_CTRL_RTCC1TEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_RTCC1TEN_DEFAULT (_LETIMER_CTRL_RTCC1TEN_DEFAULT << 11) /* Shifted mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /* Debug Mode Run Enable */
#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /* Shift value for LETIMER_DEBUGRUN */
#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /* Bit mask for LETIMER_DEBUGRUN */
#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CTRL */
#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /* Shifted mode DEFAULT for LETIMER_CTRL */
/* Bit fields for LETIMER CMD */
#define _LETIMER_CMD_RESETVALUE 0x00000000UL /* Default value for LETIMER_CMD */
#define _LETIMER_CMD_MASK 0x0000001FUL /* Mask for LETIMER_CMD */
#define LETIMER_CMD_START (0x1UL << 0) /* Start LETIMER */
#define _LETIMER_CMD_START_SHIFT 0 /* Shift value for LETIMER_START */
#define _LETIMER_CMD_START_MASK 0x1UL /* Bit mask for LETIMER_START */
#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_STOP (0x1UL << 1) /* Stop LETIMER */
#define _LETIMER_CMD_STOP_SHIFT 1 /* Shift value for LETIMER_STOP */
#define _LETIMER_CMD_STOP_MASK 0x2UL /* Bit mask for LETIMER_STOP */
#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /* Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CLEAR (0x1UL << 2) /* Clear LETIMER */
#define _LETIMER_CMD_CLEAR_SHIFT 2 /* Shift value for LETIMER_CLEAR */
#define _LETIMER_CMD_CLEAR_MASK 0x4UL /* Bit mask for LETIMER_CLEAR */
#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /* Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO0 (0x1UL << 3) /* Clear Toggle Output 0 */
#define _LETIMER_CMD_CTO0_SHIFT 3 /* Shift value for LETIMER_CTO0 */
#define _LETIMER_CMD_CTO0_MASK 0x8UL /* Bit mask for LETIMER_CTO0 */
#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /* Shifted mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO1 (0x1UL << 4) /* Clear Toggle Output 1 */
#define _LETIMER_CMD_CTO1_SHIFT 4 /* Shift value for LETIMER_CTO1 */
#define _LETIMER_CMD_CTO1_MASK 0x10UL /* Bit mask for LETIMER_CTO1 */
#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CMD */
#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /* Shifted mode DEFAULT for LETIMER_CMD */
/* Bit fields for LETIMER STATUS */
#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /* Default value for LETIMER_STATUS */
#define _LETIMER_STATUS_MASK 0x00000001UL /* Mask for LETIMER_STATUS */
#define LETIMER_STATUS_RUNNING (0x1UL << 0) /* LETIMER Running */
#define _LETIMER_STATUS_RUNNING_SHIFT 0 /* Shift value for LETIMER_RUNNING */
#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /* Bit mask for LETIMER_RUNNING */
#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_STATUS */
#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_STATUS */
/* Bit fields for LETIMER CNT */
#define _LETIMER_CNT_RESETVALUE 0x00000000UL /* Default value for LETIMER_CNT */
#define _LETIMER_CNT_MASK 0x0000FFFFUL /* Mask for LETIMER_CNT */
#define _LETIMER_CNT_CNT_SHIFT 0 /* Shift value for LETIMER_CNT */
#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /* Bit mask for LETIMER_CNT */
#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_CNT */
#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_CNT */
/* Bit fields for LETIMER COMP0 */
#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /* Default value for LETIMER_COMP0 */
#define _LETIMER_COMP0_MASK 0x0000FFFFUL /* Mask for LETIMER_COMP0 */
#define _LETIMER_COMP0_COMP0_SHIFT 0 /* Shift value for LETIMER_COMP0 */
#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /* Bit mask for LETIMER_COMP0 */
#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_COMP0 */
#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_COMP0 */
/* Bit fields for LETIMER COMP1 */
#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /* Default value for LETIMER_COMP1 */
#define _LETIMER_COMP1_MASK 0x0000FFFFUL /* Mask for LETIMER_COMP1 */
#define _LETIMER_COMP1_COMP1_SHIFT 0 /* Shift value for LETIMER_COMP1 */
#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /* Bit mask for LETIMER_COMP1 */
#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_COMP1 */
#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_COMP1 */
/* Bit fields for LETIMER REP0 */
#define _LETIMER_REP0_RESETVALUE 0x00000000UL /* Default value for LETIMER_REP0 */
#define _LETIMER_REP0_MASK 0x000000FFUL /* Mask for LETIMER_REP0 */
#define _LETIMER_REP0_REP0_SHIFT 0 /* Shift value for LETIMER_REP0 */
#define _LETIMER_REP0_REP0_MASK 0xFFUL /* Bit mask for LETIMER_REP0 */
#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_REP0 */
#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_REP0 */
/* Bit fields for LETIMER REP1 */
#define _LETIMER_REP1_RESETVALUE 0x00000000UL /* Default value for LETIMER_REP1 */
#define _LETIMER_REP1_MASK 0x000000FFUL /* Mask for LETIMER_REP1 */
#define _LETIMER_REP1_REP1_SHIFT 0 /* Shift value for LETIMER_REP1 */
#define _LETIMER_REP1_REP1_MASK 0xFFUL /* Bit mask for LETIMER_REP1 */
#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_REP1 */
#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_REP1 */
/* Bit fields for LETIMER IF */
#define _LETIMER_IF_RESETVALUE 0x00000000UL /* Default value for LETIMER_IF */
#define _LETIMER_IF_MASK 0x0000001FUL /* Mask for LETIMER_IF */
#define LETIMER_IF_COMP0 (0x1UL << 0) /* Compare Match 0 Interrupt Flag */
#define _LETIMER_IF_COMP0_SHIFT 0 /* Shift value for LETIMER_COMP0 */
#define _LETIMER_IF_COMP0_MASK 0x1UL /* Bit mask for LETIMER_COMP0 */
#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_COMP1 (0x1UL << 1) /* Compare Match 1 Interrupt Flag */
#define _LETIMER_IF_COMP1_SHIFT 1 /* Shift value for LETIMER_COMP1 */
#define _LETIMER_IF_COMP1_MASK 0x2UL /* Bit mask for LETIMER_COMP1 */
#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /* Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_UF (0x1UL << 2) /* Underflow Interrupt Flag */
#define _LETIMER_IF_UF_SHIFT 2 /* Shift value for LETIMER_UF */
#define _LETIMER_IF_UF_MASK 0x4UL /* Bit mask for LETIMER_UF */
#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /* Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP0 (0x1UL << 3) /* Repeat Counter 0 Interrupt Flag */
#define _LETIMER_IF_REP0_SHIFT 3 /* Shift value for LETIMER_REP0 */
#define _LETIMER_IF_REP0_MASK 0x8UL /* Bit mask for LETIMER_REP0 */
#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /* Shifted mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP1 (0x1UL << 4) /* Repeat Counter 1 Interrupt Flag */
#define _LETIMER_IF_REP1_SHIFT 4 /* Shift value for LETIMER_REP1 */
#define _LETIMER_IF_REP1_MASK 0x10UL /* Bit mask for LETIMER_REP1 */
#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IF */
#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /* Shifted mode DEFAULT for LETIMER_IF */
/* Bit fields for LETIMER IFS */
#define _LETIMER_IFS_RESETVALUE 0x00000000UL /* Default value for LETIMER_IFS */
#define _LETIMER_IFS_MASK 0x0000001FUL /* Mask for LETIMER_IFS */
#define LETIMER_IFS_COMP0 (0x1UL << 0) /* Set Compare Match 0 Interrupt Flag */
#define _LETIMER_IFS_COMP0_SHIFT 0 /* Shift value for LETIMER_COMP0 */
#define _LETIMER_IFS_COMP0_MASK 0x1UL /* Bit mask for LETIMER_COMP0 */
#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_COMP1 (0x1UL << 1) /* Set Compare Match 1 Interrupt Flag */
#define _LETIMER_IFS_COMP1_SHIFT 1 /* Shift value for LETIMER_COMP1 */
#define _LETIMER_IFS_COMP1_MASK 0x2UL /* Bit mask for LETIMER_COMP1 */
#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) /* Shifted mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_UF (0x1UL << 2) /* Set Underflow Interrupt Flag */
#define _LETIMER_IFS_UF_SHIFT 2 /* Shift value for LETIMER_UF */
#define _LETIMER_IFS_UF_MASK 0x4UL /* Bit mask for LETIMER_UF */
#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) /* Shifted mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_REP0 (0x1UL << 3) /* Set Repeat Counter 0 Interrupt Flag */
#define _LETIMER_IFS_REP0_SHIFT 3 /* Shift value for LETIMER_REP0 */
#define _LETIMER_IFS_REP0_MASK 0x8UL /* Bit mask for LETIMER_REP0 */
#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) /* Shifted mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_REP1 (0x1UL << 4) /* Set Repeat Counter 1 Interrupt Flag */
#define _LETIMER_IFS_REP1_SHIFT 4 /* Shift value for LETIMER_REP1 */
#define _LETIMER_IFS_REP1_MASK 0x10UL /* Bit mask for LETIMER_REP1 */
#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFS */
#define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) /* Shifted mode DEFAULT for LETIMER_IFS */
/* Bit fields for LETIMER IFC */
#define _LETIMER_IFC_RESETVALUE 0x00000000UL /* Default value for LETIMER_IFC */
#define _LETIMER_IFC_MASK 0x0000001FUL /* Mask for LETIMER_IFC */
#define LETIMER_IFC_COMP0 (0x1UL << 0) /* Clear Compare Match 0 Interrupt Flag */
#define _LETIMER_IFC_COMP0_SHIFT 0 /* Shift value for LETIMER_COMP0 */
#define _LETIMER_IFC_COMP0_MASK 0x1UL /* Bit mask for LETIMER_COMP0 */
#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_COMP1 (0x1UL << 1) /* Clear Compare Match 1 Interrupt Flag */
#define _LETIMER_IFC_COMP1_SHIFT 1 /* Shift value for LETIMER_COMP1 */
#define _LETIMER_IFC_COMP1_MASK 0x2UL /* Bit mask for LETIMER_COMP1 */
#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) /* Shifted mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_UF (0x1UL << 2) /* Clear Underflow Interrupt Flag */
#define _LETIMER_IFC_UF_SHIFT 2 /* Shift value for LETIMER_UF */
#define _LETIMER_IFC_UF_MASK 0x4UL /* Bit mask for LETIMER_UF */
#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) /* Shifted mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_REP0 (0x1UL << 3) /* Clear Repeat Counter 0 Interrupt Flag */
#define _LETIMER_IFC_REP0_SHIFT 3 /* Shift value for LETIMER_REP0 */
#define _LETIMER_IFC_REP0_MASK 0x8UL /* Bit mask for LETIMER_REP0 */
#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) /* Shifted mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_REP1 (0x1UL << 4) /* Clear Repeat Counter 1 Interrupt Flag */
#define _LETIMER_IFC_REP1_SHIFT 4 /* Shift value for LETIMER_REP1 */
#define _LETIMER_IFC_REP1_MASK 0x10UL /* Bit mask for LETIMER_REP1 */
#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IFC */
#define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) /* Shifted mode DEFAULT for LETIMER_IFC */
/* Bit fields for LETIMER IEN */
#define _LETIMER_IEN_RESETVALUE 0x00000000UL /* Default value for LETIMER_IEN */
#define _LETIMER_IEN_MASK 0x0000001FUL /* Mask for LETIMER_IEN */
#define LETIMER_IEN_COMP0 (0x1UL << 0) /* Compare Match 0 Interrupt Enable */
#define _LETIMER_IEN_COMP0_SHIFT 0 /* Shift value for LETIMER_COMP0 */
#define _LETIMER_IEN_COMP0_MASK 0x1UL /* Bit mask for LETIMER_COMP0 */
#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_COMP1 (0x1UL << 1) /* Compare Match 1 Interrupt Enable */
#define _LETIMER_IEN_COMP1_SHIFT 1 /* Shift value for LETIMER_COMP1 */
#define _LETIMER_IEN_COMP1_MASK 0x2UL /* Bit mask for LETIMER_COMP1 */
#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /* Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_UF (0x1UL << 2) /* Underflow Interrupt Enable */
#define _LETIMER_IEN_UF_SHIFT 2 /* Shift value for LETIMER_UF */
#define _LETIMER_IEN_UF_MASK 0x4UL /* Bit mask for LETIMER_UF */
#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /* Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP0 (0x1UL << 3) /* Repeat Counter 0 Interrupt Enable */
#define _LETIMER_IEN_REP0_SHIFT 3 /* Shift value for LETIMER_REP0 */
#define _LETIMER_IEN_REP0_MASK 0x8UL /* Bit mask for LETIMER_REP0 */
#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /* Shifted mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP1 (0x1UL << 4) /* Repeat Counter 1 Interrupt Enable */
#define _LETIMER_IEN_REP1_SHIFT 4 /* Shift value for LETIMER_REP1 */
#define _LETIMER_IEN_REP1_MASK 0x10UL /* Bit mask for LETIMER_REP1 */
#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_IEN */
#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /* Shifted mode DEFAULT for LETIMER_IEN */
/* Bit fields for LETIMER FREEZE */
#define _LETIMER_FREEZE_RESETVALUE 0x00000000UL /* Default value for LETIMER_FREEZE */
#define _LETIMER_FREEZE_MASK 0x00000001UL /* Mask for LETIMER_FREEZE */
#define LETIMER_FREEZE_REGFREEZE (0x1UL << 0) /* Register Update Freeze */
#define _LETIMER_FREEZE_REGFREEZE_SHIFT 0 /* Shift value for LETIMER_REGFREEZE */
#define _LETIMER_FREEZE_REGFREEZE_MASK 0x1UL /* Bit mask for LETIMER_REGFREEZE */
#define _LETIMER_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_FREEZE */
#define _LETIMER_FREEZE_REGFREEZE_UPDATE 0x00000000UL /* Mode UPDATE for LETIMER_FREEZE */
#define _LETIMER_FREEZE_REGFREEZE_FREEZE 0x00000001UL /* Mode FREEZE for LETIMER_FREEZE */
#define LETIMER_FREEZE_REGFREEZE_DEFAULT (_LETIMER_FREEZE_REGFREEZE_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_FREEZE */
#define LETIMER_FREEZE_REGFREEZE_UPDATE (_LETIMER_FREEZE_REGFREEZE_UPDATE << 0) /* Shifted mode UPDATE for LETIMER_FREEZE */
#define LETIMER_FREEZE_REGFREEZE_FREEZE (_LETIMER_FREEZE_REGFREEZE_FREEZE << 0) /* Shifted mode FREEZE for LETIMER_FREEZE */
/* Bit fields for LETIMER SYNCBUSY */
#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /* Default value for LETIMER_SYNCBUSY */
#define _LETIMER_SYNCBUSY_MASK 0x0000003FUL /* Mask for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CTRL (0x1UL << 0) /* CTRL Register Busy */
#define _LETIMER_SYNCBUSY_CTRL_SHIFT 0 /* Shift value for LETIMER_CTRL */
#define _LETIMER_SYNCBUSY_CTRL_MASK 0x1UL /* Bit mask for LETIMER_CTRL */
#define _LETIMER_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CTRL_DEFAULT (_LETIMER_SYNCBUSY_CTRL_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CMD (0x1UL << 1) /* CMD Register Busy */
#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /* Shift value for LETIMER_CMD */
#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /* Bit mask for LETIMER_CMD */
#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /* Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_COMP0 (0x1UL << 2) /* COMP0 Register Busy */
#define _LETIMER_SYNCBUSY_COMP0_SHIFT 2 /* Shift value for LETIMER_COMP0 */
#define _LETIMER_SYNCBUSY_COMP0_MASK 0x4UL /* Bit mask for LETIMER_COMP0 */
#define _LETIMER_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_COMP0_DEFAULT (_LETIMER_SYNCBUSY_COMP0_DEFAULT << 2) /* Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_COMP1 (0x1UL << 3) /* COMP1 Register Busy */
#define _LETIMER_SYNCBUSY_COMP1_SHIFT 3 /* Shift value for LETIMER_COMP1 */
#define _LETIMER_SYNCBUSY_COMP1_MASK 0x8UL /* Bit mask for LETIMER_COMP1 */
#define _LETIMER_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_COMP1_DEFAULT (_LETIMER_SYNCBUSY_COMP1_DEFAULT << 3) /* Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_REP0 (0x1UL << 4) /* REP0 Register Busy */
#define _LETIMER_SYNCBUSY_REP0_SHIFT 4 /* Shift value for LETIMER_REP0 */
#define _LETIMER_SYNCBUSY_REP0_MASK 0x10UL /* Bit mask for LETIMER_REP0 */
#define _LETIMER_SYNCBUSY_REP0_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_REP0_DEFAULT (_LETIMER_SYNCBUSY_REP0_DEFAULT << 4) /* Shifted mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_REP1 (0x1UL << 5) /* REP1 Register Busy */
#define _LETIMER_SYNCBUSY_REP1_SHIFT 5 /* Shift value for LETIMER_REP1 */
#define _LETIMER_SYNCBUSY_REP1_MASK 0x20UL /* Bit mask for LETIMER_REP1 */
#define _LETIMER_SYNCBUSY_REP1_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_SYNCBUSY */
#define LETIMER_SYNCBUSY_REP1_DEFAULT (_LETIMER_SYNCBUSY_REP1_DEFAULT << 5) /* Shifted mode DEFAULT for LETIMER_SYNCBUSY */
/* Bit fields for LETIMER ROUTE */
#define _LETIMER_ROUTE_RESETVALUE 0x00000000UL /* Default value for LETIMER_ROUTE */
#define _LETIMER_ROUTE_MASK 0x00000703UL /* Mask for LETIMER_ROUTE */
#define LETIMER_ROUTE_OUT0PEN (0x1UL << 0) /* Output 0 Pin Enable */
#define _LETIMER_ROUTE_OUT0PEN_SHIFT 0 /* Shift value for LETIMER_OUT0PEN */
#define _LETIMER_ROUTE_OUT0PEN_MASK 0x1UL /* Bit mask for LETIMER_OUT0PEN */
#define _LETIMER_ROUTE_OUT0PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_ROUTE */
#define LETIMER_ROUTE_OUT0PEN_DEFAULT (_LETIMER_ROUTE_OUT0PEN_DEFAULT << 0) /* Shifted mode DEFAULT for LETIMER_ROUTE */
#define LETIMER_ROUTE_OUT1PEN (0x1UL << 1) /* Output 1 Pin Enable */
#define _LETIMER_ROUTE_OUT1PEN_SHIFT 1 /* Shift value for LETIMER_OUT1PEN */
#define _LETIMER_ROUTE_OUT1PEN_MASK 0x2UL /* Bit mask for LETIMER_OUT1PEN */
#define _LETIMER_ROUTE_OUT1PEN_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_ROUTE */
#define LETIMER_ROUTE_OUT1PEN_DEFAULT (_LETIMER_ROUTE_OUT1PEN_DEFAULT << 1) /* Shifted mode DEFAULT for LETIMER_ROUTE */
#define _LETIMER_ROUTE_LOCATION_SHIFT 8 /* Shift value for LETIMER_LOCATION */
#define _LETIMER_ROUTE_LOCATION_MASK 0x700UL /* Bit mask for LETIMER_LOCATION */
#define _LETIMER_ROUTE_LOCATION_LOC0 0x00000000UL /* Mode LOC0 for LETIMER_ROUTE */
#define _LETIMER_ROUTE_LOCATION_DEFAULT 0x00000000UL /* Mode DEFAULT for LETIMER_ROUTE */
#define _LETIMER_ROUTE_LOCATION_LOC1 0x00000001UL /* Mode LOC1 for LETIMER_ROUTE */
#define _LETIMER_ROUTE_LOCATION_LOC2 0x00000002UL /* Mode LOC2 for LETIMER_ROUTE */
#define _LETIMER_ROUTE_LOCATION_LOC3 0x00000003UL /* Mode LOC3 for LETIMER_ROUTE */
#define LETIMER_ROUTE_LOCATION_LOC0 (_LETIMER_ROUTE_LOCATION_LOC0 << 8) /* Shifted mode LOC0 for LETIMER_ROUTE */
#define LETIMER_ROUTE_LOCATION_DEFAULT (_LETIMER_ROUTE_LOCATION_DEFAULT << 8) /* Shifted mode DEFAULT for LETIMER_ROUTE */
#define LETIMER_ROUTE_LOCATION_LOC1 (_LETIMER_ROUTE_LOCATION_LOC1 << 8) /* Shifted mode LOC1 for LETIMER_ROUTE */
#define LETIMER_ROUTE_LOCATION_LOC2 (_LETIMER_ROUTE_LOCATION_LOC2 << 8) /* Shifted mode LOC2 for LETIMER_ROUTE */
#define LETIMER_ROUTE_LOCATION_LOC3 (_LETIMER_ROUTE_LOCATION_LOC3 << 8) /* Shifted mode LOC3 for LETIMER_ROUTE */
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_LETIMER_H */
arch/arm/src/efm32/chip/efm32_leuart.h
+4
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@@ -68,6 +68,10 @@
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG) && !defined(CONFIG_EFM32_EFM32G)
# warning This is the EFM32GG/G header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
arch/arm/src/efm32/chip/efm32_pcnt.h
+529
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File diff suppressed because it is too large Load Diff
arch/arm/src/efm32/chip/efm32_prs.h
+610
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File diff suppressed because it is too large Load Diff
arch/arm/src/efm32/chip/efm32_rmu.h
+205
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@@ -0,0 +1,205 @@
/*******************************************************************************************************************************
* arch/arm/src/efm32/chip/efm32_rmu.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Authors: Pierre-noel Bouteville <pnb990@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RMU_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RMU_H
/*******************************************************************************************************************************
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG)
# warning This is the EFM32GG header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* RMU Register Offsets ********************************************************************************************************/
#define EFM32_RMU_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_RMU_RSTCAUSE_OFFSET 0x0004 /* Reset Cause Register */
#define EFM32_RMU_CMD_OFFSET 0x0008 /* Command Register */
/* RMU Register Addresses ******************************************************************************************************/
#define EFM32_RMU_CTRL (EFM32_RMU_BASE+EFM32_RMU_CTRL_OFFSET)
#define EFM32_RMU_RSTCAUSE (EFM32_RMU_BASE+EFM32_RMU_RSTCAUSE_OFFSET)
#define EFM32_RMU_CMD (EFM32_RMU_BASE+EFM32_RMU_CMD_OFFSET)
/* RMU Register Bit Field Definitions ******************************************************************************************/
/* Bit fields for RMU CTRL */
#define _RMU_CTRL_RESETVALUE 0x00000002UL /**< Default value for RMU_CTRL */
#define _RMU_CTRL_MASK 0x00000003UL /**< Mask for RMU_CTRL */
#define RMU_CTRL_LOCKUPRDIS (0x1UL << 0) /**< Lockup Reset Disable */
#define _RMU_CTRL_LOCKUPRDIS_SHIFT 0 /**< Shift value for RMU_LOCKUPRDIS */
#define _RMU_CTRL_LOCKUPRDIS_MASK 0x1UL /**< Bit mask for RMU_LOCKUPRDIS */
#define _RMU_CTRL_LOCKUPRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */
#define RMU_CTRL_LOCKUPRDIS_DEFAULT (_RMU_CTRL_LOCKUPRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */
#define RMU_CTRL_BURSTEN (0x1UL << 1) /**< Backup domain reset enable */
#define _RMU_CTRL_BURSTEN_SHIFT 1 /**< Shift value for RMU_BURSTEN */
#define _RMU_CTRL_BURSTEN_MASK 0x2UL /**< Bit mask for RMU_BURSTEN */
#define _RMU_CTRL_BURSTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for RMU_CTRL */
#define RMU_CTRL_BURSTEN_DEFAULT (_RMU_CTRL_BURSTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_CTRL */
/* Bit fields for RMU RSTCAUSE */
#define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */
#define _RMU_RSTCAUSE_MASK 0x0000FFFFUL /**< Mask for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */
#define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */
#define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */
#define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODUNREGRST (0x1UL << 1) /**< Brown Out Detector Unregulated Domain Reset */
#define _RMU_RSTCAUSE_BODUNREGRST_SHIFT 1 /**< Shift value for RMU_BODUNREGRST */
#define _RMU_RSTCAUSE_BODUNREGRST_MASK 0x2UL /**< Bit mask for RMU_BODUNREGRST */
#define _RMU_RSTCAUSE_BODUNREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODUNREGRST_DEFAULT (_RMU_RSTCAUSE_BODUNREGRST_DEFAULT << 1) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODREGRST (0x1UL << 2) /**< Brown Out Detector Regulated Domain Reset */
#define _RMU_RSTCAUSE_BODREGRST_SHIFT 2 /**< Shift value for RMU_BODREGRST */
#define _RMU_RSTCAUSE_BODREGRST_MASK 0x4UL /**< Bit mask for RMU_BODREGRST */
#define _RMU_RSTCAUSE_BODREGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODREGRST_DEFAULT (_RMU_RSTCAUSE_BODREGRST_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EXTRST (0x1UL << 3) /**< External Pin Reset */
#define _RMU_RSTCAUSE_EXTRST_SHIFT 3 /**< Shift value for RMU_EXTRST */
#define _RMU_RSTCAUSE_EXTRST_MASK 0x8UL /**< Bit mask for RMU_EXTRST */
#define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_WDOGRST (0x1UL << 4) /**< Watchdog Reset */
#define _RMU_RSTCAUSE_WDOGRST_SHIFT 4 /**< Shift value for RMU_WDOGRST */
#define _RMU_RSTCAUSE_WDOGRST_MASK 0x10UL /**< Bit mask for RMU_WDOGRST */
#define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 5) /**< LOCKUP Reset */
#define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 5 /**< Shift value for RMU_LOCKUPRST */
#define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x20UL /**< Bit mask for RMU_LOCKUPRST */
#define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 5) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_SYSREQRST (0x1UL << 6) /**< System Request Reset */
#define _RMU_RSTCAUSE_SYSREQRST_SHIFT 6 /**< Shift value for RMU_SYSREQRST */
#define _RMU_RSTCAUSE_SYSREQRST_MASK 0x40UL /**< Bit mask for RMU_SYSREQRST */
#define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 6) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EM4RST (0x1UL << 7) /**< EM4 Reset */
#define _RMU_RSTCAUSE_EM4RST_SHIFT 7 /**< Shift value for RMU_EM4RST */
#define _RMU_RSTCAUSE_EM4RST_MASK 0x80UL /**< Bit mask for RMU_EM4RST */
#define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 7) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EM4WURST (0x1UL << 8) /**< EM4 Wake-up Reset */
#define _RMU_RSTCAUSE_EM4WURST_SHIFT 8 /**< Shift value for RMU_EM4WURST */
#define _RMU_RSTCAUSE_EM4WURST_MASK 0x100UL /**< Bit mask for RMU_EM4WURST */
#define _RMU_RSTCAUSE_EM4WURST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_EM4WURST_DEFAULT (_RMU_RSTCAUSE_EM4WURST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODAVDD0 (0x1UL << 9) /**< AVDD0 Bod Reset */
#define _RMU_RSTCAUSE_BODAVDD0_SHIFT 9 /**< Shift value for RMU_BODAVDD0 */
#define _RMU_RSTCAUSE_BODAVDD0_MASK 0x200UL /**< Bit mask for RMU_BODAVDD0 */
#define _RMU_RSTCAUSE_BODAVDD0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODAVDD0_DEFAULT (_RMU_RSTCAUSE_BODAVDD0_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODAVDD1 (0x1UL << 10) /**< AVDD1 Bod Reset */
#define _RMU_RSTCAUSE_BODAVDD1_SHIFT 10 /**< Shift value for RMU_BODAVDD1 */
#define _RMU_RSTCAUSE_BODAVDD1_MASK 0x400UL /**< Bit mask for RMU_BODAVDD1 */
#define _RMU_RSTCAUSE_BODAVDD1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BODAVDD1_DEFAULT (_RMU_RSTCAUSE_BODAVDD1_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODVDDDREG (0x1UL << 11) /**< Backup Brown Out Detector, VDD_DREG */
#define _RMU_RSTCAUSE_BUBODVDDDREG_SHIFT 11 /**< Shift value for RMU_BUBODVDDDREG */
#define _RMU_RSTCAUSE_BUBODVDDDREG_MASK 0x800UL /**< Bit mask for RMU_BUBODVDDDREG */
#define _RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT (_RMU_RSTCAUSE_BUBODVDDDREG_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODBUVIN (0x1UL << 12) /**< Backup Brown Out Detector, BU_VIN */
#define _RMU_RSTCAUSE_BUBODBUVIN_SHIFT 12 /**< Shift value for RMU_BUBODBUVIN */
#define _RMU_RSTCAUSE_BUBODBUVIN_MASK 0x1000UL /**< Bit mask for RMU_BUBODBUVIN */
#define _RMU_RSTCAUSE_BUBODBUVIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODBUVIN_DEFAULT (_RMU_RSTCAUSE_BUBODBUVIN_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODUNREG (0x1UL << 13) /**< Backup Brown Out Detector Unregulated Domain */
#define _RMU_RSTCAUSE_BUBODUNREG_SHIFT 13 /**< Shift value for RMU_BUBODUNREG */
#define _RMU_RSTCAUSE_BUBODUNREG_MASK 0x2000UL /**< Bit mask for RMU_BUBODUNREG */
#define _RMU_RSTCAUSE_BUBODUNREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODUNREG_DEFAULT (_RMU_RSTCAUSE_BUBODUNREG_DEFAULT << 13) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODREG (0x1UL << 14) /**< Backup Brown Out Detector Regulated Domain */
#define _RMU_RSTCAUSE_BUBODREG_SHIFT 14 /**< Shift value for RMU_BUBODREG */
#define _RMU_RSTCAUSE_BUBODREG_MASK 0x4000UL /**< Bit mask for RMU_BUBODREG */
#define _RMU_RSTCAUSE_BUBODREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUBODREG_DEFAULT (_RMU_RSTCAUSE_BUBODREG_DEFAULT << 14) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUMODERST (0x1UL << 15) /**< Backup mode reset */
#define _RMU_RSTCAUSE_BUMODERST_SHIFT 15 /**< Shift value for RMU_BUMODERST */
#define _RMU_RSTCAUSE_BUMODERST_MASK 0x8000UL /**< Bit mask for RMU_BUMODERST */
#define _RMU_RSTCAUSE_BUMODERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
#define RMU_RSTCAUSE_BUMODERST_DEFAULT (_RMU_RSTCAUSE_BUMODERST_DEFAULT << 15) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
/* Bit fields for RMU CMD */
#define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */
#define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */
#define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */
#define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */
#define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */
#define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */
#define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RMU_H */
arch/arm/src/efm32/chip/efm32_romtable.h
+114
View File
@@ -0,0 +1,114 @@
/*******************************************************************************************************************************
* arch/arm/src/efm32/chip/efm32_romtable.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Authors: Pierre-noel Bouteville <pnb990@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ROMTABLE_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ROMTABLE_H
/*******************************************************************************************************************************
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG)
# warning This is the EFM32GG header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
#define ROMTABLE ((const struct efm32_romtable_s *)EFM32_ROMTABLE_BASE)
/* Bit fields for struct efm32_romtable_s */
#define _ROMTABLE_PID0_FAMILYLSB_MASK 0x000000C0UL /* Least Significant Bits [1:0] of CHIP FAMILY, mask */
#define _ROMTABLE_PID0_FAMILYLSB_SHIFT 6 /* Least Significant Bits [1:0] of CHIP FAMILY, shift */
#define _ROMTABLE_PID0_REVMAJOR_MASK 0x0000003FUL /* CHIP MAJOR Revison, mask */
#define _ROMTABLE_PID0_REVMAJOR_SHIFT 0 /* CHIP MAJOR Revison, shift */
#define _ROMTABLE_PID1_FAMILYMSB_MASK 0x0000000FUL /* Most Significant Bits [5:2] of CHIP FAMILY, mask */
#define _ROMTABLE_PID1_FAMILYMSB_SHIFT 0 /* Most Significant Bits [5:2] of CHIP FAMILY, shift */
#define _ROMTABLE_PID2_REVMINORMSB_MASK 0x000000F0UL /* Most Significant Bits [7:4] of CHIP MINOR revision, mask */
#define _ROMTABLE_PID2_REVMINORMSB_SHIFT 4 /* Most Significant Bits [7:4] of CHIP MINOR revision, mask */
#define _ROMTABLE_PID3_REVMINORLSB_MASK 0x000000F0UL /* Least Significant Bits [3:0] of CHIP MINOR revision, mask */
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT 4 /* Least Significant Bits [3:0] of CHIP MINOR revision, shift */
/*******************************************************************************************************************************
* Public Type Definitions
*******************************************************************************************************************************/
struct efm32_romtable_s
{
const uint32_t pid4; /* JEP_106_BANK */
const uint32_t pid5; /* Unused */
const uint32_t pid6; /* Unused */
const uint32_t pid7; /* Unused */
const uint32_t pid0; /* Chip family LSB, chip major revision */
const uint32_t pid1; /* JEP_106_NO, Chip family MSB */
const uint32_t pid2; /* Chip minor rev MSB, JEP_106_PRESENT, JEP_106_NO */
const uint32_t pid3; /* Chip minor rev LSB */
const uint32_t cid0; /* Unused */
};
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_ROMTABLE_H */
arch/arm/src/efm32/chip/efm32_rtc.h
+281
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@@ -0,0 +1,281 @@
/*******************************************************************************************************************************
* arch/arm/src/efm32/chip/efm32_rtc.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Authors: Pierre-noel Bouteville <pnb990@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RTC_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RTC_H
/*******************************************************************************************************************************
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG)
# warning This is the EFM32GG header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* RTC Register Offsets ********************************************************************************************************/
#define EFM32_RTC_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_RTC_CNT_OFFSET 0x0004 /* Counter Value Register */
#define EFM32_RTC_COMP0_OFFSET 0x0008 /* Compare Value Register 0 */
#define EFM32_RTC_COMP1_OFFSET 0x000c /* Compare Value Register 1 */
#define EFM32_RTC_IF_OFFSET 0x0010 /* Interrupt Flag Register */
#define EFM32_RTC_IFS_OFFSET 0x0014 /* Interrupt Flag Set Register */
#define EFM32_RTC_IFC_OFFSET 0x0018 /* Interrupt Flag Clear Register */
#define EFM32_RTC_IEN_OFFSET 0x001c /* Interrupt Enable Register */
#define EFM32_RTC_FREEZE_OFFSET 0x0020 /* Freeze Register */
#define EFM32_RTC_SYNCBUSY_OFFSET 0x0024 /* Synchronization Busy Register */
/* RTC Register Addresses ******************************************************************************************************/
#define EFM32_RTC_CTRL (EFM32_RTC_BASE+EFM32_RTC_CTRL_OFFSET)
#define EFM32_RTC_CNT (EFM32_RTC_BASE+EFM32_RTC_CNT_OFFSET)
#define EFM32_RTC_COMP0 (EFM32_RTC_BASE+EFM32_RTC_COMP0_OFFSET)
#define EFM32_RTC_COMP1 (EFM32_RTC_BASE+EFM32_RTC_COMP1_OFFSET)
#define EFM32_RTC_IF (EFM32_RTC_BASE+EFM32_RTC_IF_OFFSET)
#define EFM32_RTC_IFS (EFM32_RTC_BASE+EFM32_RTC_IFS_OFFSET)
#define EFM32_RTC_IFC (EFM32_RTC_BASE+EFM32_RTC_IFC_OFFSET)
#define EFM32_RTC_IEN (EFM32_RTC_BASE+EFM32_RTC_IEN_OFFSET)
#define EFM32_RTC_FREEZE (EFM32_RTC_BASE+EFM32_RTC_FREEZE_OFFSET)
#define EFM32_RTC_SYNCBUSY (EFM32_RTC_BASE+EFM32_RTC_SYNCBUSY_OFFSET)
/* RTC Register Bit Field Definitions ******************************************************************************************/
/* Bit fields for RTC CTRL */
#define _RTC_CTRL_RESETVALUE 0x00000000UL /* Default value for RTC_CTRL */
#define _RTC_CTRL_MASK 0x00000007UL /* Mask for RTC_CTRL */
#define RTC_CTRL_EN (0x1UL << 0) /* RTC Enable */
#define _RTC_CTRL_EN_SHIFT 0 /* Shift value for RTC_EN */
#define _RTC_CTRL_EN_MASK 0x1UL /* Bit mask for RTC_EN */
#define _RTC_CTRL_EN_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_CTRL */
#define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_CTRL */
#define RTC_CTRL_DEBUGRUN (0x1UL << 1) /* Debug Mode Run Enable */
#define _RTC_CTRL_DEBUGRUN_SHIFT 1 /* Shift value for RTC_DEBUGRUN */
#define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /* Bit mask for RTC_DEBUGRUN */
#define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_CTRL */
#define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) /* Shifted mode DEFAULT for RTC_CTRL */
#define RTC_CTRL_COMP0TOP (0x1UL << 2) /* Compare Channel 0 is Top Value */
#define _RTC_CTRL_COMP0TOP_SHIFT 2 /* Shift value for RTC_COMP0TOP */
#define _RTC_CTRL_COMP0TOP_MASK 0x4UL /* Bit mask for RTC_COMP0TOP */
#define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_CTRL */
#define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /* Mode DISABLE for RTC_CTRL */
#define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /* Mode ENABLE for RTC_CTRL */
#define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) /* Shifted mode DEFAULT for RTC_CTRL */
#define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) /* Shifted mode DISABLE for RTC_CTRL */
#define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) /* Shifted mode ENABLE for RTC_CTRL */
/* Bit fields for RTC CNT */
#define _RTC_CNT_RESETVALUE 0x00000000UL /* Default value for RTC_CNT */
#define _RTC_CNT_MASK 0x00FFFFFFUL /* Mask for RTC_CNT */
#define _RTC_CNT_CNT_SHIFT 0 /* Shift value for RTC_CNT */
#define _RTC_CNT_CNT_MASK 0xFFFFFFUL /* Bit mask for RTC_CNT */
#define _RTC_CNT_CNT_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_CNT */
#define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_CNT */
/* Bit fields for RTC COMP0 */
#define _RTC_COMP0_RESETVALUE 0x00000000UL /* Default value for RTC_COMP0 */
#define _RTC_COMP0_MASK 0x00FFFFFFUL /* Mask for RTC_COMP0 */
#define _RTC_COMP0_COMP0_SHIFT 0 /* Shift value for RTC_COMP0 */
#define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL /* Bit mask for RTC_COMP0 */
#define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_COMP0 */
#define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_COMP0 */
/* Bit fields for RTC COMP1 */
#define _RTC_COMP1_RESETVALUE 0x00000000UL /* Default value for RTC_COMP1 */
#define _RTC_COMP1_MASK 0x00FFFFFFUL /* Mask for RTC_COMP1 */
#define _RTC_COMP1_COMP1_SHIFT 0 /* Shift value for RTC_COMP1 */
#define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL /* Bit mask for RTC_COMP1 */
#define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_COMP1 */
#define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_COMP1 */
/* Bit fields for RTC IF */
#define _RTC_IF_RESETVALUE 0x00000000UL /* Default value for RTC_IF */
#define _RTC_IF_MASK 0x00000007UL /* Mask for RTC_IF */
#define RTC_IF_OF (0x1UL << 0) /* Overflow Interrupt Flag */
#define _RTC_IF_OF_SHIFT 0 /* Shift value for RTC_OF */
#define _RTC_IF_OF_MASK 0x1UL /* Bit mask for RTC_OF */
#define _RTC_IF_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IF */
#define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_IF */
#define RTC_IF_COMP0 (0x1UL << 1) /* Compare Match 0 Interrupt Flag */
#define _RTC_IF_COMP0_SHIFT 1 /* Shift value for RTC_COMP0 */
#define _RTC_IF_COMP0_MASK 0x2UL /* Bit mask for RTC_COMP0 */
#define _RTC_IF_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IF */
#define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for RTC_IF */
#define RTC_IF_COMP1 (0x1UL << 2) /* Compare Match 1 Interrupt Flag */
#define _RTC_IF_COMP1_SHIFT 2 /* Shift value for RTC_COMP1 */
#define _RTC_IF_COMP1_MASK 0x4UL /* Bit mask for RTC_COMP1 */
#define _RTC_IF_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IF */
#define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2) /* Shifted mode DEFAULT for RTC_IF */
/* Bit fields for RTC IFS */
#define _RTC_IFS_RESETVALUE 0x00000000UL /* Default value for RTC_IFS */
#define _RTC_IFS_MASK 0x00000007UL /* Mask for RTC_IFS */
#define RTC_IFS_OF (0x1UL << 0) /* Set Overflow Interrupt Flag */
#define _RTC_IFS_OF_SHIFT 0 /* Shift value for RTC_OF */
#define _RTC_IFS_OF_MASK 0x1UL /* Bit mask for RTC_OF */
#define _RTC_IFS_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IFS */
#define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_IFS */
#define RTC_IFS_COMP0 (0x1UL << 1) /* Set Compare match 0 Interrupt Flag */
#define _RTC_IFS_COMP0_SHIFT 1 /* Shift value for RTC_COMP0 */
#define _RTC_IFS_COMP0_MASK 0x2UL /* Bit mask for RTC_COMP0 */
#define _RTC_IFS_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IFS */
#define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for RTC_IFS */
#define RTC_IFS_COMP1 (0x1UL << 2) /* Set Compare match 1 Interrupt Flag */
#define _RTC_IFS_COMP1_SHIFT 2 /* Shift value for RTC_COMP1 */
#define _RTC_IFS_COMP1_MASK 0x4UL /* Bit mask for RTC_COMP1 */
#define _RTC_IFS_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IFS */
#define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2) /* Shifted mode DEFAULT for RTC_IFS */
/* Bit fields for RTC IFC */
#define _RTC_IFC_RESETVALUE 0x00000000UL /* Default value for RTC_IFC */
#define _RTC_IFC_MASK 0x00000007UL /* Mask for RTC_IFC */
#define RTC_IFC_OF (0x1UL << 0) /* Clear Overflow Interrupt Flag */
#define _RTC_IFC_OF_SHIFT 0 /* Shift value for RTC_OF */
#define _RTC_IFC_OF_MASK 0x1UL /* Bit mask for RTC_OF */
#define _RTC_IFC_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IFC */
#define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_IFC */
#define RTC_IFC_COMP0 (0x1UL << 1) /* Clear Compare match 0 Interrupt Flag */
#define _RTC_IFC_COMP0_SHIFT 1 /* Shift value for RTC_COMP0 */
#define _RTC_IFC_COMP0_MASK 0x2UL /* Bit mask for RTC_COMP0 */
#define _RTC_IFC_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IFC */
#define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for RTC_IFC */
#define RTC_IFC_COMP1 (0x1UL << 2) /* Clear Compare match 1 Interrupt Flag */
#define _RTC_IFC_COMP1_SHIFT 2 /* Shift value for RTC_COMP1 */
#define _RTC_IFC_COMP1_MASK 0x4UL /* Bit mask for RTC_COMP1 */
#define _RTC_IFC_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IFC */
#define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2) /* Shifted mode DEFAULT for RTC_IFC */
/* Bit fields for RTC IEN */
#define _RTC_IEN_RESETVALUE 0x00000000UL /* Default value for RTC_IEN */
#define _RTC_IEN_MASK 0x00000007UL /* Mask for RTC_IEN */
#define RTC_IEN_OF (0x1UL << 0) /* Overflow Interrupt Enable */
#define _RTC_IEN_OF_SHIFT 0 /* Shift value for RTC_OF */
#define _RTC_IEN_OF_MASK 0x1UL /* Bit mask for RTC_OF */
#define _RTC_IEN_OF_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IEN */
#define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_IEN */
#define RTC_IEN_COMP0 (0x1UL << 1) /* Compare Match 0 Interrupt Enable */
#define _RTC_IEN_COMP0_SHIFT 1 /* Shift value for RTC_COMP0 */
#define _RTC_IEN_COMP0_MASK 0x2UL /* Bit mask for RTC_COMP0 */
#define _RTC_IEN_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IEN */
#define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for RTC_IEN */
#define RTC_IEN_COMP1 (0x1UL << 2) /* Compare Match 1 Interrupt Enable */
#define _RTC_IEN_COMP1_SHIFT 2 /* Shift value for RTC_COMP1 */
#define _RTC_IEN_COMP1_MASK 0x4UL /* Bit mask for RTC_COMP1 */
#define _RTC_IEN_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_IEN */
#define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2) /* Shifted mode DEFAULT for RTC_IEN */
/* Bit fields for RTC FREEZE */
#define _RTC_FREEZE_RESETVALUE 0x00000000UL /* Default value for RTC_FREEZE */
#define _RTC_FREEZE_MASK 0x00000001UL /* Mask for RTC_FREEZE */
#define RTC_FREEZE_REGFREEZE (0x1UL << 0) /* Register Update Freeze */
#define _RTC_FREEZE_REGFREEZE_SHIFT 0 /* Shift value for RTC_REGFREEZE */
#define _RTC_FREEZE_REGFREEZE_MASK 0x1UL /* Bit mask for RTC_REGFREEZE */
#define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_FREEZE */
#define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /* Mode UPDATE for RTC_FREEZE */
#define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /* Mode FREEZE for RTC_FREEZE */
#define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_FREEZE */
#define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0) /* Shifted mode UPDATE for RTC_FREEZE */
#define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0) /* Shifted mode FREEZE for RTC_FREEZE */
/* Bit fields for RTC SYNCBUSY */
#define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL /* Default value for RTC_SYNCBUSY */
#define _RTC_SYNCBUSY_MASK 0x00000007UL /* Mask for RTC_SYNCBUSY */
#define RTC_SYNCBUSY_CTRL (0x1UL << 0) /* CTRL Register Busy */
#define _RTC_SYNCBUSY_CTRL_SHIFT 0 /* Shift value for RTC_CTRL */
#define _RTC_SYNCBUSY_CTRL_MASK 0x1UL /* Bit mask for RTC_CTRL */
#define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_SYNCBUSY */
#define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0) /* Shifted mode DEFAULT for RTC_SYNCBUSY */
#define RTC_SYNCBUSY_COMP0 (0x1UL << 1) /* COMP0 Register Busy */
#define _RTC_SYNCBUSY_COMP0_SHIFT 1 /* Shift value for RTC_COMP0 */
#define _RTC_SYNCBUSY_COMP0_MASK 0x2UL /* Bit mask for RTC_COMP0 */
#define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_SYNCBUSY */
#define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) /* Shifted mode DEFAULT for RTC_SYNCBUSY */
#define RTC_SYNCBUSY_COMP1 (0x1UL << 2) /* COMP1 Register Busy */
#define _RTC_SYNCBUSY_COMP1_SHIFT 2 /* Shift value for RTC_COMP1 */
#define _RTC_SYNCBUSY_COMP1_MASK 0x4UL /* Bit mask for RTC_COMP1 */
#define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /* Mode DEFAULT for RTC_SYNCBUSY */
#define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /* Shifted mode DEFAULT for RTC_SYNCBUSY */
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_RTC_H */
arch/arm/src/efm32/chip/efm32_timer.h
+1219
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arch/arm/src/efm32/chip/efm32_usart.h
+5
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@@ -65,8 +65,13 @@
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG) && !defined(CONFIG_EFM32_EFM32G)
# warning This is the EFM32GG/G header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
arch/arm/src/efm32/chip/efm32_usb.h
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arch/arm/src/efm32/chip/efm32_vcmp.h
+255
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@@ -0,0 +1,255 @@
/*******************************************************************************************************************************
* arch/arm/src/efm32/chip/efm32_vcmp.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Authors: Pierre-noel Bouteville <pnb990@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_VCMP_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_VCMP_H
/*******************************************************************************************************************************
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG)
# warning This is the EFM32GG header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* VCMP Register Offsets *******************************************************************************************************/
#define EFM32_VCMP_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_VCMP_INPUTSEL_OFFSET 0x0004 /* Input Selection Register */
#define EFM32_VCMP_STATUS_OFFSET 0x0008 /* Status Register */
#define EFM32_VCMP_IEN_OFFSET 0x000c /* Interrupt Enable Register */
#define EFM32_VCMP_IF_OFFSET 0x0010 /* Interrupt Flag Register */
#define EFM32_VCMP_IFS_OFFSET 0x0014 /* Interrupt Flag Set Register */
#define EFM32_VCMP_IFC_OFFSET 0x0018 /* Interrupt Flag Clear Register */
/* VCMP Register Addresses *****************************************************************************************************/
#define EFM32_VCMP_CTRL (EFM32_VCMP_BASE+EFM32_VCMP_CTRL_OFFSET)
#define EFM32_VCMP_INPUTSEL (EFM32_VCMP_BASE+EFM32_VCMP_INPUTSEL_OFFSET)
#define EFM32_VCMP_STATUS (EFM32_VCMP_BASE+EFM32_VCMP_STATUS_OFFSET)
#define EFM32_VCMP_IEN (EFM32_VCMP_BASE+EFM32_VCMP_IEN_OFFSET)
#define EFM32_VCMP_IF (EFM32_VCMP_BASE+EFM32_VCMP_IF_OFFSET)
#define EFM32_VCMP_IFS (EFM32_VCMP_BASE+EFM32_VCMP_IFS_OFFSET)
#define EFM32_VCMP_IFC (EFM32_VCMP_BASE+EFM32_VCMP_IFC_OFFSET)
/* VCMP Register Bit Field Definitions *****************************************************************************************/
/* Bit fields for VCMP CTRL */
#define _VCMP_CTRL_RESETVALUE 0x47000000UL /* Default value for VCMP_CTRL */
#define _VCMP_CTRL_MASK 0x4F030715UL /* Mask for VCMP_CTRL */
#define VCMP_CTRL_EN (0x1UL << 0) /* Voltage Supply Comparator Enable */
#define _VCMP_CTRL_EN_SHIFT 0 /* Shift value for VCMP_EN */
#define _VCMP_CTRL_EN_MASK 0x1UL /* Bit mask for VCMP_EN */
#define _VCMP_CTRL_EN_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_EN_DEFAULT (_VCMP_CTRL_EN_DEFAULT << 0) /* Shifted mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_INACTVAL (0x1UL << 2) /* Inactive Value */
#define _VCMP_CTRL_INACTVAL_SHIFT 2 /* Shift value for VCMP_INACTVAL */
#define _VCMP_CTRL_INACTVAL_MASK 0x4UL /* Bit mask for VCMP_INACTVAL */
#define _VCMP_CTRL_INACTVAL_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_INACTVAL_DEFAULT (_VCMP_CTRL_INACTVAL_DEFAULT << 2) /* Shifted mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_HYSTEN (0x1UL << 4) /* Hysteresis Enable */
#define _VCMP_CTRL_HYSTEN_SHIFT 4 /* Shift value for VCMP_HYSTEN */
#define _VCMP_CTRL_HYSTEN_MASK 0x10UL /* Bit mask for VCMP_HYSTEN */
#define _VCMP_CTRL_HYSTEN_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_HYSTEN_DEFAULT (_VCMP_CTRL_HYSTEN_DEFAULT << 4) /* Shifted mode DEFAULT for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_SHIFT 8 /* Shift value for VCMP_WARMTIME */
#define _VCMP_CTRL_WARMTIME_MASK 0x700UL /* Bit mask for VCMP_WARMTIME */
#define _VCMP_CTRL_WARMTIME_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_4CYCLES 0x00000000UL /* Mode 4CYCLES for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_8CYCLES 0x00000001UL /* Mode 8CYCLES for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_16CYCLES 0x00000002UL /* Mode 16CYCLES for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_32CYCLES 0x00000003UL /* Mode 32CYCLES for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_64CYCLES 0x00000004UL /* Mode 64CYCLES for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_128CYCLES 0x00000005UL /* Mode 128CYCLES for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_256CYCLES 0x00000006UL /* Mode 256CYCLES for VCMP_CTRL */
#define _VCMP_CTRL_WARMTIME_512CYCLES 0x00000007UL /* Mode 512CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_DEFAULT (_VCMP_CTRL_WARMTIME_DEFAULT << 8) /* Shifted mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_4CYCLES (_VCMP_CTRL_WARMTIME_4CYCLES << 8) /* Shifted mode 4CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_8CYCLES (_VCMP_CTRL_WARMTIME_8CYCLES << 8) /* Shifted mode 8CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_16CYCLES (_VCMP_CTRL_WARMTIME_16CYCLES << 8) /* Shifted mode 16CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_32CYCLES (_VCMP_CTRL_WARMTIME_32CYCLES << 8) /* Shifted mode 32CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_64CYCLES (_VCMP_CTRL_WARMTIME_64CYCLES << 8) /* Shifted mode 64CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_128CYCLES (_VCMP_CTRL_WARMTIME_128CYCLES << 8) /* Shifted mode 128CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_256CYCLES (_VCMP_CTRL_WARMTIME_256CYCLES << 8) /* Shifted mode 256CYCLES for VCMP_CTRL */
#define VCMP_CTRL_WARMTIME_512CYCLES (_VCMP_CTRL_WARMTIME_512CYCLES << 8) /* Shifted mode 512CYCLES for VCMP_CTRL */
#define VCMP_CTRL_IRISE (0x1UL << 16) /* Rising Edge Interrupt Sense */
#define _VCMP_CTRL_IRISE_SHIFT 16 /* Shift value for VCMP_IRISE */
#define _VCMP_CTRL_IRISE_MASK 0x10000UL /* Bit mask for VCMP_IRISE */
#define _VCMP_CTRL_IRISE_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_IRISE_DEFAULT (_VCMP_CTRL_IRISE_DEFAULT << 16) /* Shifted mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_IFALL (0x1UL << 17) /* Falling Edge Interrupt Sense */
#define _VCMP_CTRL_IFALL_SHIFT 17 /* Shift value for VCMP_IFALL */
#define _VCMP_CTRL_IFALL_MASK 0x20000UL /* Bit mask for VCMP_IFALL */
#define _VCMP_CTRL_IFALL_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_IFALL_DEFAULT (_VCMP_CTRL_IFALL_DEFAULT << 17) /* Shifted mode DEFAULT for VCMP_CTRL */
#define _VCMP_CTRL_BIASPROG_SHIFT 24 /* Shift value for VCMP_BIASPROG */
#define _VCMP_CTRL_BIASPROG_MASK 0xF000000UL /* Bit mask for VCMP_BIASPROG */
#define _VCMP_CTRL_BIASPROG_DEFAULT 0x00000007UL /* Mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_BIASPROG_DEFAULT (_VCMP_CTRL_BIASPROG_DEFAULT << 24) /* Shifted mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_HALFBIAS (0x1UL << 30) /* Half Bias Current */
#define _VCMP_CTRL_HALFBIAS_SHIFT 30 /* Shift value for VCMP_HALFBIAS */
#define _VCMP_CTRL_HALFBIAS_MASK 0x40000000UL /* Bit mask for VCMP_HALFBIAS */
#define _VCMP_CTRL_HALFBIAS_DEFAULT 0x00000001UL /* Mode DEFAULT for VCMP_CTRL */
#define VCMP_CTRL_HALFBIAS_DEFAULT (_VCMP_CTRL_HALFBIAS_DEFAULT << 30) /* Shifted mode DEFAULT for VCMP_CTRL */
/* Bit fields for VCMP INPUTSEL */
#define _VCMP_INPUTSEL_RESETVALUE 0x00000000UL /* Default value for VCMP_INPUTSEL */
#define _VCMP_INPUTSEL_MASK 0x0000013FUL /* Mask for VCMP_INPUTSEL */
#define _VCMP_INPUTSEL_TRIGLEVEL_SHIFT 0 /* Shift value for VCMP_TRIGLEVEL */
#define _VCMP_INPUTSEL_TRIGLEVEL_MASK 0x3FUL /* Bit mask for VCMP_TRIGLEVEL */
#define _VCMP_INPUTSEL_TRIGLEVEL_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_INPUTSEL */
#define VCMP_INPUTSEL_TRIGLEVEL_DEFAULT (_VCMP_INPUTSEL_TRIGLEVEL_DEFAULT << 0) /* Shifted mode DEFAULT for VCMP_INPUTSEL */
#define VCMP_INPUTSEL_LPREF (0x1UL << 8) /* Low Power Reference */
#define _VCMP_INPUTSEL_LPREF_SHIFT 8 /* Shift value for VCMP_LPREF */
#define _VCMP_INPUTSEL_LPREF_MASK 0x100UL /* Bit mask for VCMP_LPREF */
#define _VCMP_INPUTSEL_LPREF_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_INPUTSEL */
#define VCMP_INPUTSEL_LPREF_DEFAULT (_VCMP_INPUTSEL_LPREF_DEFAULT << 8) /* Shifted mode DEFAULT for VCMP_INPUTSEL */
/* Bit fields for VCMP STATUS */
#define _VCMP_STATUS_RESETVALUE 0x00000000UL /* Default value for VCMP_STATUS */
#define _VCMP_STATUS_MASK 0x00000003UL /* Mask for VCMP_STATUS */
#define VCMP_STATUS_VCMPACT (0x1UL << 0) /* Voltage Supply Comparator Active */
#define _VCMP_STATUS_VCMPACT_SHIFT 0 /* Shift value for VCMP_VCMPACT */
#define _VCMP_STATUS_VCMPACT_MASK 0x1UL /* Bit mask for VCMP_VCMPACT */
#define _VCMP_STATUS_VCMPACT_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_STATUS */
#define VCMP_STATUS_VCMPACT_DEFAULT (_VCMP_STATUS_VCMPACT_DEFAULT << 0) /* Shifted mode DEFAULT for VCMP_STATUS */
#define VCMP_STATUS_VCMPOUT (0x1UL << 1) /* Voltage Supply Comparator Output */
#define _VCMP_STATUS_VCMPOUT_SHIFT 1 /* Shift value for VCMP_VCMPOUT */
#define _VCMP_STATUS_VCMPOUT_MASK 0x2UL /* Bit mask for VCMP_VCMPOUT */
#define _VCMP_STATUS_VCMPOUT_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_STATUS */
#define VCMP_STATUS_VCMPOUT_DEFAULT (_VCMP_STATUS_VCMPOUT_DEFAULT << 1) /* Shifted mode DEFAULT for VCMP_STATUS */
/* Bit fields for VCMP IEN */
#define _VCMP_IEN_RESETVALUE 0x00000000UL /* Default value for VCMP_IEN */
#define _VCMP_IEN_MASK 0x00000003UL /* Mask for VCMP_IEN */
#define VCMP_IEN_EDGE (0x1UL << 0) /* Edge Trigger Interrupt Enable */
#define _VCMP_IEN_EDGE_SHIFT 0 /* Shift value for VCMP_EDGE */
#define _VCMP_IEN_EDGE_MASK 0x1UL /* Bit mask for VCMP_EDGE */
#define _VCMP_IEN_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IEN */
#define VCMP_IEN_EDGE_DEFAULT (_VCMP_IEN_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for VCMP_IEN */
#define VCMP_IEN_WARMUP (0x1UL << 1) /* Warm-up Interrupt Enable */
#define _VCMP_IEN_WARMUP_SHIFT 1 /* Shift value for VCMP_WARMUP */
#define _VCMP_IEN_WARMUP_MASK 0x2UL /* Bit mask for VCMP_WARMUP */
#define _VCMP_IEN_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IEN */
#define VCMP_IEN_WARMUP_DEFAULT (_VCMP_IEN_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for VCMP_IEN */
/* Bit fields for VCMP IF */
#define _VCMP_IF_RESETVALUE 0x00000000UL /* Default value for VCMP_IF */
#define _VCMP_IF_MASK 0x00000003UL /* Mask for VCMP_IF */
#define VCMP_IF_EDGE (0x1UL << 0) /* Edge Triggered Interrupt Flag */
#define _VCMP_IF_EDGE_SHIFT 0 /* Shift value for VCMP_EDGE */
#define _VCMP_IF_EDGE_MASK 0x1UL /* Bit mask for VCMP_EDGE */
#define _VCMP_IF_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IF */
#define VCMP_IF_EDGE_DEFAULT (_VCMP_IF_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for VCMP_IF */
#define VCMP_IF_WARMUP (0x1UL << 1) /* Warm-up Interrupt Flag */
#define _VCMP_IF_WARMUP_SHIFT 1 /* Shift value for VCMP_WARMUP */
#define _VCMP_IF_WARMUP_MASK 0x2UL /* Bit mask for VCMP_WARMUP */
#define _VCMP_IF_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IF */
#define VCMP_IF_WARMUP_DEFAULT (_VCMP_IF_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for VCMP_IF */
/* Bit fields for VCMP IFS */
#define _VCMP_IFS_RESETVALUE 0x00000000UL /* Default value for VCMP_IFS */
#define _VCMP_IFS_MASK 0x00000003UL /* Mask for VCMP_IFS */
#define VCMP_IFS_EDGE (0x1UL << 0) /* Edge Triggered Interrupt Flag Set */
#define _VCMP_IFS_EDGE_SHIFT 0 /* Shift value for VCMP_EDGE */
#define _VCMP_IFS_EDGE_MASK 0x1UL /* Bit mask for VCMP_EDGE */
#define _VCMP_IFS_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IFS */
#define VCMP_IFS_EDGE_DEFAULT (_VCMP_IFS_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for VCMP_IFS */
#define VCMP_IFS_WARMUP (0x1UL << 1) /* Warm-up Interrupt Flag Set */
#define _VCMP_IFS_WARMUP_SHIFT 1 /* Shift value for VCMP_WARMUP */
#define _VCMP_IFS_WARMUP_MASK 0x2UL /* Bit mask for VCMP_WARMUP */
#define _VCMP_IFS_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IFS */
#define VCMP_IFS_WARMUP_DEFAULT (_VCMP_IFS_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for VCMP_IFS */
/* Bit fields for VCMP IFC */
#define _VCMP_IFC_RESETVALUE 0x00000000UL /* Default value for VCMP_IFC */
#define _VCMP_IFC_MASK 0x00000003UL /* Mask for VCMP_IFC */
#define VCMP_IFC_EDGE (0x1UL << 0) /* Edge Triggered Interrupt Flag Clear */
#define _VCMP_IFC_EDGE_SHIFT 0 /* Shift value for VCMP_EDGE */
#define _VCMP_IFC_EDGE_MASK 0x1UL /* Bit mask for VCMP_EDGE */
#define _VCMP_IFC_EDGE_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IFC */
#define VCMP_IFC_EDGE_DEFAULT (_VCMP_IFC_EDGE_DEFAULT << 0) /* Shifted mode DEFAULT for VCMP_IFC */
#define VCMP_IFC_WARMUP (0x1UL << 1) /* Warm-up Interrupt Flag Clear */
#define _VCMP_IFC_WARMUP_SHIFT 1 /* Shift value for VCMP_WARMUP */
#define _VCMP_IFC_WARMUP_MASK 0x2UL /* Bit mask for VCMP_WARMUP */
#define _VCMP_IFC_WARMUP_DEFAULT 0x00000000UL /* Mode DEFAULT for VCMP_IFC */
#define VCMP_IFC_WARMUP_DEFAULT (_VCMP_IFC_WARMUP_DEFAULT << 1) /* Shifted mode DEFAULT for VCMP_IFC */
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_VCMP_H */
arch/arm/src/efm32/chip/efm32_wdog.h
+178
View File
@@ -0,0 +1,178 @@
/*******************************************************************************************************************************
* arch/arm/src/efm32/chip/efm32_wdog.h
*
* Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software.@n
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.@n
* 3. This notice may not be removed or altered from any source distribution.
*
* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
* has no obligation to support this Software. Silicon Laboratories, Inc. is
* providing the Software "AS IS", with no express or implied warranties of any
* kind, including, but not limited to, any implied warranties of
* merchantability or fitness for any particular purpose or warranties against
* infringement of any proprietary rights of a third party.
*
* Silicon Laboratories, Inc. will not be liable for any consequential,
* incidental, or special damages, or any other relief, or for any claim by
* any third party, arising from your use of this Software.
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
* Authors: Pierre-noel Bouteville <pnb990@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_WDOG_H
#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_WDOG_H
/*******************************************************************************************************************************
* Included Files
*******************************************************************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
#if !defined(CONFIG_EFM32_EFM32GG)
# warning This is the EFM32GG header file; Review/modification needed for this archtecture
#endif
/*******************************************************************************************************************************
* Pre-processor Definitions
*******************************************************************************************************************************/
/* WDOG Register Offsets *******************************************************************************************************/
#define EFM32_WDOG_CTRL_OFFSET 0x0000 /* Control Register */
#define EFM32_WDOG_CMD_OFFSET 0x0004 /* Command Register */
#define EFM32_WDOG_SYNCBUSY_OFFSET 0x0008 /* Synchronization Busy Register */
/* WDOG Register Addresses *****************************************************************************************************/
#define EFM32_WDOG_CTRL (EFM32_WDOG_BASE+EFM32_WDOG_CTRL_OFFSET)
#define EFM32_WDOG_CMD (EFM32_WDOG_BASE+EFM32_WDOG_CMD_OFFSET)
#define EFM32_WDOG_SYNCBUSY (EFM32_WDOG_BASE+EFM32_WDOG_SYNCBUSY_OFFSET)
/* WDOG Register Bit Field Definitions *****************************************************************************************/
/* Bit fields for WDOG CTRL */
#define _WDOG_CTRL_RESETVALUE 0x00000F00UL /* Default value for WDOG_CTRL */
#define _WDOG_CTRL_MASK 0x00003F7FUL /* Mask for WDOG_CTRL */
#define WDOG_CTRL_EN (0x1UL << 0) /* Watchdog Timer Enable */
#define _WDOG_CTRL_EN_SHIFT 0 /* Shift value for WDOG_EN */
#define _WDOG_CTRL_EN_MASK 0x1UL /* Bit mask for WDOG_EN */
#define _WDOG_CTRL_EN_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EN_DEFAULT (_WDOG_CTRL_EN_DEFAULT << 0) /* Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_DEBUGRUN (0x1UL << 1) /* Debug Mode Run Enable */
#define _WDOG_CTRL_DEBUGRUN_SHIFT 1 /* Shift value for WDOG_DEBUGRUN */
#define _WDOG_CTRL_DEBUGRUN_MASK 0x2UL /* Bit mask for WDOG_DEBUGRUN */
#define _WDOG_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_DEBUGRUN_DEFAULT (_WDOG_CTRL_DEBUGRUN_DEFAULT << 1) /* Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM2RUN (0x1UL << 2) /* Energy Mode 2 Run Enable */
#define _WDOG_CTRL_EM2RUN_SHIFT 2 /* Shift value for WDOG_EM2RUN */
#define _WDOG_CTRL_EM2RUN_MASK 0x4UL /* Bit mask for WDOG_EM2RUN */
#define _WDOG_CTRL_EM2RUN_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM2RUN_DEFAULT (_WDOG_CTRL_EM2RUN_DEFAULT << 2) /* Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM3RUN (0x1UL << 3) /* Energy Mode 3 Run Enable */
#define _WDOG_CTRL_EM3RUN_SHIFT 3 /* Shift value for WDOG_EM3RUN */
#define _WDOG_CTRL_EM3RUN_MASK 0x8UL /* Bit mask for WDOG_EM3RUN */
#define _WDOG_CTRL_EM3RUN_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM3RUN_DEFAULT (_WDOG_CTRL_EM3RUN_DEFAULT << 3) /* Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_LOCK (0x1UL << 4) /* Configuration lock */
#define _WDOG_CTRL_LOCK_SHIFT 4 /* Shift value for WDOG_LOCK */
#define _WDOG_CTRL_LOCK_MASK 0x10UL /* Bit mask for WDOG_LOCK */
#define _WDOG_CTRL_LOCK_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_LOCK_DEFAULT (_WDOG_CTRL_LOCK_DEFAULT << 4) /* Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM4BLOCK (0x1UL << 5) /* Energy Mode 4 Block */
#define _WDOG_CTRL_EM4BLOCK_SHIFT 5 /* Shift value for WDOG_EM4BLOCK */
#define _WDOG_CTRL_EM4BLOCK_MASK 0x20UL /* Bit mask for WDOG_EM4BLOCK */
#define _WDOG_CTRL_EM4BLOCK_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_EM4BLOCK_DEFAULT (_WDOG_CTRL_EM4BLOCK_DEFAULT << 5) /* Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_SWOSCBLOCK (0x1UL << 6) /* Software Oscillator Disable Block */
#define _WDOG_CTRL_SWOSCBLOCK_SHIFT 6 /* Shift value for WDOG_SWOSCBLOCK */
#define _WDOG_CTRL_SWOSCBLOCK_MASK 0x40UL /* Bit mask for WDOG_SWOSCBLOCK */
#define _WDOG_CTRL_SWOSCBLOCK_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_SWOSCBLOCK_DEFAULT (_WDOG_CTRL_SWOSCBLOCK_DEFAULT << 6) /* Shifted mode DEFAULT for WDOG_CTRL */
#define _WDOG_CTRL_PERSEL_SHIFT 8 /* Shift value for WDOG_PERSEL */
#define _WDOG_CTRL_PERSEL_MASK 0xF00UL /* Bit mask for WDOG_PERSEL */
#define _WDOG_CTRL_PERSEL_DEFAULT 0x0000000FUL /* Mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_PERSEL_DEFAULT (_WDOG_CTRL_PERSEL_DEFAULT << 8) /* Shifted mode DEFAULT for WDOG_CTRL */
#define _WDOG_CTRL_CLKSEL_SHIFT 12 /* Shift value for WDOG_CLKSEL */
#define _WDOG_CTRL_CLKSEL_MASK 0x3000UL /* Bit mask for WDOG_CLKSEL */
#define _WDOG_CTRL_CLKSEL_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CTRL */
#define _WDOG_CTRL_CLKSEL_ULFRCO 0x00000000UL /* Mode ULFRCO for WDOG_CTRL */
#define _WDOG_CTRL_CLKSEL_LFRCO 0x00000001UL /* Mode LFRCO for WDOG_CTRL */
#define _WDOG_CTRL_CLKSEL_LFXO 0x00000002UL /* Mode LFXO for WDOG_CTRL */
#define WDOG_CTRL_CLKSEL_DEFAULT (_WDOG_CTRL_CLKSEL_DEFAULT << 12) /* Shifted mode DEFAULT for WDOG_CTRL */
#define WDOG_CTRL_CLKSEL_ULFRCO (_WDOG_CTRL_CLKSEL_ULFRCO << 12) /* Shifted mode ULFRCO for WDOG_CTRL */
#define WDOG_CTRL_CLKSEL_LFRCO (_WDOG_CTRL_CLKSEL_LFRCO << 12) /* Shifted mode LFRCO for WDOG_CTRL */
#define WDOG_CTRL_CLKSEL_LFXO (_WDOG_CTRL_CLKSEL_LFXO << 12) /* Shifted mode LFXO for WDOG_CTRL */
/* Bit fields for WDOG CMD */
#define _WDOG_CMD_RESETVALUE 0x00000000UL /* Default value for WDOG_CMD */
#define _WDOG_CMD_MASK 0x00000001UL /* Mask for WDOG_CMD */
#define WDOG_CMD_CLEAR (0x1UL << 0) /* Watchdog Timer Clear */
#define _WDOG_CMD_CLEAR_SHIFT 0 /* Shift value for WDOG_CLEAR */
#define _WDOG_CMD_CLEAR_MASK 0x1UL /* Bit mask for WDOG_CLEAR */
#define _WDOG_CMD_CLEAR_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_CMD */
#define _WDOG_CMD_CLEAR_UNCHANGED 0x00000000UL /* Mode UNCHANGED for WDOG_CMD */
#define _WDOG_CMD_CLEAR_CLEARED 0x00000001UL /* Mode CLEARED for WDOG_CMD */
#define WDOG_CMD_CLEAR_DEFAULT (_WDOG_CMD_CLEAR_DEFAULT << 0) /* Shifted mode DEFAULT for WDOG_CMD */
#define WDOG_CMD_CLEAR_UNCHANGED (_WDOG_CMD_CLEAR_UNCHANGED << 0) /* Shifted mode UNCHANGED for WDOG_CMD */
#define WDOG_CMD_CLEAR_CLEARED (_WDOG_CMD_CLEAR_CLEARED << 0) /* Shifted mode CLEARED for WDOG_CMD */
/* Bit fields for WDOG SYNCBUSY */
#define _WDOG_SYNCBUSY_RESETVALUE 0x00000000UL /* Default value for WDOG_SYNCBUSY */
#define _WDOG_SYNCBUSY_MASK 0x00000003UL /* Mask for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_CTRL (0x1UL << 0) /* CTRL Register Busy */
#define _WDOG_SYNCBUSY_CTRL_SHIFT 0 /* Shift value for WDOG_CTRL */
#define _WDOG_SYNCBUSY_CTRL_MASK 0x1UL /* Bit mask for WDOG_CTRL */
#define _WDOG_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_CTRL_DEFAULT (_WDOG_SYNCBUSY_CTRL_DEFAULT << 0) /* Shifted mode DEFAULT for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_CMD (0x1UL << 1) /* CMD Register Busy */
#define _WDOG_SYNCBUSY_CMD_SHIFT 1 /* Shift value for WDOG_CMD */
#define _WDOG_SYNCBUSY_CMD_MASK 0x2UL /* Bit mask for WDOG_CMD */
#define _WDOG_SYNCBUSY_CMD_DEFAULT 0x00000000UL /* Mode DEFAULT for WDOG_SYNCBUSY */
#define WDOG_SYNCBUSY_CMD_DEFAULT (_WDOG_SYNCBUSY_CMD_DEFAULT << 1) /* Shifted mode DEFAULT for WDOG_SYNCBUSY */
#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_WDOG_H */
arch/arm/src/efm32/efm32_clockconfig.c
+1 -1
View File
@@ -875,7 +875,7 @@ static inline void efm32_itm_syslog(void)
*/
regval = getreg32(EFM32_GPIO_ROUTE);
regval &= _GPIO_ROUTE_SWLOCATION_MASK;
regval &= ~_GPIO_ROUTE_SWLOCATION_MASK;
regval |= GPIO_ROUTE_SWOPEN;
regval |= ((uint32_t)BOARD_SWOPORT_LOCATION << _GPIO_ROUTE_SWLOCATION_SHIFT);
putreg32(regval, EFM32_GPIO_ROUTE);
arch/arm/src/efm32/efm32_serial.c
+6
View File
@@ -240,7 +240,9 @@ static inline void efm32_serialout(struct efm32_usart_s *priv, int offset,
static inline void efm32_setuartint(struct efm32_usart_s *priv);
static void efm32_restoreuartint(struct efm32_usart_s *priv, uint32_t ien);
#ifdef HAVE_UART_CONSOLE
static void efm32_disableuartint(struct efm32_usart_s *priv, uint32_t *ien);
#endif
static int efm32_setup(struct uart_dev_s *dev);
static void efm32_shutdown(struct uart_dev_s *dev);
static int efm32_attach(struct uart_dev_s *dev);
@@ -574,6 +576,7 @@ static void efm32_restoreuartint(struct efm32_usart_s *priv, uint32_t ien)
* Name: efm32_disableuartint
****************************************************************************/
#ifdef HAVE_UART_CONSOLE
static void efm32_disableuartint(struct efm32_usart_s *priv, uint32_t *ien)
{
irqstate_t flags;
@@ -587,6 +590,7 @@ static void efm32_disableuartint(struct efm32_usart_s *priv, uint32_t *ien)
efm32_restoreuartint(priv, 0);
irqrestore(flags);
}
#endif
/****************************************************************************
* Name: efm32_setup
@@ -1125,6 +1129,7 @@ static bool efm32_txempty(struct uart_dev_s *dev)
*
****************************************************************************/
#ifdef USE_EARLYSERIALINIT
void up_earlyserialinit(void)
{
/* Disable interrupts from all UARTS. The console is enabled in
@@ -1152,6 +1157,7 @@ void up_earlyserialinit(void)
efm32_setup(&CONSOLE_DEV);
#endif
}
#endif
/****************************************************************************
* Name: up_serialinit
arch/arm/src/efm32/efm32_spi.c
+1
View File
@@ -60,6 +60,7 @@
#include "up_arch.h"
#include "chip.h"
#include "chip/efm32_usart.h"
#include "efm32_config.h"
#include "efm32_dma.h"
#include "efm32_lowputc.h"
arch/arm/src/sam34/sam_serial.c
+3 -4
View File
@@ -1118,7 +1118,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
/* Decode number of bits */
switch (priv->bits)
switch (termiosp->c_cflag & CSIZE)
{
case CS5:
nbits = 5;
@@ -1147,7 +1147,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
/* Decode parity */
if (termiosp->c_cflag & PARENB)
if ((termiosp->c_cflag & PARENB) != 0)
{
parity = (termiosp->c_cflag & PARODD) ? 1 : 2;
}
@@ -1178,12 +1178,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
priv->flowc = flowc;
#endif
/* effect the changes immediately - note that we do not
* implement TCSADRAIN / TCSAFLUSH
*/
up_setup(dev);
ret = up_setup(dev);
}
}
break;
fs/Kconfig
+6
View File
@@ -73,6 +73,12 @@ config SYSLOG
console (like printf()). This setting is required to enable
customization of the basic system loggin capability.
config SYSLOG_TIMESTAMP
bool "Prepend timestamp to syslog message"
default n
---help---
Prepend timestamp to syslog message.
if SYSLOG
config SYSLOG_CHAR
libc/syslog/lib_syslog.c
+56 -11
View File
@@ -42,6 +42,7 @@
#include <stdio.h>
#include <syslog.h>
#include <nuttx/clock.h>
#include <nuttx/streams.h>
#include "syslog/syslog.h"
@@ -94,41 +95,85 @@
static inline int vsyslog_internal(FAR const char *fmt, va_list ap)
{
#if defined(CONFIG_SYSLOG)
struct lib_outstream_s stream;
#elif CONFIG_NFILE_DESCRIPTORS > 0
struct lib_rawoutstream_s stream;
#elif defined(CONFIG_ARCH_LOWPUTC)
struct lib_outstream_s stream;
#endif
#if defined(CONFIG_SYSLOG_TIMESTAMP)
struct timespec ts;
int ret;
/* Get the current time */
ret = clock_systimespec(&ts);
#endif
#if defined(CONFIG_SYSLOG)
/* Wrap the low-level output in a stream object and let lib_vsprintf
* do the work.
*/
lib_syslogstream((FAR struct lib_outstream_s *)&stream);
#if defined(CONFIG_SYSLOG_TIMESTAMP)
/* Pre-pend the message with the current time */
if (ret == OK)
{
(void)lib_sprintf((FAR struct lib_outstream_s *)&stream,
"[%6d.%06d]",
ts.tv_sec, ts.tv_nsec/1000);
}
#endif
return lib_vsprintf((FAR struct lib_outstream_s *)&stream, fmt, ap);
#elif CONFIG_NFILE_DESCRIPTORS > 0
struct lib_rawoutstream_s rawoutstream;
/* Wrap the stdout in a stream object and let lib_vsprintf
* do the work.
*/
lib_rawoutstream(&rawoutstream, 1);
return lib_vsprintf(&rawoutstream.public, fmt, ap);
lib_rawoutstream(&stream, 1);
#if defined(CONFIG_SYSLOG_TIMESTAMP)
/* Pre-pend the message with the current time */
if (ret == OK)
{
(void)lib_sprintf((FAR struct lib_outstream_s *)&stream,
"[%6d.%06d]",
ts.tv_sec, ts.tv_nsec/1000);
}
#endif
return lib_vsprintf(&stream.public, fmt, ap);
#elif defined(CONFIG_ARCH_LOWPUTC)
struct lib_outstream_s stream;
/* Wrap the low-level output in a stream object and let lib_vsprintf
* do the work.
*/
lib_lowoutstream((FAR struct lib_outstream_s *)&stream);
#if defined(CONFIG_SYSLOG_TIMESTAMP)
/* Pre-pend the message with the current time */
if (ret == OK)
{
(void)lib_sprintf((FAR struct lib_outstream_s *)&stream,
"[%6d.%06d]",
ts.tv_sec, ts.tv_nsec/1000);
}
#endif
return lib_vsprintf((FAR struct lib_outstream_s *)&stream, fmt, ap);
#else
#else /* CONFIG_SYSLOG */
return 0;
#endif
#endif /* CONFIG_SYSLOG */
}
/****************************************************************************
libc/termios/lib_tcsetattr.c
+1
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@@ -118,5 +118,6 @@ int tcsetattr(int fd, int options, FAR const struct termios *termiosp)
{
return ioctl(fd, TCSETS, (unsigned long)termiosp);
}
return -ENOSYS;
}