mirror of
https://github.com/apache/nuttx.git
synced 2026-06-06 16:50:55 +08:00
SAMA5 page table is cached; need to flush the cache each time that the page table is updated
This commit is contained in:
Gregory Nutt
+345
-318
File diff suppressed because it is too large
Load Diff
@@ -179,7 +179,7 @@
|
||||
|
||||
.macro cp15_invalidate_icache_inner_sharable, tmp
|
||||
mov \tmp, #0
|
||||
mrc p15, 0, \tmp, c7, c1, 0
|
||||
mrc p15, 0, \tmp, c7, c1, 0 /* ICIALLUIS */
|
||||
.endm
|
||||
|
||||
/************************************************************************************
|
||||
@@ -198,7 +198,7 @@
|
||||
|
||||
.macro cp15_invalidate_btb_inner_sharable, tmp
|
||||
mov \tmp, #0
|
||||
mrc p15, 0, \tmp, c7, c1, 6
|
||||
mrc p15, 0, \tmp, c7, c1, 6 /* BPIALLIS */
|
||||
.endm
|
||||
|
||||
/************************************************************************************
|
||||
@@ -217,7 +217,7 @@
|
||||
|
||||
.macro cp15_invalidate_icache, tmp
|
||||
mov \tmp, #0
|
||||
mrc p15, 0, \tmp, c7, c5, 0
|
||||
mrc p15, 0, \tmp, c7, c5, 0 /* ICIALLU */
|
||||
.endm
|
||||
|
||||
/************************************************************************************
|
||||
@@ -235,7 +235,7 @@
|
||||
************************************************************************************/
|
||||
|
||||
.macro cp15_invalidate_icache_bymva, va
|
||||
mrc p15, 0, \va, c7, c5, 1
|
||||
mrc p15, 0, \va, c7, c5, 1 /* ICIMVAU */
|
||||
.endm
|
||||
|
||||
/************************************************************************************
|
||||
@@ -254,7 +254,7 @@
|
||||
|
||||
.macro cp15_flush_btb, tmp
|
||||
mov \tmp, #0
|
||||
mrc p15, 0, \tmp, c7, c5, 6
|
||||
mrc p15, 0, \tmp, c7, c5, 6 /* BPIALL */
|
||||
.endm
|
||||
|
||||
/************************************************************************************
|
||||
@@ -273,7 +273,7 @@
|
||||
|
||||
.macro cp15_flush_btb_bymva, tmp
|
||||
mov \tmp, #0
|
||||
mrc p15, 0, \tmp, c7, c5, 7
|
||||
mrc p15, 0, \tmp, c7, c5, 7 /* BPIMVA */
|
||||
.endm
|
||||
|
||||
/************************************************************************************
|
||||
@@ -291,7 +291,7 @@
|
||||
************************************************************************************/
|
||||
|
||||
.macro cp15_invalidate_dcacheline_bymva, va
|
||||
mrc p15, 0, \va, c7, c6, 1
|
||||
mrc p15, 0, \va, c7, c6, 1 /* DCIMVAC */
|
||||
.endm
|
||||
|
||||
/************************************************************************************
|
||||
@@ -309,7 +309,7 @@
|
||||
************************************************************************************/
|
||||
|
||||
.macro cp15_invalidate_dcacheline_bysetway, setway
|
||||
mrc p15, 0, \setway, c7, c6, 2
|
||||
mrc p15, 0, \setway, c7, c6, 2 /* DCISW */
|
||||
.endm
|
||||
|
||||
/************************************************************************************
|
||||
@@ -327,7 +327,7 @@
|
||||
************************************************************************************/
|
||||
|
||||
.macro cp15_clean_dcache_bymva, va
|
||||
mrc p15, 0, \va, c7, c10, 1
|
||||
mrc p15, 0, \va, c7, c10, 1 /* DCCMVAC */
|
||||
.endm
|
||||
|
||||
/************************************************************************************
|
||||
@@ -345,11 +345,11 @@
|
||||
************************************************************************************/
|
||||
|
||||
.macro cp15_clean_dcache_bysetway, setway
|
||||
mrc p15, 0, \setway, c7, c10, 2
|
||||
mrc p15, 0, \setway, c7, c10, 2 /* DCCSW */
|
||||
.endm
|
||||
|
||||
/************************************************************************************
|
||||
* Name: cp15_clean_dcache_bymva
|
||||
* Name: cp15_clean_ucache_bymva
|
||||
*
|
||||
* Description:
|
||||
* Clean unified cache line by MVA
|
||||
@@ -362,8 +362,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
.macro cp15_clean_dcache_bymva, setway
|
||||
mrc p15, 0, \setway, c7, c11, 1
|
||||
.macro cp15_clean_ucache_bymva, setway
|
||||
mrc p15, 0, \setway, c7, c11, 1 /* DCCMVAU */
|
||||
.endm
|
||||
|
||||
/************************************************************************************
|
||||
@@ -381,7 +381,7 @@
|
||||
************************************************************************************/
|
||||
|
||||
.macro cp15_cleaninvalidate_dcacheline_bymva, va
|
||||
mrc p15, 0, \va, c7, c14, 1
|
||||
mrc p15, 0, \va, c7, c14, 1 /* DCCIMVAC */
|
||||
.endm
|
||||
|
||||
/************************************************************************************
|
||||
@@ -399,7 +399,7 @@
|
||||
************************************************************************************/
|
||||
|
||||
.macro cp15_cleaninvalidate_dcacheline, setway
|
||||
mrc p15, 0, \setway, c7, c14, 2
|
||||
mrc p15, 0, \setway, c7, c14, 2 /* DCCISW */
|
||||
.endm
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
@@ -429,7 +429,7 @@ static inline void cp15_invalidate_icache_inner_sharable(void)
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmov r0, #0\n"
|
||||
"\tmcr p15, 0, r0, c7, c1, 0\n"
|
||||
"\tmcr p15, 0, r0, c7, c1, 0\n" /* ICIALLUIS */
|
||||
:
|
||||
:
|
||||
: "r0", "memory"
|
||||
@@ -455,7 +455,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void)
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmov r0, #0\n"
|
||||
"\tmcr p15, 0, r0, c7, c1, 6\n"
|
||||
"\tmcr p15, 0, r0, c7, c1, 6\n" /* BPIALLIS */
|
||||
:
|
||||
:
|
||||
: "r0", "memory"
|
||||
@@ -481,7 +481,7 @@ static inline void cp15_invalidate_icache(void)
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmov r0, #0\n"
|
||||
"\tmcr p15, 0, r0, c7, c5, 0\n"
|
||||
"\tmcr p15, 0, r0, c7, c5, 0\n" /* ICIALLU */
|
||||
:
|
||||
:
|
||||
: "r0", "memory"
|
||||
@@ -506,7 +506,7 @@ static inline void cp15_invalidate_icache_bymva(unsigned int va)
|
||||
{
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmcr p15, 0, %0, c7, c5, 1\n"
|
||||
"\tmcr p15, 0, %0, c7, c5, 1\n" /* ICIMVAU */
|
||||
:
|
||||
: "r" (va)
|
||||
: "memory"
|
||||
@@ -532,7 +532,7 @@ static inline void cp15_flush_btb(void)
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmov r0, #0\n"
|
||||
"\tmcr p15, 0, r0, c7, c5, 6\n"
|
||||
"\tmcr p15, 0, r0, c7, c5, 6\n" /* BPIALL */
|
||||
:
|
||||
:
|
||||
: "r0", "memory"
|
||||
@@ -558,7 +558,7 @@ static inline void cp15_flush_btb_bymva(void)
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmov r0, #0\n"
|
||||
"\tmcr p15, 0, r0, c7, c5, 7\n"
|
||||
"\tmcr p15, 0, r0, c7, c5, 7\n" /* BPIMVA */
|
||||
:
|
||||
:
|
||||
: "r0", "memory"
|
||||
@@ -585,7 +585,7 @@ static inline void cp15_invalidate_dcacheline_bymva(unsigned int va)
|
||||
{
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmcr p15, 0, %0, c7, c6, 1\n"
|
||||
"\tmcr p15, 0, %0, c7, c6, 1\n" /* DCIMVAC */
|
||||
:
|
||||
: "r" (va)
|
||||
: "memory"
|
||||
@@ -612,7 +612,7 @@ static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway)
|
||||
{
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmcr p15, 0, %0, c7, c6, 2\n"
|
||||
"\tmcr p15, 0, %0, c7, c6, 2\n" /* DCISW */
|
||||
:
|
||||
: "r" (setway)
|
||||
: "memory"
|
||||
@@ -639,7 +639,7 @@ static inline void cp15_clean_dcache_bymva(unsigned int va)
|
||||
{
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmcr p15, 0, %0, c7, c10, 1\n"
|
||||
"\tmcr p15, 0, %0, c7, c10, 1\n" /* DCCMVAC */
|
||||
:
|
||||
: "r" (va)
|
||||
: "memory"
|
||||
@@ -664,7 +664,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway)
|
||||
{
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmcr p15, 0, %0, c7, c10, 2\n"
|
||||
"\tmcr p15, 0, %0, c7, c10, 2\n" /* DCCSW */
|
||||
:
|
||||
: "r" (setway)
|
||||
: "memory"
|
||||
@@ -672,7 +672,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway)
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: cp15_clean_dcache_bymva
|
||||
* Name: cp15_clean_ucache_bymva
|
||||
*
|
||||
* Description:
|
||||
* Clean unified cache line by MVA
|
||||
@@ -685,11 +685,11 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
static inline void cp15_clean_dcache_bymva(unsigned int setway)
|
||||
static inline void cp15_clean_ucache_bymva(unsigned int setway)
|
||||
{
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmcr p15, 0, %0, c7, c11, 1\n"
|
||||
"\tmcr p15, 0, %0, c7, c11, 1\n" /* DCCMVAU */
|
||||
:
|
||||
: "r" (setway)
|
||||
: "memory"
|
||||
@@ -714,7 +714,7 @@ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va)
|
||||
{
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmcr p15, 0, r0, c7, c14, 1\n"
|
||||
"\tmcr p15, 0, r0, c7, c14, 1\n" /* DCCIMVAC */
|
||||
:
|
||||
: "r" (va)
|
||||
: "memory"
|
||||
@@ -739,7 +739,7 @@ static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway)
|
||||
{
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmcr p15, 0, %0, c7, c14, 2\n"
|
||||
"\tmcr p15, 0, %0, c7, c14, 2\n" /* DCCISW */
|
||||
:
|
||||
: "r" (setway)
|
||||
: "memory"
|
||||
@@ -768,9 +768,10 @@ extern "C" {
|
||||
* Name: cp15_coherent_dcache_for_dma
|
||||
*
|
||||
* Description:
|
||||
* Ensure that the I and D caches are coherent within specified region.
|
||||
* This is typically used when code has been written to a memory region,
|
||||
* and will be executed.
|
||||
* Ensure that the I and D caches are coherent within specified region
|
||||
* by cleaning the D cache (i.e., flushing the D cache contents to memory
|
||||
* and invalidating the I cache. This is typically used when code has been
|
||||
* written to a memory region, and will be executed.
|
||||
*
|
||||
* Input Parameters:
|
||||
* start - virtual start address of region
|
||||
@@ -806,7 +807,8 @@ void cp15_invalidate_dcache_for_dma(uintptr_t start, uintptr_t end);
|
||||
* Name: cp15_clean_dcache_for_dma
|
||||
*
|
||||
* Description:
|
||||
* Clean the data cache within the specified region
|
||||
* Clean the data cache within the specified region by flushing the
|
||||
* contents of the data cache to memory.
|
||||
*
|
||||
* Input Parameters:
|
||||
* start - virtual start address of region
|
||||
@@ -823,7 +825,8 @@ void cp15_clean_dcache_for_dma(uintptr_t start, uintptr_t end);
|
||||
* Name: cp15_flush_dcache_for_dma
|
||||
*
|
||||
* Description:
|
||||
* Flush the data cache within the specified region
|
||||
* Flush the data cache within the specified region by cleaning and
|
||||
* invalidating the the D cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* start - virtual start address of region
|
||||
|
||||
@@ -196,11 +196,4 @@
|
||||
#define CP15_CBADDR(r) _CP15(4, r, c15, c0, 0) /* Configuration Base Address Register */
|
||||
#define CP15_TLBHITMAP(r) _CP15(5, r, c15, c0, 0) /* TLB access and attributes */
|
||||
|
||||
/* System control register descriptions.
|
||||
*
|
||||
* To be provided
|
||||
*
|
||||
* Reference: Cortex-A5™ MPCore, Technical Reference Manual, Paragraph 4.3.
|
||||
*/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_ARMV7_A_CP15_H */
|
||||
|
||||
@@ -51,6 +51,7 @@
|
||||
#include "chip.h"
|
||||
#include "arm.h"
|
||||
#include "mmu.h"
|
||||
#include "cache.h"
|
||||
#include "fpu.h"
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
@@ -500,6 +501,14 @@ void up_boot(void)
|
||||
|
||||
sam_vectormapping();
|
||||
|
||||
|
||||
/* The SRAM address hold the the page table is probably buffered. Make sure
|
||||
* that the modified contents of the page table are flushed into physical
|
||||
* memory.
|
||||
*/
|
||||
|
||||
cp15_clean_dcache_for_dma(VECTOR_L2_VBASE, VECTOR_L2_VBASE + PGTABLE_SIZE);
|
||||
|
||||
#endif /* CONFIG_ARCH_ROMPGTABLE */
|
||||
|
||||
/* Setup up vector block. _vector_start and _vector_end are exported from
|
||||
|
||||
Reference in New Issue
Block a user