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Update/fix last commit: On some STM32's, the CSR regiser is 18 vs. 16 bits wide. Need to use 32-bit register accesses.

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This commit is contained in:
Gregory Nutt
2017-09-08 14:21:24 -06:00
parent 3596c75d78
commit 3ca3674cca
2 changed files with 4 additions and 10 deletions
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arch/arm/src/stm32/chip/stm32_pwr.h
+2 -2
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@@ -166,8 +166,8 @@
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
# define PWR_CSR_ODRDY (1 << 16) /* Over Drive generator ready */ # define PWR_CSR_ODRDY (1 << 16) /* Git 16: Over Drive generator ready */
# define PWR_CSR_ODSWRDY (1 << 17) /* Over Drive Switch ready */ # define PWR_CSR_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */
#endif #endif
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_PWR_H */ #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_PWR_H */
arch/arm/src/stm32/stm32_pwr.c
+2 -8
View File
@@ -105,12 +105,6 @@ static inline void stm32_pwr_modifyreg32(uint8_t offset, uint32_t clearbits,
modifyreg32(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits); modifyreg32(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits);
} }
static inline void stm32_pwr_modifyreg16(uint8_t offset, uint32_t clearbits,
uint32_t setbits)
{
modifyreg16(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits);
}
/************************************************************************************ /************************************************************************************
* Public Functions * Public Functions
************************************************************************************/ ************************************************************************************/
@@ -314,13 +308,13 @@ int stm32_pwr_enablewkup(enum stm32_pwr_wupin_e wupin, bool wupon)
{ {
/* Enable the wakeup pin by setting the bit in the CSR. */ /* Enable the wakeup pin by setting the bit in the CSR. */
stm32_pwr_modifyreg16(STM32_PWR_CSR_OFFSET, 0, pinmask); stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, 0, pinmask);
} }
else else
{ {
/* Disable the wakeup pin by clearing the bit in the CSR. */ /* Disable the wakeup pin by clearing the bit in the CSR. */
stm32_pwr_modifyreg16(STM32_PWR_CSR_OFFSET, pinmask, 0); stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, pinmask, 0);
} }
return OK; return OK;