diff --git a/arch/arm/src/stm32/chip/stm32_pwr.h b/arch/arm/src/stm32/chip/stm32_pwr.h index 3cbf8524640..e67f81112ba 100644 --- a/arch/arm/src/stm32/chip/stm32_pwr.h +++ b/arch/arm/src/stm32/chip/stm32_pwr.h @@ -166,8 +166,8 @@ #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# define PWR_CSR_ODRDY (1 << 16) /* Over Drive generator ready */ -# define PWR_CSR_ODSWRDY (1 << 17) /* Over Drive Switch ready */ +# define PWR_CSR_ODRDY (1 << 16) /* Git 16: Over Drive generator ready */ +# define PWR_CSR_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */ #endif #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_PWR_H */ diff --git a/arch/arm/src/stm32/stm32_pwr.c b/arch/arm/src/stm32/stm32_pwr.c index f99dc0636aa..ca08ccf7c87 100644 --- a/arch/arm/src/stm32/stm32_pwr.c +++ b/arch/arm/src/stm32/stm32_pwr.c @@ -105,12 +105,6 @@ static inline void stm32_pwr_modifyreg32(uint8_t offset, uint32_t clearbits, modifyreg32(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits); } -static inline void stm32_pwr_modifyreg16(uint8_t offset, uint32_t clearbits, - uint32_t setbits) -{ - modifyreg16(STM32_PWR_BASE + (uint32_t)offset, clearbits, setbits); -} - /************************************************************************************ * Public Functions ************************************************************************************/ @@ -314,13 +308,13 @@ int stm32_pwr_enablewkup(enum stm32_pwr_wupin_e wupin, bool wupon) { /* Enable the wakeup pin by setting the bit in the CSR. */ - stm32_pwr_modifyreg16(STM32_PWR_CSR_OFFSET, 0, pinmask); + stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, 0, pinmask); } else { /* Disable the wakeup pin by clearing the bit in the CSR. */ - stm32_pwr_modifyreg16(STM32_PWR_CSR_OFFSET, pinmask, 0); + stm32_pwr_modifyreg32(STM32_PWR_CSR_OFFSET, pinmask, 0); } return OK;