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STM32 F4 RTC driver is fully coded (but not tested)
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4176 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -82,6 +82,26 @@
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/* Register Bitfield Definitions ****************************************************/
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/* EXTI lines > 15 are associated with internal devices: */
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#if defined(CONFIG_STM32_STM32F10XX)
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# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */
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# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */
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# define EXTI_USB_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB Wakeup event */
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# ifdef CONFIG_STM32_CONNECTIVITYLINE
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# define EXTI_ETH_WAKEUP (1 << 19) /* EXTI line 19 is connected to the Ethernet Wakeup event */
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# endif
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#elif defined(CONFIG_STM32_STM32F40XX)
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# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */
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# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */
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# define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */
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# define EXTI_ETH_WAKEUP (1 << 19) /* EXTI line 19 is connected to the Ethernet Wakeup event */
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# define EXTI_OTGHS_WAKEUP (1 << 20) /* EXTI line 20 is connected to the USB OTG HS Wakeup event */
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# define EXTI_RTC_TAMPER (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */
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# define EXTI_RTC_TIMESTAMP (1 << 22) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */
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# define EXTI_RTC_WAKEUP (1 << 23) /* EXTI line 22 is connected to the RTC Wakeup event
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#endif
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/* Interrupt mask register */
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#define EXTI_IMR_BIT(n) STM32_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */
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@@ -133,7 +133,7 @@
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#define RTC_TR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format */
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#define RTC_TR_SU_MASK (15 << RTC_TR_SU_SHIFT)
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#define RTC_TR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format */
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#define RTC_TR_ST_MASK (7 << RTC_TR_ST_SHIFT)*
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#define RTC_TR_ST_MASK (7 << RTC_TR_ST_SHIFT)
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#define RTC_TR_MNU_SHIFT (8) /* Bit 8-11: Minute units in BCD format */
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#define RTC_TR_MNU_MASK (15 << RTC_TR_MNU_SHIFT)
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#define RTC_TR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format */
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@@ -143,10 +143,11 @@
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#define RTC_TR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format */
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#define RTC_TR_HT_MASK (3 << RTC_TR_HT_SHIFT)
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#define RTC_TR_PM (1 << 22) /* Bit 22: AM/PM notation */
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#define RTC_TR_RESERVED_BITS (0xff808080)
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/* RTC date register */
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#define RTC_DR_DU_SHIFT (0) /* Bits 0-3]: Date units in BCD format */
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#define RTC_DR_DU_SHIFT (0) /* Bits 0-3: Date units in BCD format */
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#define RTC_DR_DU_MASK (15 << RTC_DR_DU_SHIFT)
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#define RTC_DR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */
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#define RTC_DR_DT_MASK (3 << RTC_DR_DT_SHIFT)
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@@ -166,6 +167,7 @@
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#define RTC_DR_YU_MASK (15 << RTC_DR_YU_SHIFT)
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#define RTC_DR_YT_SHIFT (20) /* Bits 20-23: Year tens in BCD format */
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#define RTC_DR_YT_MASK (15 << RTC_DR_YT_SHIFT)
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#define RTC_DR_RESERVED_BITS (0xff0000c0)
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/* RTC control register */
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@@ -220,13 +222,14 @@
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#define RTC_ISR_TSOVF (1 << 12) /* Bit 12: Timestamp overflow flag */
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#define RTC_ISR_TAMP1F (1 << 13) /* Bit 13: Tamper detection flag */
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#define RTC_ISR_TAMP2F (1 << 14) /* Bit 14: TAMPER2 detection flag */
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#define RTC_ISR_RECALPF (1 << 15) /* Bit 16: Recalibration pending Flag */
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#define RTC_ISR_RECALPF (1 << 16) /* Bit 16: Recalibration pending Flag */
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#define RTC_ISR_ALLFLAGS (0x00017fff)
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/* RTC prescaler register */
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#define RTC_PRER_PREDIV_S_SHIFT (0) /* Bits 0-14: Synchronous prescaler factor */
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#define RTC_PRER_PREDIV_S_MASK (0x7fff << RTC_PRER_PREDIV_S_SHIFT)
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#define RTC_PRER_PREDIV_A_SHIFT (22) /* Bits 16-22: Asynchronous prescaler factor */
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#define RTC_PRER_PREDIV_A_SHIFT (16) /* Bits 16-22: Asynchronous prescaler factor */
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#define RTC_PRER_PREDIV_A_MASK (0x7f << RTC_PRER_PREDIV_A_SHIFT)
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/* RTC wakeup timer register */
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@@ -2,7 +2,7 @@
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* arch/arm/src/stm32/stm32_lse.c
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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* Author: Gregory Nutt <gnutt@nuttx.orgr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -63,31 +63,43 @@
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/****************************************************************************
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* Name: stm32_rcc_enablelse
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*
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* Description:
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* Enable the External Low-Speed (LSE) Oscillator and, if the RTC is
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* configured, setup the LSE as the RTC clock source, and enable the RTC.
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*
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* Todo:
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* Check for LSE good timeout and return with -1,
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* possible ISR optimization? or at least ISR should be cough in case of\
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* failure
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*
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****************************************************************************/
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void stm32_rcc_enablelse(void)
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{
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/* Enable LSE */
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/* Enable the External Low-Speed (LSE) Oscillator by setting the LSEON bit
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* the RCC BDCR register.
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*/
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modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
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/* We could wait for ISR here ... */
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/* Wait for the LSE clock to be ready */
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while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0)
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{
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up_waste();
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}
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/* Select LSE as RTC Clock Source */
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/* The primariy purpose of the LSE clock is to drive the RTC. The RTC could
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* also be driven by the LSI (but that would be very inaccurate) or by the
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* HSE (but that would prohibit low-power operation)
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*
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* Select LSE as RTC Clock Source by setting the RTCSEL field of the RCC BDCR
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* register.
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*/
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#ifdef CONFIG_RTC
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modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
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/* Enable Clock */
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/* Enable the RTC Clock by setting the RTCEN bit in the RCC BDCR register */
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modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
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#endif
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}
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@@ -33,13 +33,9 @@
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*
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************************************************************************************/
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/** \file
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* \author Uros Platise
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* \brief STM32 Power
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*
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* \addtogroup STM32_PWR
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* \{
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*/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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@@ -50,7 +46,6 @@
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#include "up_arch.h"
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#include "stm32_pwr.h"
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#if defined(CONFIG_STM32_PWR)
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/************************************************************************************
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@@ -59,32 +54,41 @@
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static inline uint16_t stm32_pwr_getreg(uint8_t offset)
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{
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return getreg32(STM32_PWR_BASE + offset);
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return getreg32(STM32_PWR_BASE + offset);
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}
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static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value)
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{
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putreg32(value, STM32_PWR_BASE + offset);
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putreg32(value, STM32_PWR_BASE + offset);
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}
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static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits)
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{
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modifyreg32(STM32_PWR_BASE + offset, clearbits, setbits);
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modifyreg32(STM32_PWR_BASE + offset, clearbits, setbits);
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}
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Public Function - Initialization
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* Name: stm32_pwr_enablebkp
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*
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* Description:
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* Enables access to the backup domain (RTC registers, RTC backup data registers
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* and backup SRAM).
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*
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* Input Parameters:
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* None
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*
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* Returned Values:
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* None
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*
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************************************************************************************/
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void stm32_pwr_enablebkp(void)
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{
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stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, 0, PWR_CR_DBP);
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stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, 0, PWR_CR_DBP);
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}
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#endif // defined(CONFIG_STM32_PWR)
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/** \} */
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@@ -63,15 +63,27 @@ extern "C" {
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* Public Functions
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************************************************************************************/
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/** Disables Write Protection to the Backup Area
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**/
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/************************************************************************************
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* Name: stm32_pwr_enablebkp
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*
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* Description:
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* Enables access to the backup domain (RTC registers, RTC backup data registers
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* and backup SRAM).
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*
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* Input Parameters:
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* None
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*
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* Returned Values:
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* None
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*
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************************************************************************************/
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EXTERN void stm32_pwr_enablebkp(void);
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/** \} */
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_STM32_STM32_PWR_H */
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@@ -2,7 +2,7 @@
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* arch/arm/src/stm32/stm32_rcc.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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* Author: Gregory Nutt <gnutt@nuttx.orgr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -170,7 +170,8 @@ EXTERN void stm32_clockconfig(void);
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* Name: stm32_rcc_enablelse
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*
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* Description:
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* Enable LSE Clock
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* Enable the External Low-Speed (LSE) Oscillator and, if the RTC is
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* configured, setup the LSE as the RTC clock source, and enable the RTC.
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*
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* Input Parameters:
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* None
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@@ -354,7 +354,8 @@ static int stm32_rtc_interrupt(int irq, void *context)
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int up_rtcinitialize(void)
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{
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/* Set access to the peripheral, enable the backup domain (BKP) and the lower power
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* extern 32,768Hz (Low-Speed External, LSE) oscillator.
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* extern 32,768Hz (Low-Speed External, LSE) oscillator. Configure the LSE to
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* drive the RTC.
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*/
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stm32_pwr_enablebkp();
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@@ -426,7 +426,7 @@ static inline void rcc_enableapb1(void)
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#endif
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/* Power interface clock enable. The PWR block is always enabled so that
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* we can set the internal voltage regulator for maximum performanc.
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* we can set the internal voltage regulator for maximum performance.
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*/
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regval |= RCC_APB1ENR_PWREN;
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