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SAM4E: Update SAM3/4 TC and DMAC register definition header files

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This commit is contained in:
Gregory Nutt
2014-02-25 10:56:23 -06:00
parent 4d600b7a73
commit 3b07bc6716
19 changed files with 655 additions and 406 deletions
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Documentation/NuttX.html
+3 -3
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@@ -1980,10 +1980,10 @@ nsh>
</p>
<ul>
<p>
This is a work-in-progress.
As of this writing (2014-2-18), there is a functional NuttShell (NSH) configuration.
An SPI driver to support the the added on OLED1 and I/O1 modules is in-work.
<b>STATUS</b>.
The initial SAMD20 Xplained Pro release (NuttX 6.34) included a functional NuttShell (NSH) configuration.
An SPI driver was also included to support the OLED1 and I/O1 modules.
That SPI driver, however, was not completed verified due to higher priority tasks that came up (I hope to get back to this later).
Refer to the SAMD20 Explained Pro board <a href="http://sourceforge.net/p/nuttx/git/ci/master/tree/nuttx/configs/samd20-xplained/README.txt">README</a> file for further information.
</p>
</ul>
arch/arm/src/sam34/Kconfig
+1 -1
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@@ -510,7 +510,7 @@ config SAM34_PDCA
depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
select ARCH_DMA
config SAM34_DMA
config SAM34_DMAC
bool "DMA controller"
default n
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
arch/arm/src/sam34/Make.defs
+2 -2
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@@ -92,8 +92,8 @@ ifeq ($(CONFIG_NUTTX_KERNEL),y)
CHIP_CSRCS += sam_userspace.c sam_mpuinit.c
endif
ifeq ($(CONFIG_SAM34_DMA),y)
CHIP_CSRCS += sam3u_dmac.c
ifeq ($(CONFIG_SAM34_DMAC),y)
CHIP_CSRCS += sam_dmac.c
endif
ifeq ($(CONFIG_SAM34_PDCA),y)
arch/arm/src/sam34/chip/sam4e_memorymap.h
+10 -4
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@@ -93,10 +93,16 @@
# define SAM_TC0_BASE 0x40090000 /* 0x40090000-0x4009003f: Timer Counter 0 */
# define SAM_TC1_BASE 0x40090040 /* 0x40090040-0x4009007f: Timer Counter 1 */
# define SAM_TC2_BASE 0x40090080 /* 0x40090080-0x400900bf: Timer Counter 2 */
#define SAM_TC345_BASE 0x40098000 /* 0x40098000-0x40097fff: Timer Counters 3-5 */
# define SAM_TC3_BASE 0x40098000 /* 0x40098000-0x4009003f: Timer Counter 3 */
# define SAM_TC4_BASE 0x40098040 /* 0x40098040-0x4009007f: Timer Counter 4 */
# define SAM_TC5_BASE 0x40098080 /* 0x40098080-0x400900bf: Timer Counter 5 */
/* 0x400900c0-0x40093fff Reserved */
#define SAM_TC345_BASE 0x40094000 /* 0x40094000-0x40094fff: Timer Counters 3-5 */
# define SAM_TC3_BASE 0x40094000 /* 0x40094000-0x4009403f: Timer Counter 3 */
# define SAM_TC4_BASE 0x40094040 /* 0x40094040-0x4009407f: Timer Counter 4 */
# define SAM_TC5_BASE 0x40094080 /* 0x40094080-0x400940bf: Timer Counter 5 */
/* 0x400940c0-0x40097fff Reserved */
#define SAM_TC678_BASE 0x40098000 /* 0x40098000-0x40097fff: Timer Counters 6-8 */
# define SAM_TC6_BASE 0x40098000 /* 0x40098000-0x4009003f: Timer Counter 6 */
# define SAM_TC7_BASE 0x40098040 /* 0x40098040-0x4009007f: Timer Counter 7 */
# define SAM_TC8_BASE 0x40098080 /* 0x40098080-0x400900bf: Timer Counter 8 */
/* 0x4009c000-0x4009ffff: Reserved */
#define SAM_USART_BASE 0x400a0000 /* 0x400a0000-0x400abfff: USART */
# define SAM_USART0_BASE 0x400a0000 /* 0x400a0000-0x400a3fff: USART0 */
arch/arm/src/sam34/chip/sam4s_memorymap.h
+2 -1
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@@ -73,11 +73,12 @@
#define SAM_SSC_BASE 0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */
#define SAM_SPI0_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */
/* 0x4000c000-0x4000ffff: Reserved */
#define SAM_TC_BASE 0x40010000 /* 0x40010000-0x40017fff: Timer Counters */
#define SAM_TC012_BASE 0x40010000 /* 0x40010000-0x400100bf: Timer Counters 0-2 */
# define SAM_TC0_BASE 0x40080000 /* 0x40010000-0x4001003f: Timer Counter 0 */
# define SAM_TC1_BASE 0x40080040 /* 0x40010040-0x4001007f: Timer Counter 1 */
# define SAM_TC2_BASE 0x40080080 /* 0x40010080-0x400100bf: Timer Counter 2 */
/* 0x400100c0-0x40013fff Reserved */
#define SAM_TC345_BASE 0x40080000 /* 0x40014000-0x400140bf: Timer Counters 3-5 */
# define SAM_TC3_BASE 0x40080000 /* 0x40014000-0x4001403f: Timer Counter 3 */
# define SAM_TC4_BASE 0x40080040 /* 0x40014040-0x4001407f: Timer Counter 4 */
# define SAM_TC5_BASE 0x40080080 /* 0x40014080-0x400140bf: Timer Counter 5 */
arch/arm/src/sam34/chip/sam3u_dmac.h → arch/arm/src/sam34/chip/sam_dmac.h
+135 -69
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@@ -1,7 +1,8 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam3u_dmac.h
* arch/arm/src/sam34/chip/sam_dmac.h
* DMA Controller (DMAC) definitions for the SAM3U, SAM3X, SAM3A, and RCH_CHIP_SAM4E
*
* Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -33,8 +34,8 @@
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_DMAC_H
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_DMAC_H
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_DMAC_H
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_DMAC_H
/****************************************************************************************
* Included Files
@@ -53,36 +54,42 @@
/* Global Registers */
#define SAM_DMAC_GCFG_OFFSET 0x00 /* DMAC Global Configuration Register */
#define SAM_DMAC_EN_OFFSET 0x04 /* DMAC Enable Register */
#define SAM_DMAC_SREQ_OFFSET 0x08 /* DMAC Software Single Request Register */
#define SAM_DMAC_CREQ_OFFSET 0x0c /* DMAC Software Chunk Transfer Request Register */
#define SAM_DMAC_LAST_OFFSET 0x10 /* DMAC Software Last Transfer Flag Register */
/* 0x014: Reserved */
#define SAM_DMAC_EBCIER_OFFSET 0x18 /* DMAC Error Enable */
#define SAM_DMAC_EBCIDR_OFFSET 0x1C /* DMAC Error Disable */
#define SAM_DMAC_EBCIMR_OFFSET 0x20 /* DMAC Error Mask */
#define SAM_DMAC_EBCISR_OFFSET 0x24 /* DMAC Error Status */
#define SAM_DMAC_CHER_OFFSET 0x28 /* DMAC Channel Handler Enable Register */
#define SAM_DMAC_CHDR_OFFSET 0x2c /* DMAC Channel Handler Disable Register */
#define SAM_DMAC_CHSR_OFFSET 0x30 /* DMAC Channel Handler Status Register */
/* 0x034-0x38: Reserved */
#define SAM_DMAC_GCFG_OFFSET 0x0000 /* DMAC Global Configuration Register */
#define SAM_DMAC_EN_OFFSET 0x0004 /* DMAC Enable Register */
#define SAM_DMAC_SREQ_OFFSET 0x0008 /* DMAC Software Single Request Register */
#define SAM_DMAC_CREQ_OFFSET 0x000c /* DMAC Software Chunk Transfer Request Register */
#define SAM_DMAC_LAST_OFFSET 0x0010 /* DMAC Software Last Transfer Flag Register */
/* 0x014: Reserved */
#define SAM_DMAC_EBCIER_OFFSET 0x0018 /* DMAC Error Enable */
#define SAM_DMAC_EBCIDR_OFFSET 0x001C /* DMAC Error Disable */
#define SAM_DMAC_EBCIMR_OFFSET 0x0020 /* DMAC Error Mask */
#define SAM_DMAC_EBCISR_OFFSET 0x0024 /* DMAC Error Status */
#define SAM_DMAC_CHER_OFFSET 0x0028 /* DMAC Channel Handler Enable Register */
#define SAM_DMAC_CHDR_OFFSET 0x002c /* DMAC Channel Handler Disable Register */
#define SAM_DMAC_CHSR_OFFSET 0x0030 /* DMAC Channel Handler Status Register */
/* 0x034-0x38: Reserved */
/* DMA channel registers */
#define SAM_DMACHAN_OFFSET(n) (0x3c+((n)*0x28))
#define SAM_DMACHAN0_OFFSET 0x3c /* 0x3c-0x60: Channel 0 */
#define SAM_DMACHAN1_OFFSET 0x64 /* 0x64-0x88: Channel 1 */
#define SAM_DMACHAN2_OFFSET 0x8c /* 0x8c-0xb0: Channel 2 */
#define SAM_DMACHAN3_OFFSET 0xb4 /* 0xb4-0xd8: Channel 3 */
#define SAM_DMACHAN_OFFSET(n) (0x003c+((n)*0x28))
#define SAM_DMACHAN0_OFFSET 0x003c /* 0x3c-0x60: Channel 0 */
#define SAM_DMACHAN1_OFFSET 0x0064 /* 0x64-0x88: Channel 1 */
#define SAM_DMACHAN2_OFFSET 0x008c /* 0x8c-0xb0: Channel 2 */
#define SAM_DMACHAN3_OFFSET 0x00b4 /* 0xb4-0xd8: Channel 3 */
#define SAM_DMACHAN_SADDR_OFFSET 0x00 /* DMAC Channel Source Address Register */
#define SAM_DMACHAN_DADDR_OFFSET 0x04 /* DMAC Channel Destination Address Register */
#define SAM_DMACHAN_DSCR_OFFSET 0x08 /* DMAC Channel Descriptor Address Register */
#define SAM_DMACHAN_CTRLA_OFFSET 0x0c /* DMAC Channel Control A Register */
#define SAM_DMACHAN_CTRLB_OFFSET 0x10 /* DMAC Channel Control B Register */
#define SAM_DMACHAN_CFG_OFFSET 0x14 /* DMAC Channel Configuration Register */
#define SAM_DMACHAN_SADDR_OFFSET 0x0000 /* DMAC Channel Source Address Register */
#define SAM_DMACHAN_DADDR_OFFSET 0x0004 /* DMAC Channel Destination Address Register */
#define SAM_DMACHAN_DSCR_OFFSET 0x0008 /* DMAC Channel Descriptor Address Register */
#define SAM_DMACHAN_CTRLA_OFFSET 0x000c /* DMAC Channel Control A Register */
#define SAM_DMACHAN_CTRLB_OFFSET 0x0010 /* DMAC Channel Control B Register */
#define SAM_DMACHAN_CFG_OFFSET 0x0014 /* DMAC Channel Configuration Register */
/* 0x18-0x24: Reserved */
/* 0x017c-0x1fc: Reserved */
/* More Global Registers */
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_DMAC_WPMR_OFFSET 0x01e4 /* DMAC Write Protect Mode Register */
# define SAM_DMAC_WPSR_OFFSET 0x01e8 /* DMAC Write Protect Status Register DMAC_WPSR */
#endif
/* DMAC register adresses ***************************************************************/
@@ -144,6 +151,13 @@
#define SAM_DMACHAN3_CTRLB (SAM_DMACHAN3_BASE+SAM_DMACHAN_CTRLB_OFFSET)
#define SAM_DMACHAN3_CFG (SAM_DMACHAN3_BASE+SAM_DMACHAN_CFG_OFFSET)
/* More Global Registers */
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_DMAC_WPMR (SAM_DMAC_BASE+SAM_DMAC_WPMR_OFFSET)
# define SAM_DMAC_WPSR (SAM_DMAC_BASE+SAM_DMAC_WPSR_OFFSET)
#endif
/* DMAC register bit definitions ********************************************************/
/* Global Registers */
@@ -160,14 +174,14 @@
#define DMAC_SREQ_SHIFT(n) ((n)<<1)
#define DMAC_SREQ_MASK(n) (3 << DMAC_SREQ_SHIFT(n))
#define DMAC_SREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */
#define DMAC_SREQ0_MASK (3 << DMAC_SREQ0_SHIFT)
#define DMAC_SREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */
#define DMAC_SREQ1_MASK (3 << DMAC_SREQ1_SHIFT)
#define DMAC_SREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */
#define DMAC_SREQ2_MASK (3 << DMAC_SREQ2_SHIFT)
#define DMAC_SREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */
#define DMAC_SREQ3_MASK (3 << DMAC_SREQ3_SHIFT)
# define DMAC_SREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */
# define DMAC_SREQ0_MASK (3 << DMAC_SREQ0_SHIFT)
# define DMAC_SREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */
# define DMAC_SREQ1_MASK (3 << DMAC_SREQ1_SHIFT)
# define DMAC_SREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */
# define DMAC_SREQ2_MASK (3 << DMAC_SREQ2_SHIFT)
# define DMAC_SREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */
# define DMAC_SREQ3_MASK (3 << DMAC_SREQ3_SHIFT)
#define DMAC_SREQ_SSREQ_SHIFT (0) /* Bits 0, 2, 4, 6: Request a source single transfer */
# define DMAC_SREQ_SSREQ(n) (1 << (DMAC_SREQ_SSREQ_SHIFT+DMAC_SREQ_SHIFT(n)))
@@ -186,14 +200,14 @@
#define DMAC_CREQ_SHIFT(n) ((n)<<1)
#define DMAC_CREQ_MASK(n) (3 << DMAC_CREQ_SHIFT(n))
#define DMAC_CREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */
#define DMAC_CREQ0_MASK (3 << DMAC_CREQ0_SHIFT)
#define DMAC_CREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */
#define DMAC_CREQ1_MASK (3 << DMAC_CREQ1_SHIFT)
#define DMAC_CREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */
#define DMAC_CREQ2_MASK (3 << DMAC_CREQ2_SHIFT)
#define DMAC_CREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */
#define DMAC_CREQ3_MASK (3 << DMAC_CREQ3_SHIFT)
# define DMAC_CREQ0_SHIFT (0) /* Bits 0-1: Channel 0 */
# define DMAC_CREQ0_MASK (3 << DMAC_CREQ0_SHIFT)
# define DMAC_CREQ1_SHIFT (2) /* Bits 2-3: Channel 1 */
# define DMAC_CREQ1_MASK (3 << DMAC_CREQ1_SHIFT)
# define DMAC_CREQ2_SHIFT (4) /* Bits 4-5: Channel 2 */
# define DMAC_CREQ2_MASK (3 << DMAC_CREQ2_SHIFT)
# define DMAC_CREQ3_SHIFT (6) /* Bits 6-7: Channel 3 */
# define DMAC_CREQ3_MASK (3 << DMAC_CREQ3_SHIFT)
#define DMAC_CREQ_SCREQ_SHIFT (0) /* Bits 0, 2, 4, 6: Request a source chunk transfer */
# define DMAC_CREQ_SCREQ(n) (1 << (DMAC_CREQ_SCREQ_SHIFT+DMAC_CREQ_SHIFT(n)))
@@ -212,14 +226,14 @@
#define DMAC_LAST_SHIFT(n) ((n)<<1)
#define DMAC_LAST_MASK(n) (3 << DMAC_LAST_SHIFT(n))
#define DMAC_LAST0_SHIFT (0) /* Bits 0-1: Channel 0 */
#define DMAC_LAST0_MASK (3 << DMAC_LAST0_SHIFT)
#define DMAC_LAST1_SHIFT (2) /* Bits 2-3: Channel 1 */
#define DMAC_LAST1_MASK (3 << DMAC_LAST1_SHIFT)
#define DMAC_LAST2_SHIFT (4) /* Bits 4-5: Channel 2 */
#define DMAC_LAST2_MASK (3 << DMAC_LAST2_SHIFT)
#define DMAC_LAST3_SHIFT (6) /* Bits 6-7: Channel 3 */
#define DMAC_LAST3_MASK (3 << DMAC_LAST3_SHIFT)
# define DMAC_LAST0_SHIFT (0) /* Bits 0-1: Channel 0 */
# define DMAC_LAST0_MASK (3 << DMAC_LAST0_SHIFT)
# define DMAC_LAST1_SHIFT (2) /* Bits 2-3: Channel 1 */
# define DMAC_LAST1_MASK (3 << DMAC_LAST1_SHIFT)
# define DMAC_LAST2_SHIFT (4) /* Bits 4-5: Channel 2 */
# define DMAC_LAST2_MASK (3 << DMAC_LAST2_SHIFT)
# define DMAC_LAST3_SHIFT (6) /* Bits 6-7: Channel 3 */
# define DMAC_LAST3_MASK (3 << DMAC_LAST3_SHIFT)
#define DMAC_LAST_SLAST_SHIFT (0) /* Bits 0, 2, 4, 6: Indicates the last transfer */
# define DMAC_LAST_SLAST(n) (1 << (DMAC_LAST_SLAST_SHIFT+DMAC_LAST_SHIFT(n)))
@@ -342,17 +356,26 @@
# define DMAC_CHSR_STAL3 (1 << (DMAC_CHSR_STAL_SHIFT+3))
/* DMA channel registers */
/* DMAC Channel n [n = 0..3] Source Address Register -- 32-bit address*/
/* DMAC Channel n [n = 0..3] Destination Address Register -- 32-bit address*/
/* DMAC Channel n [n = 0..3] Descriptor Address Register -- 32-bit address*/
/* DMAC Channel n [n = 0..3] Control A Register */
#define DMACHAN_CTRLA_BTSIZE_MAX (0xfff)
#define DMACHAN_CTRLA_BTSIZE_SHIFT (0) /* Bits 0-11: Buffer Transfer Size */
#define DMACHAN_CTRLA_BTSIZE_MASK (DMACHAN_CTRLA_BTSIZE_MAX << DMACHAN_CTRLA_BTSIZE_SHIFT)
#define DMACHAN_CTRLA_SCSIZE (1 << 16) /* Bit 16: Source Chunk Transfer Size */
# define DMACHAN_CTRLA_SCSIZE_1 (0)
# define DMACHAN_CTRLA_SCSIZE_4 DMACHAN_CTRLA_SCSIZE
#define DMACHAN_CTRLA_DCSIZE (1 << 20) /* Bit 20: Destination Chunk Transfer size */
# define DMACHAN_CTRLA_DCSIZE_1 (0)
# define DMACHAN_CTRLA_DCSIZE_4 DMACHAN_CTRLA_DCSIZE
# define DMACHAN_CTRLA_BTSIZE(n) ((uint32_t)(n) << DMACHAN_CTRLA_BTSIZE_SHIFT)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define DMACHAN_CTRLA_SCSIZE (1 << 16) /* Bit 16: Source Chunk Transfer Size */
# define DMACHAN_CTRLA_SCSIZE_1 (0)
# define DMACHAN_CTRLA_SCSIZE_4 DMACHAN_CTRLA_SCSIZE
# define DMACHAN_CTRLA_DCSIZE (1 << 20) /* Bit 20: Destination Chunk Transfer size */
# define DMACHAN_CTRLA_DCSIZE_1 (0)
# define DMACHAN_CTRLA_DCSIZE_4 DMACHAN_CTRLA_DCSIZE
#endif
#define DMACHAN_CTRLA_SRCWIDTH_SHIFT (24) /* Bits 24-25 */
#define DMACHAN_CTRLA_SRCWIDTH_MASK (3 << DMACHAN_CTRLA_SRCWIDTH_SHIFT)
# define DMACHAN_CTRLA_SRCWIDTH_BYTE (0 << DMACHAN_CTRLA_SRCWIDTH_SHIFT)
@@ -378,10 +401,16 @@
#define DMACHAN_CTRLB_SRCINCR_SHIFT (24) /* Bits 24-25 */
#define DMACHAN_CTRLB_SRCINCR_MASK (3 << DMACHAN_CTRLB_SRCINCR_SHIFT)
# define DMACHAN_CTRLB_SRCINCR_INCR (0 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Incrementing address */
# if defined(CONFIG_ARCH_CHIP_SAM4E)
# define DMACHAN_CTRLB_SRCINCR_DECR (1 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Decrementing address */
# endif
# define DMACHAN_CTRLB_SRCINCR_FIXED (2 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Fixed address */
#define DMACHAN_CTRLB_DSTINCR_SHIFT (28) /* Bits 28-29 */
#define DMACHAN_CTRLB_DSTINCR_MASK (3 << DMACHAN_CTRLB_DSTINCR_SHIFT)
# define DMACHAN_CTRLB_DSTINCR_INCR (0 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Incrementing address */
# if defined(CONFIG_ARCH_CHIP_SAM4E)
# define DMACHAN_CTRLB_DSTINCR_DECR (1 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Decrementing address */
# endif
# define DMACHAN_CTRLB_DSTINCR_FIXED (2 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Fixed address */
#define DMACHAN_CTRLB_IEN (1 << 30) /* Bit 30: Clear sets BTC[n] flag in EBCISR */
@@ -397,22 +426,59 @@
#define DMACHAN_CFG_LOCKIF (1 << 20) /* Bit 20: Enable lock interface capability */
#define DMACHAN_CFG_LOCKB (1 << 21) /* Bit 21: Enable AHB Bus Locking capability */
#define DMACHAN_CFG_LOCKIFL (1 << 22) /* Bit 22: Lock Master Interface Arbiter */
#define DMACHAN_CFG_AHBPRO_SHIFT (24) /* Bits 24-26: Bus access privilege */
#define DMACHAN_CFG_AHBPRO_MASK (7 << DMACHAN_CFG_AHBPRO_SHIFT)
# define DMACHAN_CFG_AHBPRO_PRIV (1 << DMACHAN_CFG_AHBPRO_SHIFT)
# define DMACHAN_CFG_AHBPRO_BUFF (2 << DMACHAN_CFG_AHBPRO_SHIFT)
# define DMACHAN_CFG_AHBPRO_CACHE (4 << DMACHAN_CFG_AHBPRO_SHIFT)
#define DMACHAN_CFG_AHBPROT_SHIFT (24) /* Bits 24-26: Bus access privilege */
#define DMACHAN_CFG_AHBPROT_MASK (7 << DMACHAN_CFG_AHBPROT_SHIFT)
# define DMACHAN_CFG_AHBPROT_PRIV (1 << DMACHAN_CFG_AHBPROT_SHIFT)
# define DMACHAN_CFG_AHBPROT_BUFF (2 << DMACHAN_CFG_AHBPROT_SHIFT)
# define DMACHAN_CFG_AHBPROT_CACHE (4 << DMACHAN_CFG_AHBPROT_SHIFT)
#define DMACHAN_CFG_FIFOCFG_SHIFT (28) /* Bits 28-29 */
#define DMACHAN_CFG_FIFOCFG_MASK (3 << DMACHAN_CFG_FIFOCFG_SHIFT)
# define DMACHAN_CFG_FIFOCFG_LARGEST (0 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Largest length AHB burst */
# define DMACHAN_CFG_FIFOCFG_HALF (1 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Half FIFO size */
# define DMACHAN_CFG_FIFOCFG_SINGLE (2 << DMACHAN_CFG_FIFOCFG_SHIFT) /* Single AHB access */
/* More Global Registers */
/* DMAC Write Protect Mode Register */
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define DMAC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
# define DMAC_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
# define DMAC_WPMR_WPKEY_MASK (0x00ffffff << DMAC_WPMR_WPKEY_SHIFT)
# define DMAC_WPMR_WPKEY (0x00444d41 << DMAC_WPMR_WPKEY_SHIFT)
#endif
/* DMAC Write Protect Status Register DMAC_WPSR */
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define DMAC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */
# define DMAC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
# define DMAC_WPSR_WPVSRC_MASK (0xffff << DMAC_WPSR_WPVSRC_SHIFT)
#endif
/* DMA Peripheral IDs *******************************************************************/
#define DMACHAN_PID_MCI0 0
#define DMACHAN_PID_SSC 3
#define DMACHAN_PID_MCI1 13
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define DMACHAN_PID_MCI0 0
# define DMACHAN_PID_SSC 3
# define DMACHAN_PID_MCI1 13
#endif
/* Hardware interface numbers */
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define DMAC_INTF_HSMCI 0 /* HSMCI Transmit/Receive */
# define DMAC_INTF_SPI0TX 1 /* SPI Transmit */
# define DMAC_INTF_SPI0RX 2 /* SPI Receive */
# define DMAC_INTF_USART0TX 3 /* USART0 Transmit */
# define DMAC_INTF_USART0RX 4 /* USART0 Receive */
# define DMAC_INTF_USART1TX 5 /* USART1 Transmit */
# define DMAC_INTF_USART1RX 6 /* USART1 Receive */
# define DMAC_INTF_AESTX 11 /* AES Transmit */
# define DMAC_INTF_AESRX 12 /* AES Receive */
# define DMAC_INTF_PWMTX 13 /* PWM Transmit */
#endif
/****************************************************************************************
* Public Types
@@ -437,4 +503,4 @@ struct dma_linklist_s
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_DMAC_H */
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_DMAC_H */
arch/arm/src/sam34/chip/sam_tc.h
+435 -294
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File diff suppressed because it is too large Load Diff
arch/arm/src/sam34/chip/sam_twi.h
+50 -15
View File
@@ -1,8 +1,8 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam_twi.h
* Two-wire Interface (TWI) definitions for the SAM3U and SAM4S
* Two-wire Interface (TWI) definitions for the SAM3U, SAM4E, and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -52,19 +52,22 @@
/* TWI register offsets *****************************************************************/
#define SAM_TWI_CR_OFFSET 0x00 /* Control Register */
#define SAM_TWI_MMR_OFFSET 0x04 /* Master Mode Register */
#define SAM_TWI_SMR_OFFSET 0x08 /* Slave Mode Register */
#define SAM_TWI_IADR_OFFSET 0x0c /* Internal Address Register */
#define SAM_TWI_CWGR_OFFSET 0x10 /* Clock Waveform Generator Register */
#define SAM_TWI_SR_OFFSET 0x20 /* Status Register */
#define SAM_TWI_IER_OFFSET 0x24 /* Interrupt Enable Register */
#define SAM_TWI_IDR_OFFSET 0x28 /* Interrupt Disable Register */
#define SAM_TWI_IMR_OFFSET 0x2c /* Interrupt Mask Register */
#define SAM_TWI_RHR_OFFSET 0x30 /* Receive Holding Register */
#define SAM_TWI_THR_OFFSET 0x34 /* Transmit Holding Register */
/* 0x38-0xfc: Reserved */
/* 0x100-0x124: Reserved for the PDC */
#define SAM_TWI_CR_OFFSET 0x0000 /* Control Register */
#define SAM_TWI_MMR_OFFSET 0x0004 /* Master Mode Register */
#define SAM_TWI_SMR_OFFSET 0x0008 /* Slave Mode Register */
#define SAM_TWI_IADR_OFFSET 0x000c /* Internal Address Register */
#define SAM_TWI_CWGR_OFFSET 0x0010 /* Clock Waveform Generator Register */
#define SAM_TWI_SR_OFFSET 0x0020 /* Status Register */
#define SAM_TWI_IER_OFFSET 0x0024 /* Interrupt Enable Register */
#define SAM_TWI_IDR_OFFSET 0x0028 /* Interrupt Disable Register */
#define SAM_TWI_IMR_OFFSET 0x002c /* Interrupt Mask Register */
#define SAM_TWI_RHR_OFFSET 0x0030 /* Receive Holding Register */
#define SAM_TWI_THR_OFFSET 0x0034 /* Transmit Holding Register */
/* 0x38-0xfc: Reserved */
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TWI_WPMR_OFFSET 0x00e4 /* Protection Mode Register */
# define SAM_TWI_WPSR_OFFSET 0x00e8 /* Protection Status Register */
#endif
/* TWI register adresses ****************************************************************/
@@ -79,6 +82,10 @@
#define SAM_TWI_IMR(n) (SAM_TWIN_BASE(n)+SAM_TWI_IMR_OFFSET)
#define SAM_TWI_RHR(n) (SAM_TWIN_BASE(n)+SAM_TWI_RHR_OFFSET)
#define SAM_TWI_THR(n) (SAM_TWIN_BASE(n)+SAM_TWI_THR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TWI_WPMR(n) (SAM_TWIN_BASE(n)+SAM_TWI_WPMR_OFFSET)
# define SAM_TWI_WPSR(n) (SAM_TWIN_BASE(n)+SAM_TWI_WPSR_OFFSET)
#endif
#define SAM_TWI0_CR (SAM_TWI0_BASE+SAM_TWI_CR_OFFSET)
#define SAM_TWI0_MMR (SAM_TWI0_BASE+SAM_TWI_MMR_OFFSET)
@@ -91,6 +98,10 @@
#define SAM_TWI0_IMR (SAM_TWI0_BASE+SAM_TWI_IMR_OFFSET)
#define SAM_TWI0_RHR (SAM_TWI0_BASE+SAM_TWI_RHR_OFFSET)
#define SAM_TWI0_THR (SAM_TWI0_BASE+SAM_TWI_THR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TWI0_WPMR (SAM_TWI0_BASE+SAM_TWI_WPMR_OFFSET)
# define SAM_TWI0_WPSR (SAM_TWI0_BASE)+SAM_TWI_WPSR_OFFSET)
#endif
#define SAM_TWI1_CR (SAM_TWI1_BASE+SAM_TWI_CR_OFFSET)
#define SAM_TWI1_MMR (SAM_TWI1_BASE+SAM_TWI_MMR_OFFSET)
@@ -103,6 +114,10 @@
#define SAM_TWI1_IMR (SAM_TWI1_BASE+SAM_TWI_IMR_OFFSET)
#define SAM_TWI1_RHR (SAM_TWI1_BASE+SAM_TWI_RHR_OFFSET)
#define SAM_TWI1_THR (SAM_TWI1_BASE+SAM_TWI_THR_OFFSET)
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_TWI1_WPMR (SAM_TWI1_BASE+SAM_TWI_WPMR_OFFSET)
# define SAM_TWI1_WPSR (SAM_TWI1_BASE)+SAM_TWI_WPSR_OFFSET)
#endif
/* TWI register bit definitions *********************************************************/
@@ -143,10 +158,13 @@
#define TWI_CWGR_CLDIV_SHIFT (0) /* Bits 0-7: Clock Low Divider */
#define TWI_CWGR_CLDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT)
# define TWI_CWGR_CLDIV(n) ((uint32_t)(n) << TWI_CWGR_CLDIV_SHIFT)
#define TWI_CWGR_CHDIV_SHIFT (8) /* Bits 8-15: Clock High Divider */
#define TWI_CWGR_CHDIV_MASK (0xff << TWI_CWGR_CLDIV_SHIFT)
# define TWI_CWGR_CHDIV(n) ((uint32_t)(n) << TWI_CWGR_CLDIV_SHIFT)
#define TWI_CWGR_CKDIV_SHIFT (16) /* Bits 16-18: Clock Divider */
#define TWI_CWGR_CKDIV_MASK (7 << TWI_CWGR_CLDIV_SHIFT)
# define TWI_CWGR_CKDIV(n) ((uint32_t)(n) << TWI_CWGR_CLDIV_SHIFT)
/* TWI Status Register, TWI Interrupt Enable Register, TWI Interrupt Disable
* Register, and TWI Interrupt Mask Register common bit fields.
@@ -178,6 +196,23 @@
#define TWI_THR_TXDATA_SHIFT (0) /* Bits 0-7: Master or Slave Transmit Holding Data */
#define TWI_THR_TXDATA_MASK (0xff << TWI_THR_TXDATA_SHIFT)
/* Protection Mode Register */
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define TWI_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
# define TWI_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect Key */
# define TWI_WPMR_WPKEY_MASK (0x00ffffff << TWI_WPMR_WPKEY_SHIFT)
# define TWI_WPMR_WPKEY (0x00545749 << TWI_WPMR_WPKEY_SHIFT)
#endif
/* Protection Status Register */
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define TWI_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */
# define TWI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
# define TWI_WPSR_WPVSRC_MASK (0xffff << TWI_WPSR_WPVSRC_SHIFT)
#endif
/****************************************************************************************
* Public Types
****************************************************************************************/
arch/arm/src/sam34/sam3u_dmac.c → arch/arm/src/sam34/sam_dmac.c
+4 -4
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/sam34/sam3u_dmac.c
* arch/arm/src/sam34/sam_dmac.c
*
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -58,7 +58,7 @@
#include "sam_dmac.h"
#include "sam_periphclks.h"
#include "chip/sam_pmc.h"
#include "chip/sam3u_dmac.h"
#include "chip/sam_dmac.h"
/****************************************************************************
* Pre-processor Definitions
@@ -68,7 +68,7 @@
/* Condition out the whole file unless DMA is selected in the configuration */
#ifdef CONFIG_SAM34_DMA
#ifdef CONFIG_SAM34_DMAC
/* If AT90SAM3U support is enabled, then OS DMA support should also be enabled */
@@ -1715,4 +1715,4 @@ void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
dmadbg(" CFG[%08x]: %08x\n", dmach->base + SAM_DMACHAN_CFG_OFFSET, regs->cfg);
}
#endif /* CONFIG_DEBUG_DMA */
#endif /* CONFIG_SAM34_DMA */
#endif /* CONFIG_SAM34_DMAC */
arch/arm/src/sam34/sam_hsmci.c
+3 -3
View File
@@ -64,7 +64,7 @@
#include "sam_dmac.h"
#include "sam_hsmci.h"
#include "sam_periphclks.h"
#include "chip/sam3u_dmac.h"
#include "chip/sam_dmac.h"
#include "chip/sam_pmc.h"
#include "chip/sam_hsmci.h"
#include "chip/sam_pinmap.h"
@@ -77,8 +77,8 @@
/* Configuration ************************************************************/
#ifndef CONFIG_SAM34_DMA
# warning "HSMCI driver requires CONFIG_SAM34_DMA"
#ifndef CONFIG_SAM34_DMAC
# warning "HSMCI driver requires CONFIG_SAM34_DMAC"
#endif
#ifndef CONFIG_SCHED_WORKQUEUE
configs/arduino-due/README.txt
+1 -1
View File
@@ -817,7 +817,7 @@ Arduino DUE-specific Configuration Options
CONFIG_SAM34_PWM - Pulse Width Modulation
CONFIG_SAM34_ADC12B - 12-bit Analog To Digital Converter
CONFIG_SAM34_DACC - Digital To Analog Converter
CONFIG_SAM34_DMA - DMA Controller
CONFIG_SAM34_DMAC - DMA Controller
CONFIG_SAM34_UOTGHS - USB OTG High Speed
CONFIG_SAM34_TRNG - True Random Number Generator
CONFIG_SAM34_EMAC - Ethernet MAC
configs/arduino-due/nsh/defconfig
+1 -1
View File
@@ -165,7 +165,7 @@ CONFIG_SAM34_UART0=y
# CONFIG_SAM34_CAN1 is not set
# CONFIG_SAM34_SMC is not set
# CONFIG_SAM34_SDRAMC is not set
# CONFIG_SAM34_DMA is not set
# CONFIG_SAM34_DMAC is not set
# CONFIG_SAM34_UOTGHS is not set
# CONFIG_SAM34_RTC is not set
# CONFIG_SAM34_RTT is not set
configs/arduino-due/ostest/defconfig
+1 -1
View File
@@ -165,7 +165,7 @@ CONFIG_SAM34_UART0=y
# CONFIG_SAM34_CAN1 is not set
# CONFIG_SAM34_SMC is not set
# CONFIG_SAM34_SDRAMC is not set
# CONFIG_SAM34_DMA is not set
# CONFIG_SAM34_DMAC is not set
# CONFIG_SAM34_UOTGHS is not set
# CONFIG_SAM34_RTC is not set
# CONFIG_SAM34_RTT is not set
configs/sam3u-ek/README.txt
+2 -2
View File
@@ -381,7 +381,7 @@ SAM3U-EK-specific Configuration Options
CONFIG_SAM34_PWM - Pulse Width Modulation Controller
CONFIG_SAM34_ADC12B - 12-bit ADC Controller
CONFIG_SAM34_ADC - 10-bit ADC Controller
CONFIG_SAM34_DMA - DMA Controller
CONFIG_SAM34_DMAC - DMA Controller
CONFIG_SAM34_UDPHS - USB Device High Speed
Some subsystems can be configured to operate in different ways. The drivers
@@ -646,7 +646,7 @@ Configurations
System Type->ATSAM3/4 Peripheral Support
CONFIG_SAM34_HSMCI=y : Enable HSMCI support
CONFIG_SAM34_DMA=y : DMAC support is needed by HSMCI
CONFIG_SAM34_DMAC=y : DMAC support is needed by HSMCI
System Type
CONFIG_SAM34_GPIO_IRQ=y : PIO interrupts needed
configs/sam3u-ek/knsh/defconfig
+1 -1
View File
@@ -154,7 +154,7 @@ CONFIG_SAM34_UART0=y
# CONFIG_SAM34_ADC is not set
# CONFIG_SAM34_SMC is not set
# CONFIG_SAM34_NAND is not set
# CONFIG_SAM34_DMA is not set
# CONFIG_SAM34_DMAC is not set
# CONFIG_SAM34_UDPHS is not set
# CONFIG_SAM34_RTC is not set
# CONFIG_SAM34_RTT is not set
configs/sam3u-ek/nsh/defconfig
+1 -1
View File
@@ -165,7 +165,7 @@ CONFIG_SAM34_UART0=y
# CONFIG_SAM34_ADC is not set
# CONFIG_SAM34_SMC is not set
# CONFIG_SAM34_NAND is not set
# CONFIG_SAM34_DMA is not set
# CONFIG_SAM34_DMAC is not set
# CONFIG_SAM34_UDPHS is not set
# CONFIG_SAM34_UOTGHS is not set
# CONFIG_SAM34_RTC is not set
configs/sam3u-ek/nx/defconfig
+1 -1
View File
@@ -146,7 +146,7 @@ CONFIG_SAM34_UART0=y
# CONFIG_SAM34_ADC is not set
# CONFIG_SAM34_SMC is not set
# CONFIG_SAM34_NAND is not set
# CONFIG_SAM34_DMA is not set
# CONFIG_SAM34_DMAC is not set
# CONFIG_SAM34_UDPHS is not set
# CONFIG_SAM34_RTC is not set
# CONFIG_SAM34_RTT is not set
configs/sam3u-ek/nxwm/defconfig
+1 -1
View File
@@ -180,7 +180,7 @@ CONFIG_SAM34_UART0=y
# CONFIG_SAM34_ADC is not set
# CONFIG_SAM34_SMC is not set
# CONFIG_SAM34_NAND is not set
# CONFIG_SAM34_DMA is not set
# CONFIG_SAM34_DMAC is not set
# CONFIG_SAM34_UDPHS is not set
# CONFIG_SAM34_UOTGHS is not set
# CONFIG_SAM34_RTC is not set
configs/sam3u-ek/ostest/defconfig
+1 -1
View File
@@ -146,7 +146,7 @@ CONFIG_SAM34_UART0=y
# CONFIG_SAM34_ADC is not set
# CONFIG_SAM34_SMC is not set
# CONFIG_SAM34_NAND is not set
# CONFIG_SAM34_DMA is not set
# CONFIG_SAM34_DMAC is not set
# CONFIG_SAM34_UDPHS is not set
# CONFIG_SAM34_RTC is not set
# CONFIG_SAM34_RTT is not set