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SAMV7: More SDRAM logic. It does still does not work

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This commit is contained in:
Gregory Nutt
2015-03-14 13:27:00 -06:00
parent cc497202ed
commit 3b0615ece8
4 changed files with 164 additions and 78 deletions
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arch/arm/src/samv7/Kconfig
+23 -9
View File
@@ -480,9 +480,28 @@ config SAMV7_GPIOE_IRQ
endif # SAMV7_GPIO_IRQ
endif # ARCH_CHIP_SAMV7
if SAMV7_SPI0 || SAMV7_SPI1
menu "SDRAM Configuration"
depends on SAMV7_SDRAMC
config SAMV7_SDRAMSIZE
int "SDRAM size (bytes)"
default 0
---help---
This is the usable size of the SDRAM. This may be a value less that
the actual size of the SDRAM if, for some reason, you wish to
reserve the end of SDRAM memory for some other purpose.
config SAMV7_SDRAMHEAP
bool "SDRAM heap"
default y
---help---
Add the first SAMV7_SDRAMSIZE bytes of SDRAM to the heap. NOTE that
this requires also that MM_REGIONS be incremented to support another memory region.
endmenu # SDRAM Configuration
menu "SAMV7 SPI device driver options"
depends on AMV7_SPI0 || SAMV7_SPI1
config SAMV7_SPI_DMA
bool "SPI DMA"
@@ -519,11 +538,9 @@ config SAMV7_SPI_REGDEBUG
Requires also DEBUG.
endmenu # SAMV7 SPI device driver options
endif # SAMV7_SPI0 || SAMV7_SPI1
if SAMV7_TWIHS0 || SAMV7_TWIHS1 || SAMV7_TWIHS2
menu "TWIHS device driver options"
depends on SAMV7_TWIHS0 || SAMV7_TWIHS1 || SAMV7_TWIHS2
config SAMV7_TWIHS0_FREQUENCY
int "TWIHS0 Frequency"
@@ -549,10 +566,9 @@ config SAMV7_TWIHS_REGDEBUG
Very invasive! Requires also DEBUG.
endmenu # TWIHS device driver options
endif # SAMV7_TWIHS0 || SAMV7_TWIHS1 || SAMV7_TWIHS2
if SAMV7_SSC
menu "SSC Configuration"
depends on SAMV7_SSC
config SAMV7_SSC_MAXINFLIGHT
int "SSC queue size"
@@ -940,10 +956,9 @@ config SAMV7_SSC_DUMPBUFFERS
Enable instrumentation to dump TX and RX buffers.
endmenu # SSC Configuration
endif # SAMV7_SSC
if SAMV7_HSMCI
menu "HSMCI device driver options"
depends on SAMV7_HSMCI
config SAMV7_HSMCI_RDPROOF
bool "Read Proof Enable"
@@ -994,4 +1009,3 @@ config SAMV7_HSMCI_REGDEBUG
Very invasive! Requires also DEBUG.
endmenu # HSMCI device driver options
endif # SAMV7_HSMCI
arch/arm/src/samv7/sam_allocateheap.c
+63 -46
View File
@@ -59,18 +59,22 @@
/****************************************************************************
* Private Definitions
****************************************************************************/
/* All SAM's have SRAM0.and possibly NFCSRAM. NFCSRAM may not be used,
* however, if NAND support is enabled. External memory may also be
* available.
*
* REVISIT: Support for external SRAM at CS1-3 is not fully implemented.
/* All SAM's have SRAM. In addition, they may have external SRAM or SDRAM */
#define HAVE_SDRAM_REGION 0 /* Assume no external SDRAM */
#define HAVE_EXTSRAM0_REGION 0 /* Assume no external SRAM at CS0 */
#define HAVE_EXTSRAM1_REGION 0 /* Assume no external SRAM at CS1 */
#define HAVE_EXTSRAM2_REGION 0 /* Assume no external SRAM at CS2 */
#define HAVE_EXTSRAM3_REGION 0 /* Assume no external SRAM at CS3 */
/* Check if external SDRAM is supported and, if so, it is is intended
* to be used as heap.
*/
#undef HAVE_NFCSRAM_REGION /* Assume no available NFC SRAM */
#undef HAVE_EXTSRAM0_REGION /* Assume no external SRAM at CS0 */
#undef HAVE_EXTSRAM1_REGION /* Assume no external SRAM at CS1 */
#undef HAVE_EXTSRAM2_REGION /* Assume no external SRAM at CS2 */
#undef HAVE_EXTSRAM3_REGION /* Assume no external SRAM at CS3 */
#if !defined(CONFIG_SAMV7_SDRAMC) || !defined(CONFIG_SAMV7_SDRAMHEAP)
# undef CONFIG_SAMV7_SDRAMSIZE
# define CONFIG_SAMV7_SDRAMSIZE 0
#endif
/* Check if external SRAM is supported and, if so, it is is intended
* to be used as heap.
@@ -96,33 +100,52 @@
# define CONFIG_SAMV7_EXTSRAM3SIZE 0
#endif
/* NFCSRAM is not available is NAND is supported */
/* Now lets reconcile the number of configured regions with the available
* memory resource configured for use as a heap region.
*/
#ifdef CONFIG_SAMV7_NAND
# undef SAMV7_NFCSRAM_SIZE
# define SAMV7_NFCSRAM_SIZE 0
#if CONFIG_SAMV7_SDRAMSIZE > 0
# if CONFIG_MM_REGIONS > 1
# undef HAVE_SDRAM_REGION
# define HAVE_SDRAM_REGION 1
# else
# warning "CONFIG_MM_REGIONS < 2: SDRAM not included in HEAP"
# endif
#endif
#if SAMV7_NFCSRAM_SIZE > 0
# if CONFIG_MM_REGIONS > 2
# define HAVE_NFCSRAM_REGION
# else
# warning "CONFIG_MM_REGIONS < 3: NFC SRAM not included in HEAP"
# endif
# if CONFIG_SAMV7_EXTSRAM0SIZE > 0
# if CONFIG_MM_REGIONS > 3
# define HAVE_EXTSRAM0_REGION 1
# else
# warning "CONFIG_MM_REGIONS < 4: External SRAM not included in HEAP"
# endif
# endif
#elif CONFIG_SAMV7_EXTSRAM0SIZE > 0
# if CONFIG_MM_REGIONS > 2
#if CONFIG_SAMV7_EXTSRAM0SIZE > 0
# if CONFIG_MM_REGIONS > (HAVE_SDRAM_REGION + 1)
# undef HAVE_EXTSRAM0_REGION
# define HAVE_EXTSRAM0_REGION 1
# else
# warning "CONFIG_MM_REGIONS < 3: External SRAM not included in HEAP"
# warning "CONFIG_MM_REGIONS too small: External SRAM0 not included in HEAP"
# endif
#endif
#if CONFIG_SAMV7_EXTSRAM1SIZE > 0
# if CONFIG_MM_REGIONS > (HAVE_SDRAM_REGION + HAVE_EXTSRAM0_REGION + 1)
# undef HAVE_EXTSRAM1_REGION
# define HAVE_EXTSRAM1_REGION 1
# else
# warning "CONFIG_MM_REGIONS too small: External SRAM1 not included in HEAP"
# endif
#endif
#if CONFIG_SAMV7_EXTSRAM2SIZE > 0
# if CONFIG_MM_REGIONS > (HAVE_SDRAM_REGION + HAVE_EXTSRAM0_REGION + HAVE_EXTSRAM1_REGION + 1)
# undef HAVE_EXTSRAM2_REGION
# define HAVE_EXTSRAM2_REGION 1
# else
# warning "CONFIG_MM_REGIONS too small: External SRAM2 not included in HEAP"
# endif
#endif
#if CONFIG_SAMV7_EXTSRAM3SIZE > 0
# if CONFIG_MM_REGIONS > (HAVE_SDRAM_REGION + HAVE_EXTSRAM0_REGION + HAVE_EXTSRAM1_REGION + HAVE_EXTSRAM2_REGION + 1)
# undef HAVE_EXTSRAM3_REGION
# define HAVE_EXTSRAM3_REGION 1
# else
# warning "CONFIG_MM_REGIONS too small: External SRAM3 not included in HEAP"
# endif
#endif
@@ -287,24 +310,18 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
#if CONFIG_MM_REGIONS > 1
void up_addregion(void)
{
#ifdef HAVE_NFCSRAM_REGION
/* Clocking may need to be applied to the SMC module in order for the
* NFCS SRAM to be functional.
*/
sam_smc_enableclk();
#if HAVE_SDRAM_REGION != 0
/* Allow user access to the heap memory */
sam_mpu_uheap(SAM_NFCSRAM_BASE, SAMV7_NFCSRAM_SIZE);
sam_mpu_uheap(SAM_SDRAMCS_BASE, CONFIG_SAMV7_SDRAMSIZE);
/* Add the region */
kumm_addregion((FAR void*)SAM_NFCSRAM_BASE, SAMV7_NFCSRAM_SIZE);
kumm_addregion((FAR void*)SAM_SDRAMCS_BASE, CONFIG_SAMV7_SDRAMSIZE);
#endif /* HAVE_NFCSRAM_REGION */
#endif /* HAVE_SDRAM_REGION */
#ifdef HAVE_EXTSRAM0_REGION
#if HAVE_EXTSRAM0_REGION != 0
/* Allow user access to the heap memory */
sam_mpu_uheap(SAM_EXTCS0_BASE, CONFIG_SAMV7_EXTSRAM0SIZE);
@@ -315,7 +332,7 @@ void up_addregion(void)
#endif /* HAVE_EXTSRAM0_REGION */
#ifdef HAVE_EXTSRAM1_REGION
#if HAVE_EXTSRAM1_REGION != 0
/* Allow user access to the heap memory */
sam_mpu_uheap(SAM_EXTCS1_BASE, CONFIG_SAMV7_EXTSRAM1SIZE);
@@ -326,7 +343,7 @@ void up_addregion(void)
#endif /* HAVE_EXTSRAM0_REGION */
#ifdef HAVE_EXTSRAM2_REGION
#if HAVE_EXTSRAM2_REGION != 0
/* Allow user access to the heap memory */
sam_mpu_uheap(SAM_EXTCS2_BASE, CONFIG_SAMV7_EXTSRAM2SIZE);
@@ -337,7 +354,7 @@ void up_addregion(void)
#endif /* HAVE_EXTSRAM0_REGION */
#ifdef HAVE_EXTSRAM3_REGION
#if HAVE_EXTSRAM3_REGION != 0
/* Allow user access to the heap memory */
sam_mpu_uheap(SAM_EXTCS3_BASE, CONFIG_SAMV7_EXTSRAM3SIZE);
configs/samv71-xult/README.txt
+36 -3
View File
@@ -437,7 +437,40 @@ Configuration sub-directories
Application Configuration:
CONFIG_NSH_BUILTIN_APPS=y : Enable starting apps from NSH command line
3. The button test at apps/examples/buttons is included in the
4. SDRAM is not enabled in this configuration. I have enabled SDRAM and
the apps/examples RAM test using this configuration settings:
System Type
CONFIG_SAMV7_SDRAMC=y
CONFIG_SAMV7_SDRAMSIZE=2097152
Application Configuration:
CONFIG_SYSTEM_RAMTEST=y
The RAM test can be executed as follows:
nsh> ramtest -w 70000000 209152
STATUS: As of this writing, SDRAM does not pass the RAM test. This is the sympton:
nsh> mw 70000000
70000000 = 0x00000000
nsh> mw 70000000=55555555
70000000 = 0x00000000 -> 0x55555555
nsh> mw 70000000
70000000 = 0x55555555
nsh> mw 70100000
70100000 = 0x00000000
nsh> mw 70100000=aaaaaaaa
70100000 = 0x00000000 -> 0xaaaaaaaa
nsh> mw 70100000
70100000 = 0xaaaaaaaa
nsh> mw 70000000
70000000 = 0x00000000 <<< Lost RAM content
5. The button test at apps/examples/buttons is included in the
configuration. This configuration illustrates (1) use of the buttons
on the evaluation board, and (2) the use of PIO interrupts. Example
usage:
@@ -466,7 +499,7 @@ Configuration sub-directories
SW1 depressed
nsh>
4. TWI/I2C
6. TWI/I2C
TWIHS0 is enabled in this configuration. The SAM V71 Xplained Ultra
supports two devices on the one on-board I2C device on the TWIHS0 bus:
@@ -544,7 +577,7 @@ Configuration sub-directories
CAREFUL!!! You can trash your MAC address using the I2C tool!
5. Performance-related Configuration settings:
7. Performance-related Configuration settings:
CONFIG_ARMV7M_ICACHE=y : Instruction cache is enabled
CONFIG_ARMV7M_DCACHE=y : Data cache is enabled
configs/samv71-xult/src/sam_sdram.c
+42 -20
View File
@@ -118,27 +118,49 @@ void sam_sdram_config(void)
sam_configgpio(GPIO_SMC_D14);
sam_configgpio(GPIO_SMC_D15);
sam_configgpio(GPIO_SMC_A0);
sam_configgpio(GPIO_SMC_A1);
sam_configgpio(GPIO_SMC_A2);
sam_configgpio(GPIO_SMC_A3);
sam_configgpio(GPIO_SMC_A4);
sam_configgpio(GPIO_SMC_A5);
sam_configgpio(GPIO_SMC_A6);
sam_configgpio(GPIO_SMC_A7);
sam_configgpio(GPIO_SMC_A8);
sam_configgpio(GPIO_SMC_A9);
sam_configgpio(GPIO_SDRAMC_A10_1);
/* SAMV71 SDRAM
* --------------- -----------
* PC20 A2 A0
* PC21 A3 A1
* PC22 A4 A2
* PC23 A5 A3
* PC24 A6 A4
* PC25 A7 A5
* PC26 A8 A6
* PC27 A9 A7
* PC28 A10 A8
* PC29 A11 A9
* PD13 SDA10 A10
* PA20 BA0 A11
* PD17 CAS nCAS
* PD14 SDCKE CKE
* PD23 SDCK CLK
* PC15 SDCS nCS
* PC18 A0/NBS0 LDQM
* PD16 RAS nRAS
* PD15 NWR1/NBS1 UDQM
* PD29 SDWE nWE
*/
sam_configgpio(GPIO_SDRAMC_CAS);
sam_configgpio(GPIO_SDRAMC_RAS);
sam_configgpio(GPIO_SDRAMC_CKE);
sam_configgpio(GPIO_SDRAMC_CK);
sam_configgpio(GPIO_SDRAMC_CS_1);
sam_configgpio(GPIO_SMC_NBS0);
sam_configgpio(GPIO_SMC_NBS1);
sam_configgpio(GPIO_SDRAMC_WE);
sam_configgpio(GPIO_SDRAMC_BA0);
sam_configgpio(GPIO_SMC_A2); /* PC20 A2 -> A0 */
sam_configgpio(GPIO_SMC_A3); /* PC21 A3 -> A1 */
sam_configgpio(GPIO_SMC_A4); /* PC22 A4 -> A2 */
sam_configgpio(GPIO_SMC_A5); /* PC23 A5 -> A3 */
sam_configgpio(GPIO_SMC_A6); /* PC24 A6 -> A4 */
sam_configgpio(GPIO_SMC_A7); /* PC25 A7 -> A5 */
sam_configgpio(GPIO_SMC_A8); /* PC26 A8 -> A6 */
sam_configgpio(GPIO_SMC_A9); /* PC27 A9 -> A7 */
sam_configgpio(GPIO_SDRAMC_A10_2); /* PD13 SDA10 -> A10 */
sam_configgpio(GPIO_SDRAMC_BA0); /* PA20 BA0 -> A11 */
sam_configgpio(GPIO_SDRAMC_CAS); /* PD17 CAS -> nCAS */
sam_configgpio(GPIO_SDRAMC_CKE); /* PD14 SDCKE -> CKE */
sam_configgpio(GPIO_SDRAMC_CK); /* PD23 SDCK -> CLK */
sam_configgpio(GPIO_SDRAMC_CS_1); /* PC15 SDCS -> nCS */
sam_configgpio(GPIO_SMC_NBS0); /* PC18 A0/NBS0 -> LDQM */
sam_configgpio(GPIO_SDRAMC_RAS); /* PD16 RAS -> nRAS */
sam_configgpio(GPIO_SMC_NBS1); /* PD15 NWR1/NBS1 -> UDQM */
sam_configgpio(GPIO_SDRAMC_WE); /* PD29 SDWE -> nWE */
/* Enable the SDRAMC peripheral */