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Merged in david_s5/nuttx/upstream_kinetis (pull request #221)

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Kinetis:Add LPUART

Approved-by: Gregory Nutt
This commit is contained in:
David Sidrane
2017-02-25 17:23:04 +00:00
committed by Gregory Nutt
parent d77d322a61 df01e343a7
commit 38df949adc
13 changed files with 1977 additions and 161 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/include/kinetis/chip.h
+2 -1
View File
@@ -1427,7 +1427,8 @@
# define KINETIS_NUSBDEV 1 /* One USB device controller */
# define KINETIS_NSDHC 1 /* SD host controller */
# define KINETIS_NI2C 4 /* Four I2C modules */
# define KINETIS_NUART 5 /* Five UART modues */
# define KINETIS_NUART 5 /* Five UART modules */
# define KINETIS_NLPUART 1 /* One LPUART modules */
# define KINETIS_NSPI 3 /* Three SPI modules */
# define KINETIS_NCAN 2 /* Two CAN controllers */
# define KINETIS_NI2S 1 /* One I2S modules */
arch/arm/src/kinetis/Kconfig
+218
View File
@@ -220,27 +220,60 @@ config ARCH_CHIP_MK66FN2M0VLQ18
endchoice
# These "hidden" settings determine is a peripheral option is available for
# the selection MCU
config KINETIS_HAVE_UART5
bool
default n
config KINETIS_HAVE_LPUART0
bool
default n
config KINETIS_HAVE_LPUART1
bool
default n
# When there are multiple instances of a device, these "hidden" settings
# will automatically be selected and will represent the 'OR' of the
# instances selected.
config KINETIS_LPUART
bool
default n
config KINETIS_UART
bool
default n
select MCU_SERIAL
# Chip families
config ARCH_FAMILY_K20
bool
default n
select KINETIS_HAVE_UART5
config ARCH_FAMILY_K40
bool
default n
select KINETIS_HAVE_UART5
config ARCH_FAMILY_K60
bool
default n
select KINETIS_HAVE_UART5
config ARCH_FAMILY_K64
bool
default n
select KINETIS_HAVE_UART5
config ARCH_FAMILY_K66
bool
default n
select KINETIS_HAVE_LPUART0
menu "Kinetis Peripheral Support"
@@ -280,6 +313,7 @@ config KINETIS_UART0
bool "UART0"
default n
select UART0_SERIALDRIVER
select KINETIS_UART
---help---
Support UART0
@@ -287,6 +321,7 @@ config KINETIS_UART1
bool "UART1"
default n
select UART1_SERIALDRIVER
select KINETIS_UART
---help---
Support UART1
@@ -294,6 +329,7 @@ config KINETIS_UART2
bool "UART2"
default n
select UART2_SERIALDRIVER
select KINETIS_UART
---help---
Support UART2
@@ -301,6 +337,7 @@ config KINETIS_UART3
bool "UART3"
default n
select UART3_SERIALDRIVER
select KINETIS_UART
---help---
Support UART3
@@ -308,16 +345,37 @@ config KINETIS_UART4
bool "UART4"
default n
select UART4_SERIALDRIVER
select KINETIS_UART
---help---
Support UART4
config KINETIS_UART5
bool "UART5"
default n
depends on KINETIS_HAVE_UART5
select UART5_SERIALDRIVER
select KINETIS_UART
---help---
Support UART5
config KINETIS_LPUART0
bool "Low power LPUART0"
default n
depends on KINETIS_HAVE_LPUART0
select OTHER_UART_SERIALDRIVER
select KINETIS_LPUART
---help---
Support the low power UART0
config KINETIS_LPUART1
bool "Low power LPUART1"
default n
depends on KINETIS_HAVE_LPUART1
select OTHER_UART_SERIALDRIVER
select KINETIS_LPUART
---help---
Support the low power UART1
config KINETIS_ENET
bool "Ethernet"
default n
@@ -839,6 +897,10 @@ config KINETIS_SD4BIT_FREQ
endif
endmenu # Kinetis SDHC Configuration
#
# MCU serial peripheral driver?
#
menu "Kinetis UART Configuration"
config KINETIS_UARTFIFOS
@@ -847,3 +909,159 @@ config KINETIS_UARTFIFOS
depends on KINETIS_UART0
endmenu # Kinetis UART Configuration
menu "Kinetis LPUART0 Configuration"
depends on KINETIS_LPUART0
config LPUART0_RXBUFSIZE
int "Receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config LPUART0_TXBUFSIZE
int "Transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config LPUART0_BAUD
int "BAUD rate"
default 115200
---help---
The configured BAUD of the UART.
config LPUART0_BITS
int "Character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config LPUART0_PARITY
int "Parity setting"
range 0 2
default 0
---help---
0=no parity, 1=odd parity, 2=even parity
config LPUART0_2STOP
int "use 2 stop bits"
default 0
---help---
1=Two stop bits
config LPUART0_IFLOWCONTROL
bool "LPUART0 RTS flow control"
default n
select SERIAL_IFLOWCONTROL
---help---
Enable LPUART0 RTS flow control
config LPUART0_OFLOWCONTROL
bool "LPUART0 CTS flow control"
default n
select SERIAL_OFLOWCONTROL
---help---
Enable LPUART0 CTS flow control
config LPUART0_DMA
bool "LPUART0 DMA support"
default n
select SERIAL_DMA
---help---
Enable DMA transfers on LPUART0
endmenu # Kinetis LPUART0 Configuration
menu "Kinetis LPUART1 Configuration"
depends on KINETIS_LPUART1
config LPUART1_RXBUFSIZE
int "Receive buffer size"
default 256
---help---
Characters are buffered as they are received. This specifies
the size of the receive buffer.
config LPUART1_TXBUFSIZE
int "Transmit buffer size"
default 256
---help---
Characters are buffered before being sent. This specifies
the size of the transmit buffer.
config LPUART1_BAUD
int "BAUD rate"
default 115200
---help---
The configured BAUD of the UART.
config LPUART1_BITS
int "Character size"
default 8
---help---
The number of bits. Must be either 7 or 8.
config LPUART1_PARITY
int "Parity setting"
range 0 2
default 0
---help---
0=no parity, 1=odd parity, 2=even parity
config LPUART1_2STOP
int "use 2 stop bits"
default 0
---help---
1=Two stop bits
config LPUART1_IFLOWCONTROL
bool "LPUART1 RTS flow control"
default n
select SERIAL_IFLOWCONTROL
---help---
Enable LPUART1 RTS flow control
config LPUART1_OFLOWCONTROL
bool "LPUART1 CTS flow control"
default n
select SERIAL_OFLOWCONTROL
---help---
Enable LPUART1 CTS flow control
config LPUART1_DMA
bool "LPUART1 DMA support"
default n
select SERIAL_DMA
---help---
Enable DMA transfers on LPUART1
endmenu # Kinetis LPUART1 Configuration
choice
prompt "Kinetis LPUART Serial Console"
default NO_LPUART_SERIAL_CONSOLE
depends on DEV_CONSOLE && KINETIS_LPUART
config LPUART0_SERIAL_CONSOLE
bool "Use LPUART0 as the serial console"
depends on KINETIS_LPUART0
select OTHER_SERIAL_CONSOLE
---help---
Use the LPUART0 device as the serial console
config LPUART1_SERIAL_CONSOLE
bool "Use LPUART1 as the serial console"
depends on KINETIS_LPUART1
select OTHER_SERIAL_CONSOLE
---help---
Use the LPUART1 device as the serial console
config NO_LPUART_SERIAL_CONSOLE
bool "No LPUART serial console"
---help---
No serial LPUART based console OR some other serial device provides the serial console
endchoice # Kinetis LPUART Serial Console
arch/arm/src/kinetis/Make.defs
+4
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@@ -162,6 +162,10 @@ ifeq ($(CONFIG_I2C),y)
CHIP_CSRCS += kinetis_i2c.c
endif
ifeq ($(CONFIG_KINETIS_LPUART),y)
CHIP_CSRCS += kinetis_lpserial.c
endif
ifeq ($(CONFIG_RTC),y)
CHIP_CSRCS += kinetis_rtc.c
ifeq ($(CONFIG_RTC_DRIVER),y)
arch/arm/src/kinetis/chip/kinetis_lpuart.h
+222
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@@ -0,0 +1,222 @@
/****************************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_lpuart.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane<david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPUART_H
#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPUART_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
/* Register Offsets *********************************************************************************/
#define KINETIS_LPUART_BAUD_OFFSET 0x0000 /* Low Power UART Baud Rate Register */
#define KINETIS_LPUART_STAT_OFFSET 0x0004 /* Low Power UART Status Register */
#define KINETIS_LPUART_CTRL_OFFSET 0x0008 /* Low Power UART Control Register */
#define KINETIS_LPUART_DATA_OFFSET 0x000c /* Low Power UART Data Register */
#define KINETIS_LPUART_MATCH_OFFSET 0x000c /* Low Power UART Match Address Register */
#define KINETIS_LPUART_MODIR_OFFSET 0x000c /* Low Power UART Modem IrDA Register */
/* Register Addresses *******************************************************************************/
#define KINETIS_LPUART0_BAUD (KINETIS_LPUART0_BASE+KINETIS_LPUART_BAUD_OFFSET)
#define KINETIS_LPUART0_STAT (KINETIS_LPUART0_BASE+KINETIS_LPUART_STAT_OFFSET)
#define KINETIS_LPUART0_CTRL (KINETIS_LPUART0_BASE+KINETIS_LPUART_CTRL_OFFSET)
#define KINETIS_LPUART0_DATA (KINETIS_LPUART0_BASE+KINETIS_LPUART_DATA_OFFSET)
#define KINETIS_LPUART0_MATCH (KINETIS_LPUART0_BASE+KINETIS_LPUART_MATCH_OFFSET)
#define KINETIS_LPUART0_MODIR (KINETIS_LPUART0_BASE+KINETIS_LPUART_MODIR_OFFSET)
/* Register Bit Definitions *************************************************************************/
/* Low Power UART Baud Rate Register */
#define LPUART_BAUD_SBR_SHIFT (0) /* Bits 0-12: Baud Rate Modulo Divisor */
#define LPUART_BAUD_SBR_MASK (0x1fff << LPUART_BAUD_SBR_SHIFT)
# define LPUART_BAUD_SBR(n) (((n) & 0x1fff) << LPUART_BAUD_SBR_SHIFT) /* n= 1..8191*/
#define LPUART_BAUD_SBNS (1 << 13) /* Bit 13: Stop Bit Number Select */
#define LPUART_BAUD_RXEDGIE (1 << 14) /* Bit 14: RX Input Active Edge Interrupt Enable */
#define LPUART_BAUD_LBKDIE (1 << 15) /* Bit 15: LIN Break Detect Interrupt Enable */
#define LPUART_BAUD_RESYNCDIS (1 << 16) /* Bit 16: Resynchronizations Disable */
#define LPUART_BAUD_BOTHEDGE (1 << 17) /* Bit 17: Both Edge Sampling */
#define LPUART_BAUD_MATCFG_SHIFT (18) /* Bits 18-19: Match Configuration */
#define LPUART_BAUD_MATCFG_MASK (3 << LPUART_BAUD_MATCFG_SHIFT)
# define LPUART_BAUD_MATCFG_AMW (0 << LPUART_BAUD_MATCFG_SHIFT) /* Address Match Wakeup */
# define LPUART_BAUD_MATCFG_IMW (1 << LPUART_BAUD_MATCFG_SHIFT) /* Idle Match Wakeup */
# define LPUART_BAUD_MATCFG_MONOFF (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */
# define LPUART_BAUD_MATCFG_RWU (3 << LPUART_BAUD_MATCFG_SHIFT) /* Enables RWU on Data Match and Match On/Off for transmitter CTS input */
/* Bit 20: Reserved */
#define LPUART_BAUD_RDMAE (1 << 21) /* Bit 21: Receiver Full DMA Enable */
/* Bit 22: Reserved */
#define LPUART_BAUD_TDMAE (1 << 23) /* Bit 23: Transmitter DMA Enable */
#define LPUART_BAUD_OSR_SHIFT (24) /* Bits 24-28: Over Sampling Ratio */
#define LPUART_BAUD_OSR_MASK (0x1f << LPUART_BAUD_OSR_SHIFT)
#define LPUART_BAUD_OSR(n) ((((n)-1) & 0x1f) << LPUART_BAUD_OSR_SHIFT) /* n=4..32 */
#define LPUART_BAUD_M10 (1 << 29) /* Bit 29: 10-bit Mode select */
#define LPUART_BAUD_MAEN2 (1 << 30) /* Bit 30: Match Address Mode Enable 2 */
#define LPUART_BAUD_MAEN1 (1 << 31) /* Bit 31: Match Address Mode Enable 1 */
/* Low Power UART Status Register */
/* Bits 0-13: Reserved */
#define LPUART_STAT_MA2F (1 << 14) /* Match 2 Flag */
#define LPUART_STAT_MA1F (1 << 15) /* Match 1 Flag */
#define LPUART_STAT_PF (1 << 16) /* Parity Error Flag */
#define LPUART_STAT_FE (1 << 17) /* Framing Error Flag */
#define LPUART_STAT_NF (1 << 18) /* Noise Flag */
#define LPUART_STAT_OR (1 << 19) /* Receiver Overrun Flag */
#define LPUART_STAT_IDLE (1 << 20) /* Idle Line Flag */
#define LPUART_STAT_RDRF (1 << 21) /* Receive Data Register Full Flag */
#define LPUART_STAT_TC (1 << 22) /* Transmission Complete Flag */
#define LPUART_STAT_TDRE (1 << 23) /* Transmit Data Register Empty Flag */
#define LPUART_STAT_RAF (1 << 24) /* Receiver Active Flag */
#define LPUART_STAT_LBKDE (1 << 25) /* LIN Break Detection Enable */
#define LPUART_STAT_BRK13 (1 << 26) /* Break Character Generation Length */
#define LPUART_STAT_RWUID (1 << 27) /* Receive Wake Up Idle Detect */
#define LPUART_STAT_RXINV (1 << 28) /* Receive Data Inversion */
#define LPUART_STAT_MSBF (1 << 29) /* MSB First */
#define LPUART_STAT_RXEDGIF (1 << 30) /* LPUART_RX Pin Active Edge Interrupt Flag */
#define LPUART_STAT_LBKDIF (1 << 31) /* LIN Break Detect Interrupt Flag */
/* Low Power UART Control Register */
#define LPUART_CTRL_PT (1 << 0) /* Bit 0: Parity Type */
#define LPUART_CTRL_PE (1 << 1) /* Bit 1: Parity Enable */
#define LPUART_CTRL_ILT (1 << 2) /* Bit 2: Idle Line Type Select */
#define LPUART_CTRL_WAKE (1 << 3) /* Bit 3: Receiver Wakeup Method Select */
#define LPUART_CTRL_M (1 << 4) /* Bit 4: 9-Bit or 8-Bit Mode Select */
#define LPUART_CTRL_RSRC (1 << 5) /* Bit 5: Receiver Source Select */
#define LPUART_CTRL_DOZEEN (1 << 6) /* Bit 6: Doze Enable */
#define LPUART_CTRL_LOOPS (1 << 7) /* Bit 7: Loop Mode Select */
#define LPUART_CTRL_IDLECFG_SHIFT (8) /* Bits 8-10: Idle Configuration */
#define LPUART_CTRL_IDLECFG_MASK (3 << LPUART_CTRL_IDLECFG_SHIFT)
# define LPUART_CTRL_IDLECFG_1 (0 << LPUART_CTRL_IDLECFG_SHIFT) /* 1 idle character */
# define LPUART_CTRL_IDLECFG_2 (1 << LPUART_CTRL_IDLECFG_SHIFT) /* 2 idle characters */
# define LPUART_CTRL_IDLECFG_4 (2 << LPUART_CTRL_IDLECFG_SHIFT) /* 4 idle characters */
# define LPUART_CTRL_IDLECFG_8 (3 << LPUART_CTRL_IDLECFG_SHIFT) /* 8 idle characters */
# define LPUART_CTRL_IDLECFG_16 (4 << LPUART_CTRL_IDLECFG_SHIFT) /* 16 idle characters */
# define LPUART_CTRL_IDLECFG_32 (5 << LPUART_CTRL_IDLECFG_SHIFT) /* 32 idle characters */
# define LPUART_CTRL_IDLECFG_64 (6 << LPUART_CTRL_IDLECFG_SHIFT) /* 64 idle characters */
# define LPUART_CTRL_IDLECFG_128 (7 << LPUART_CTRL_IDLECFG_SHIFT) /* 128 idle characters */
/* Bits 11-13: Reserved */
#define LPUART_CTRL_MA2IE (1 << 14) /* Bit 14: Match 2 Interrupt Enable */
#define LPUART_CTRL_MA1IE (1 << 15) /* Bit 15: Match 1 Interrupt Enable */
#define LPUART_CTRL_SBK (1 << 16) /* Bit 16: Send Break */
#define LPUART_CTRL_RWU (1 << 17) /* Bit 17: Receiver Wakeup Control */
#define LPUART_CTRL_RE (1 << 18) /* Bit 18: Receiver Enable */
#define LPUART_CTRL_TE (1 << 19) /* Bit 19: Transmitter Enable */
#define LPUART_CTRL_ILIE (1 << 20) /* Bit 20: Idle Line Interrupt Enable */
#define LPUART_CTRL_RIE (1 << 21) /* Bit 21: Receiver Interrupt Enable */
#define LPUART_CTRL_TCIE (1 << 22) /* Bit 22: Transmission Complete Interrupt Enable for */
#define LPUART_CTRL_TIE (1 << 23) /* Bit 23: Transmit Interrupt Enable */
#define LPUART_CTRL_PEIE (1 << 24) /* Bit 24: Parity Error Interrupt Enable */
#define LPUART_CTRL_FEIE (1 << 25) /* Bit 25: Framing Error Interrupt Enable */
#define LPUART_CTRL_NEIE (1 << 26) /* Bit 26: Noise Error Interrupt Enable */
#define LPUART_CTRL_ORIE (1 << 27) /* Bit 27: Overrun Interrupt Enable */
#define LPUART_CTRL_TXINV (1 << 28) /* Bit 28: Transmit Data Inversion */
#define LPUART_CTRL_TXDIR (1 << 29) /* Bit 29: LPUART_TX Pin Direction in Single-Wire Mode */
#define LPUART_CTRL_R9T8 (1 << 30) /* Bit 30: Receive Bit 9 / Transmit Bit 8 */
#define LPUART_CTRL_R8T9 (1 << 31) /* Bit 31: Receive Bit 8 / Transmit Bit 9 */
/* Low Power UART Data Register */
#define LPUART_DATA_SHIFT (0) /* Bits 0-9: Read receive/ write transmit data */
#define LPUART_DATA_MASK (0x3ff << LPUART_DATA_SHIFT)
#define LPUART_DATA8(n) (((n) & 0xff) << LPUART_DATA_SHIFT)
#define LPUART_DATA9(n) (((n) & 0x1ff) << LPUART_DATA_SHIFT)
#define LPUART_DATA10(n) (((n) & 0x3ff) << LPUART_DATA_SHIFT)
#define LPUART_DATA_R0T0 (1 << 0) /* Bit 0: Read receive data buffer 0 or write transmit data buffer 0 */
#define LPUART_DATA_R1T1 (1 << 1) /* Bit 1: Read receive data buffer 1 or write transmit data buffer 1 */
#define LPUART_DATA_R2T2 (1 << 2) /* Bit 2: Read receive data buffer 2 or write transmit data buffer 2 */
#define LPUART_DATA_R3T3 (1 << 3) /* Bit 3: Read receive data buffer 3 or write transmit data buffer 3 */
#define LPUART_DATA_R4T4 (1 << 4) /* Bit 4: Read receive data buffer 4 or write transmit data buffer 4 */
#define LPUART_DATA_R5T5 (1 << 5) /* Bit 5: Read receive data buffer 5 or write transmit data buffer 5 */
#define LPUART_DATA_R6T6 (1 << 6) /* Bit 6: Read receive data buffer 6 or write transmit data buffer 6 */
#define LPUART_DATA_R7T7 (1 << 7) /* Bit 7: Read receive data buffer 7 or write transmit data buffer 7 */
#define LPUART_DATA_R8T8 (1 << 8) /* Bit 8: Read receive data buffer 8 or write transmit data buffer 8 */
#define LPUART_DATA_R9T9 (1 << 9) /* Bit 9: Read receive data buffer 9 or write transmit data buffer 9 */
/* Bit 10: Reserved */
#define LPUART_DATA_IDLINE (1 << 11) /* Bit 11: Idle Line */
#define LPUART_DATA_RXEMPT (1 << 12) /* Bit 12: Receive Buffer Empty */
#define LPUART_DATA_FRETSC (1 << 13) /* Bit 13: Frame Error / Transmit Special Character */
#define LPUART_DATA_PARITYE (1 << 14) /* Bit 14: The current received dataword contained in DATA[R9:R0] was received with a parity error */
#define LPUART_DATA_NOISY (1 << 15) /* Bit 15: The current received dataword contained in DATA[R9:R0] was received with noise */
/* Bits 16-31: This field is reserved */
/* Low Power UART Match Address Register */
#define LPUART_MATCH_MA1_SHIFT (0) /* Bits 0-9: Match Address 1 */
#define LPUART_MATCH_MA1_MASK (0x3ff << LPUART_MATCH_MA1_SHIFT)
/* Bits 10-15: Reserved */
#define LPUART_MATCH_MA2_SHIFT (16) /* Bits 16-25: Match Address 2 */
#define LPUART_MATCH_MA2_MASK (0x3ff << LPUART_MATCH_MA2_SHIFT)
/* Bits 26-31: Reserved */
/* Low Power UART Modem IrDA Register */
#define LPUART_MODIR_TXCTSE (1 << 0) /* Bit 0: Transmitter clear-to-send enable */
#define LPUART_MODIR_TXRTSE (1 << 1) /* Bit 1: Transmitter request-to-send enable */
#define LPUART_MODIR_TXRTSPOL (1 << 2) /* Bit 2: Transmitter request-to-send polarity */
#define LPUART_MODIR_RXRTSE (1 << 3) /* Bit 3: Receiver request-to-send enable */
#define LPUART_MODIR_TXCTSC (1 << 4) /* Bit 4: Transmit CTS Configuration */
#define LPUART_MODIR_TXCTSSRC (1 << 5) /* Bit 5: Transmit CTS Source */
/* Bits 6-15: Reserved */
#define LPUART_MODIR_TNP_SHIFT (16) /* Bits 16-17: Transmitter narrow pulse */
#define LPUART_MODIR_TNP_MASK (3 << LPUART_MODIR_TNP_SHIFT)
# define LPUART_MODIR_TNP(n) (((n)-1) << LPUART_MODIR_TNP_SHIFT) /* n=1-4 */
#define LPUART_MODIR_IREN (1 << 18) /* Bit 18: Infrared enable */
/* Bits 19-31: Reserved */
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPUART_H */
arch/arm/src/kinetis/chip/kinetis_sim.h
+14 -4
View File
@@ -1140,19 +1140,25 @@
/* System Clock Divider Register 2 */
#if defined(KINETIS_SIM_HAS_CLKDIV2_USBFRAC)
# define SIM_CLKDIV2_USBFRAC (1 << 0) /* Bit 0: USB clock divider fraction */
# define SIM_CLKDIV2_USBFRAC_SHIFT (0) /* Bit 0: USB clock divider fraction */
# define SIM_CLKDIV2_USBFRAC_MASK (1 << SIM_CLKDIV2_USBFRAC_SHIFT)
# define SIM_CLKDIV2_USBFRAC(n) ((((n)-1) & 1) << SIM_CLKDIV2_USBFRAC_SHIFT) /* n=1..2 */
#endif
#if defined(KINETIS_SIM_HAS_CLKDIV2_USBDIV)
# define SIM_CLKDIV2_USBDIV_SHIFT (1) /* Bits 1-3: USB clock divider divisor */
# define SIM_CLKDIV2_USBDIV_MASK (7 << SIM_CLKDIV2_USBDIV_SHIFT)
# define SIM_CLKDIV2_USBDIV(n) ((((n)-1) & 7) << SIM_CLKDIV2_USBDIV_SHIFT) /* n=1..8 */
#endif
/* Bits 4-7: Reserved */
#if defined(KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC)
# define SIM_CLKDIV2_USBHSFRAC (1 << 8) /* Bit 8: USB HS clock divider fraction */
# define SIM_CLKDIV2_USBHSFRAC_SHIFT (8) /* Bit 8: USB HS clock divider fraction */
# define SIM_CLKDIV2_USBHSFRAC_MASK (1 << SIM_CLKDIV2_USBHSFRAC_SHIFT)
# define SIM_CLKDIV2_USBHSFRAC(n) ((((n)-1) & 1) << SIM_CLKDIV2_USBHSFRAC_SHIFT) /* n=1..2 */
#endif
#if defined(KINETIS_SIM_HAS_CLKDIV2_USBHSDIV)
# define SIM_CLKDIV2_USBHSDIV_SHIFT (9) /* Bits 1-3: USB HS clock divider divisor */
# define SIM_CLKDIV2_USBHSDIV_MASK (7 << SIM_CLKDIV2_USBHSDIV_SHIFT)
# define SIM_CLKDIV2_USBHSDIV(n) ((((n)-1) & 7) << SIM_CLKDIV2_USBHSDIV_SHIFT) /* n=1..8 */
#endif
#if defined(KINETIS_SIM_HAS_CLKDIV2_I2SFRAC)
# define SIM_CLKDIV2_I2SFRAC_SHIFT (8) /* Bits 8-15: I2S clock divider fraction */
@@ -1259,7 +1265,9 @@
/* System Clock Divider Register 3 */
# if defined(KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC)
# define SIM_CLKDIV3_PLLFLLFRAC (1 << 0) /* Bit 0: PLLFLL clock divider fraction */
# define SIM_CLKDIV3_PLLFLLFRAC_SHIFT (0) /* Bit 0: PLLFLL clock divider fraction */
# define SIM_CLKDIV3_PLLFLLFRAC_MASK (1 << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)
# define SIM_CLKDIV3_PLLFLLFRAC(n) ((((n)-1) & 1) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT) /* n=1..2 */
# endif
# if defined(KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV)
# define SIM_CLKDIV3_PLLFLLDIV_SHIFT (1) /* Bits 1-3: PLLFLL clock divider divisor */
@@ -1271,7 +1279,9 @@
/* System Clock Divider Register 4 */
# if defined(KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC)
# define SIM_CLKDIV4_TRACEFRAC (1 << 0) /* Bit 0: Trace clock divider fraction */
# define SIM_CLKDIV4_TRACEFRAC_SHIFTS (0) /* Bit 0: Trace clock divider fraction */
# define SIM_CLKDIV4_TRACEFRAC_MASK (1 << SIM_CLKDIV4_TRACEFRAC_SHIFTS)
# define SIM_CLKDIV4_TRACEFRAC(n) ((((n)-1) & 1) << SIM_CLKDIV4_TRACEFRAC_SHIFTS) /* n=1..2 */
# endif
# if defined(KINETIS_SIM_HAS_CLKDIV4_TRACEDIV)
# define SIM_CLKDIV4_TRACEDIV_SHIFT (1) /* Bits 1-3: Trace clock divider divisor */
arch/arm/src/kinetis/chip/kinetis_uart.h
+4 -3
View File
@@ -1,8 +1,9 @@
/************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_uart.h
*
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane<david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -293,7 +294,7 @@
#define UART_BDH_SBR_SHIFT (0) /* Bits 0-4: MS Bits 8-13 of the UART Baud Rate Bits */
#define UART_BDH_SBR_MASK (31 << UART_BDH_SBR_SHIFT)
/* Bit 5: Reserved */
#define UART_BDH_SBNS (1 << 5) /* Bit 5: Stop Bit Number Select */
#define UART_BDH_RXEDGIE (1 << 6) /* Bit 6: RxD Input Active Edge Interrupt Enable */
#define UART_BDH_LBKDIE (1 << 7) /* Bit 7: LIN Break Detect Interrupt Enable */
arch/arm/src/kinetis/kinetis.h
+31 -3
View File
@@ -1,8 +1,9 @@
/************************************************************************************
* arch/arm/src/kinetis/kinetis.h
*
* Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright (C) 2011, 2013, 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -364,6 +365,18 @@ void kinetis_lowsetup(void);
void kinetis_uartreset(uintptr_t uart_base);
#endif
/****************************************************************************
* Name: kinetis_lpuartreset
*
* Description:
* Reset a UART.
*
****************************************************************************/
#ifdef HAVE_LPUART_DEVICE
void kinetis_lpuartreset(uintptr_t uart_base);
#endif
/****************************************************************************
* Name: kinetis_uartconfigure
*
@@ -374,7 +387,22 @@ void kinetis_uartreset(uintptr_t uart_base);
#ifdef HAVE_UART_DEVICE
void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock,
unsigned int parity, unsigned int nbits);
unsigned int parity, unsigned int nbits,
unsigned int stop2);
#endif
/****************************************************************************
* Name: kinetis_lpuartconfigure
*
* Description:
* Configure a UART as a RS-232 UART.
*
****************************************************************************/
#ifdef HAVE_LPUART_DEVICE
void kinetis_lpuartconfigure(uintptr_t uart_base, uint32_t baud, uint32_t clock,
unsigned int parity, unsigned int nbits,
unsigned int stop2);
#endif
/************************************************************************************
arch/arm/src/kinetis/kinetis_clockconfig.c
+25 -2
View File
@@ -2,7 +2,8 @@
* arch/arm/src/kinetis/kinetis_clockconfig.c
*
* Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane<david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -192,7 +193,8 @@ static inline void kinesis_portclocks(void)
void kinetis_pllconfig(void)
{
#if defined(SIM_SCGC4_LLWU)
#if defined(SIM_SCGC4_LLWU) || defined(BOARD_SOPT2_PLLFLLSEL) || \
defined(BOARD_SIM_CLKDIV3_FREQ)
uint32_t regval32;
#endif
uint8_t regval8;
@@ -346,6 +348,27 @@ void kinetis_pllconfig(void)
while ((getreg8(KINETIS_MCG_S) & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
/* We are now running in PLL Engaged External (PEE) mode. */
/* Do we have BOARD_SOPT2_PLLFLLSEL */
#if defined(BOARD_SOPT2_PLLFLLSEL)
/* Set up the SOPT2[PLLFLLSEL] */
regval32 = getreg32(KINETIS_SIM_SOPT2);
regval32 &= ~SIM_SOPT2_PLLFLLSEL_MASK;
regval32 |= BOARD_SOPT2_PLLFLLSEL;
putreg32(regval32, KINETIS_SIM_SOPT2);
#endif
#if defined(BOARD_SIM_CLKDIV3_FREQ)
/* Set up the SIM_CLKDIV3 [PLLFLLFRAC, PLLFLLDIV] */
regval32 = getreg32(KINETIS_SIM_CLKDIV3);
regval32 &= ~(SIM_CLKDIV3_PLLFLLFRAC_MASK | SIM_CLKDIV3_PLLFLLDIV_MASK);
regval32 |= (SIM_CLKDIV3_PLLFLLFRAC(BOARD_SIM_CLKDIV3_PLLFLLFRAC) |
SIM_CLKDIV3_PLLFLLDIV(BOARD_SIM_CLKDIV3_PLLFLLDIV));
putreg32(regval32, KINETIS_SIM_CLKDIV3);
#endif
}
/****************************************************************************
arch/arm/src/kinetis/kinetis_config.h
+124 -53
View File
@@ -1,8 +1,9 @@
/************************************************************************************
* arch/arm/src/kinetis/kinetis_config.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright (C) 2011, 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane<david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -50,7 +51,11 @@
************************************************************************************/
/* Configuration *********************************************************************/
/* Make that no unsupported UARTs are enabled */
/* Make sure that no unsupported UARTs are enabled */
#ifndef KINETIS_NLPUART
# define KINETIS_NLPUART 0
#endif
#ifndef KINETIS_NISO7816
# define KINETIS_NISO7816 0
@@ -75,69 +80,127 @@
# endif
#endif
#if KINETIS_NLPUART < 1
# undef CONFIG_KINETIS_LPUART0
#endif
/* Are any UARTs enabled? */
#undef HAVE_UART_DEVICE
#if defined(CONFIG_KINETIS_UART0) || defined(CONFIG_KINETIS_UART1) || \
defined(CONFIG_KINETIS_UART2) || defined(CONFIG_KINETIS_UART3) || \
defined(CONFIG_KINETIS_UART4) || defined(CONFIG_KINETIS_UART5)
defined(CONFIG_KINETIS_UART4) || defined(CONFIG_KINETIS_UART5) || \
defined(CONFIG_KINETIS_LPUART0)
# define HAVE_UART_DEVICE 1
#endif
#undef HAVE_LPUART_DEVICE
#if defined(CONFIG_KINETIS_LPUART0)
# define HAVE_LPUART_DEVICE 1
#endif
/* Is there a serial console? There should be at most one defined. It could be on
* any UARTn, n=0,1,2,3,4,5
*/
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART0)
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART1)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART2)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART3)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART4)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART5)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#undef HAVE_UART_CONSOLE
#undef HAVE_LPUART_CONSOLE
#if defined(CONFIG_CONSOLE_SYSLOG)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
#else
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef HAVE_SERIAL_CONSOLE
# if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART0)
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# define HAVE_UART_CONSOLE 1
# elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART1)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# define HAVE_UART_CONSOLE 1
# elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART2)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# define HAVE_UART_CONSOLE 1
# elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART3)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# define HAVE_UART_CONSOLE 1
# elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART4)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# define HAVE_UART_CONSOLE 1
# elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_UART5)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# define HAVE_UART_CONSOLE 1
# elif defined(CONFIG_LPUART0_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_LPUART0)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
# elif defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_KINETIS_LPUART1)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# define HAVE_LPUART_CONSOLE 1
# else
# ifdef CONFIG_DEV_CONSOLE
# warning "No valid CONFIG_[LP]UART[n]_SERIAL_CONSOLE Setting"
# endif
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_LPUART0_SERIAL_CONSOLE
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# endif
#endif
/* Check UART flow control (Not yet supported) */
@@ -148,6 +211,8 @@
# undef CONFIG_UART3_FLOWCONTROL
# undef CONFIG_UART4_FLOWCONTROL
# undef CONFIG_UART5_FLOWCONTROL
# undef CONFIG_LPUART0_FLOWCONTROL
# undef CONFIG_LPUART1_FLOWCONTROL
/* UART FIFO support is not fully implemented.
*
@@ -183,6 +248,12 @@
#ifndef CONFIG_KINETIS_UART5PRIO
# define CONFIG_KINETIS_UART5PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
#ifndef CONFIG_KINETIS_LPUART0PRIO
# define CONFIG_KINETIS_LPUART0PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
#ifndef CONFIG_KINETIS_LPUART1PRIO
# define CONFIG_KINETIS_LPUART1PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
/* Ethernet controller configuration */
arch/arm/src/kinetis/kinetis_lowputc.c
+362 -86
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/kinetis/kinetis_lpserial.c
+901
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/kinetis/kinetis_serial.c
+15 -7
View File
@@ -1,8 +1,9 @@
/****************************************************************************
* arch/mips/src/kinetis/kinetis_serial.c
*
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright (C) 2011-2012, 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -240,6 +241,7 @@ struct up_dev_s
uint8_t ie; /* Interrupts enabled */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (8 or 9) */
uint8_t stop2; /* Use 2 stop bits */
};
/****************************************************************************
@@ -334,6 +336,7 @@ static struct up_dev_s g_uart0priv =
.irqprio = CONFIG_KINETIS_UART0PRIO,
.parity = CONFIG_UART0_PARITY,
.bits = CONFIG_UART0_BITS,
.stop2 = CONFIG_UART0_2STOP,
};
static uart_dev_t g_uart0port =
@@ -368,6 +371,7 @@ static struct up_dev_s g_uart1priv =
.irqprio = CONFIG_KINETIS_UART1PRIO,
.parity = CONFIG_UART1_PARITY,
.bits = CONFIG_UART1_BITS,
.stop2 = CONFIG_UART1_2STOP,
};
static uart_dev_t g_uart1port =
@@ -402,6 +406,7 @@ static struct up_dev_s g_uart2priv =
.irqprio = CONFIG_KINETIS_UART2PRIO,
.parity = CONFIG_UART2_PARITY,
.bits = CONFIG_UART2_BITS,
.stop2 = CONFIG_UART2_2STOP,
};
static uart_dev_t g_uart2port =
@@ -436,6 +441,7 @@ static struct up_dev_s g_uart3priv =
.irqprio = CONFIG_KINETIS_UART3PRIO,
.parity = CONFIG_UART3_PARITY,
.bits = CONFIG_UART3_BITS,
.stop2 = CONFIG_UART3_2STOP,
};
static uart_dev_t g_uart3port =
@@ -470,6 +476,7 @@ static struct up_dev_s g_uart4priv =
.irqprio = CONFIG_KINETIS_UART4PRIO,
.parity = CONFIG_UART4_PARITY,
.bits = CONFIG_UART4_BITS,
.stop2 = CONFIG_UART4_2STOP,
};
static uart_dev_t g_uart4port =
@@ -504,6 +511,7 @@ static struct up_dev_s g_uart5priv =
.irqprio = CONFIG_KINETIS_UART5PRIO,
.parity = CONFIG_UART5_PARITY,
.bits = CONFIG_UART5_BITS,
.stop2 = CONFIG_UART5_2STOP,
};
static uart_dev_t g_uart5port =
@@ -615,7 +623,7 @@ static int up_setup(struct uart_dev_s *dev)
/* Configure the UART as an RS-232 UART */
kinetis_uartconfigure(priv->uartbase, priv->baud, priv->clock,
priv->parity, priv->bits);
priv->parity, priv->bits, priv->stop2);
#endif
/* Make sure that all interrupts are disabled */
@@ -1256,7 +1264,7 @@ void up_earlyserialinit(void)
/* Configuration whichever one is the console */
#ifdef HAVE_SERIAL_CONSOLE
#ifdef HAVE_UART_CONSOLE
CONSOLE_DEV.isconsole = true;
up_setup(&CONSOLE_DEV);
#endif
@@ -1275,7 +1283,7 @@ void up_serialinit(void)
{
/* Register the console */
#ifdef HAVE_SERIAL_CONSOLE
#ifdef HAVE_UART_CONSOLE
(void)uart_register("/dev/console", &CONSOLE_DEV);
#endif
@@ -1309,7 +1317,7 @@ void up_serialinit(void)
int up_putc(int ch)
{
#ifdef HAVE_SERIAL_CONSOLE
#ifdef HAVE_UART_CONSOLE
struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv;
uint8_t ie;
@@ -1342,7 +1350,7 @@ int up_putc(int ch)
int up_putc(int ch)
{
#ifdef HAVE_SERIAL_CONSOLE
#ifdef HAVE_UART_CONSOLE
/* Check for LF */
if (ch == '\n')
configs/freedom-k66f/include/board.h
+55 -2
View File
@@ -42,11 +42,12 @@
************************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
@@ -62,7 +63,7 @@
*
*/
#define BOARD_EXTAL_LP 1
#define BOARD_EXTAL_LP 1
#define BOARD_EXTAL_FREQ 12000000 /* 12MHz Oscillator */
#define BOARD_XTAL32_FREQ 32768 /* 32KHz RTC Oscillator */
@@ -103,6 +104,46 @@
#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3)
#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4)
/* Use BOARD_MCG_FREQ as the output SIM_SOPT2 MUX selected by
* SIM_SOPT2[PLLFLLSEL]
*/
#define BOARD_SOPT2_PLLFLLSEL SIM_SOPT2_PLLFLLSEL_MCGPLLCLK
#define BOARD_SOPT2_FREQ BOARD_MCG_FREQ
/* N.B. The above BOARD_SOPT2_FREQ precludes use of USB with a 12 Mhz Xtal
* Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]
* SIM_CLKDIV2_FREQ = BOARD_SOPT2_FREQ × [ (USBFRAC+1) / (USBDIV+1) ]
* 48Mhz = 168Mhz X [(1 + 1) / (6 + 1)]
* 48Mhz = 168Mhz / (6 + 1) * (1 + 1)
*/
#if (BOARD_MCG_FREQ == 168000000L)
# define BOARD_SIM_CLKDIV2_USBFRAC 2
# define BOARD_SIM_CLKDIV2_USBDIV 7
# define BOARD_SIM_CLKDIV2_FREQ (BOARD_SOPT2_FREQ / \
BOARD_SIM_CLKDIV2_USBDIV * \
BOARD_SIM_CLKDIV2_USBFRAC)
#endif
/* Divider output clock = Divider input clock * ((PLLFLLFRAC+1)/(PLLFLLDIV+1))
* SIM_CLKDIV3_FREQ = BOARD_SOPT2_FREQ × [ (PLLFLLFRAC+1) / (PLLFLLDIV+1)]
* 90 Mhz = 180 Mhz X [(0 + 1) / (1 + 1)]
* 90 Mhz = 180 Mhz / (1 + 1) * (0 + 1)
*/
#define BOARD_SIM_CLKDIV3_PLLFLLFRAC 1
#define BOARD_SIM_CLKDIV3_PLLFLLDIV 2
#define BOARD_SIM_CLKDIV3_FREQ (BOARD_SOPT2_FREQ / \
BOARD_SIM_CLKDIV3_PLLFLLDIV * \
BOARD_SIM_CLKDIV3_PLLFLLFRAC)
#define BOARD_LPUART0_CLKSRC SIM_SOPT2_LPUARTSRC_MCGCLK
#define BOARD_LPUART0_FREQ BOARD_SIM_CLKDIV3_FREQ
#define BOARD_TPM_CLKSRC SIM_SOPT2_TPMSRC_MCGCLK
#define BOARD_TPM_FREQ BOARD_SIM_CLKDIV3_FREQ
/* SDHC clocking ********************************************************************/
/* SDCLK configurations corresponding to various modes of operation. Formula is:
@@ -276,6 +317,18 @@
#define PIN_UART4_RX PIN_UART4_RX_1
#define PIN_UART4_TX PIN_UART4_TX_1
/* LPUART
*
* J1 Pin Name K66 Name
* -------- ------------ ------ ---------
* 7 I2S_RX_BCLK PTE9 LPUART0_RX
* 11 I2S_RX_FS PTE8 LPUART0_TX
* -------- ----- ------ ---------
*/
#define PIN_LPUART0_RX PIN_LPUART0_RX_1
#define PIN_LPUART0_TX PIN_LPUART0_TX_1
/* I2C INERTIAL SENSOR (Gyroscope)
*
* Pin Name K66 Name