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arch/arm/src/lpc54xx: DMA driver is code compelete. Untested and still needs more review.
This commit is contained in:
Gregory Nutt
@@ -48,6 +48,7 @@
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********************************************************************************************/
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#define LPC54_DMA_NCHANNELS 30 /* Channels 0..29 */
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#define LPC54_DMA_MAXXFRS 1024 /* Maximum number of transfers per DMA */
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/* Register offsets *************************************************************************/
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@@ -201,4 +202,77 @@
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#define DMA_XFERCFG_XFERCOUNT_MASK (0x3ff << DMA_XFERCFG_XFERCOUNT_SHIFT)
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# define DMA_XFERCFG_XFERCOUNT(n) ((uint32_t)((n)-1) << DMA_XFERCFG_XFERCOUNT_SHIFT)
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/* DMA requests *****************************************************************************/
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/* DMA requests are directly connected to the peripherals. Each channel supports one DMA
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* request line and one trigger input. Some DMA requests allow a selection of requests
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* sources. DMA triggers are selected from many possible input sources.
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*/
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/* Peripheral request inputs to DMA channel. For DMA channel 'n', the corresponding DMA
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* trigger input is provided by the setting of the INPUT MUX register DMA_ITRIG_INMUXn
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*/
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#define FLEXCOMM0_RX_DMACHAN (0) /* Flexcomm Interface 0 RX */
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#define FLEXCOMM0_I2CSLAVE_DMACHAN (0) /* Flexcomm Interface 0 I2C Slave */
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#define FLEXCOMM0_TX_DMACHAN (1) /* Flexcomm Interface 0 TX */
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#define FLEXCOMM0_I2CMASTER_DMACHAN (1) /* Flexcomm Interface 0 I2C Master */
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#define FLEXCOMM1_RX_DMACHAN (2) /* Flexcomm Interface 1 RX */
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#define FLEXCOMM1_I2CSLAVE_DMACHAN (2) /* Flexcomm Interface 1 I2C Slave */
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#define FLEXCOMM1_TX_DMACHAN (3) /* Flexcomm Interface 1 TX */
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#define FLEXCOMM1_I2CMASTER_DMACHAN (3) /* Flexcomm Interface 1 I2C Master */
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#define FLEXCOMM2_RX_DMACHAN (4) /* Flexcomm Interface 2 RX */
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#define FLEXCOMM2_I2CSLAVE_DMACHAN (4) /* Flexcomm Interface 2 I2C Slave */
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#define FLEXCOMM2_TX_DMACHAN (5) /* Flexcomm Interface 2 TX */
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#define FLEXCOMM2_I2CMASTER_DMACHAN (5) /* Flexcomm Interface 2 I2C Master */
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#define FLEXCOMM3_RX_DMACHAN (6) /* Flexcomm Interface 3 RX */
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#define FLEXCOMM3_I2CSLAVE_DMACHAN (6) /* Flexcomm Interface 3 I2C Slave */
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#define FLEXCOMM3_TX_DMACHAN (7) /* Flexcomm Interface 3 TX */
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#define FLEXCOMM3_I2CMASTER_DMACHAN (7) /* Flexcomm Interface 3 I2C Master */
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#define FLEXCOMM4_RX_DMACHAN (8) /* Flexcomm Interface 4 RX */
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#define FLEXCOMM4_I2CSLAVE_DMACHAN (8) /* Flexcomm Interface 4 I2C Slave */
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#define FLEXCOMM4_TX_DMACHAN (9) /* Flexcomm Interface 4 TX */
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#define FLEXCOMM4_I2CMASTER_DMACHAN (9) /* Flexcomm Interface 4 I2C Master */
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#define FLEXCOMM5_RX_DMACHAN (10) /* Flexcomm Interface 5 RX */
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#define FLEXCOMM5_I2CSLAVE_DMACHAN (10) /* Flexcomm Interface 5 I2C Slave */
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#define FLEXCOMM5_TX_DMACHAN (11) /* Flexcomm Interface 5 TX */
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#define FLEXCOMM5_I2CMASTER_DMACHAN (11) /* Flexcomm Interface 5 I2C Master */
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#define FLEXCOMM6_RX_DMACHAN (12) /* Flexcomm Interface 6 RX */
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#define FLEXCOMM6_I2CSLAVE_DMACHAN (12) /* Flexcomm Interface 6 I2C Slave */
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#define FLEXCOMM6_TX_DMACHAN (13) /* Flexcomm Interface 6 TX */
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#define FLEXCOMM6_I2CMASTER_DMACHAN (13) /* Flexcomm Interface 6 I2C Master */
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#define FLEXCOMM7_RX_DMACHAN (14) /* Flexcomm Interface 7 RX */
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#define FLEXCOMM7_I2CSLAVE_DMACHAN (14) /* Flexcomm Interface 7 I2C Slave */
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#define FLEXCOMM7_TX_DMACHAN (15) /* Flexcomm Interface 7 TX */
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#define FLEXCOMM7_I2CMASTER_DMACHAN (15) /* Flexcomm Interface 7 I2C Master */
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#define DMIC0_DMACHAN (16) /* DMIC0 */
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#define DMIC1_DMACHAN (17) /* DMIC1 */
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#define SPIFI_DMACHAN (18) /* SPIFI */
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#define SHA_DMACHAN (19) /* SHA */
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#define FLEXCOMM8_RX_DMACHAN (20) /* Flexcomm Interface 8 RX */
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#define FLEXCOMM8_I2CSLAVE_DMACHAN (20) /* Flexcomm Interface 8 I2C Slave */
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#define FLEXCOMM8_TX_DMACHAN (21) /* Flexcomm Interface 8 TX */
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#define FLEXCOMM8_I2CMASTER_DMACHAN (21) /* Flexcomm Interface 8 I2C Slave (?) */
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#define FLEXCOMM9_RX_DMACHAN (22) /* Flexcomm Interface 9 RX */
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#define FLEXCOMM9_I2CSLAVE_DMACHAN (22) /* Flexcomm Interface 9 I2C Slave */
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#define FLEXCOMM9_TX_DMACHAN (23) /* Flexcomm Interface 9 TX */
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#define FLEXCOMM9_I2CMASTER_DMACHAN (23) /* Flexcomm Interface 9 I2C Slave (?) */
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#define SMARTCARD0_RX_DMACHAN (24) /* SMARTCARD0_RX */
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#define SMARTCARD0_TX_DMACHAN (25) /* SMARTCARD0_TX */
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#define SMARTCARD1_RX_DMACHAN (26) /* SMARTCARD1_RX */
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#define SMARTCARD1_TX_DMACHAN (27) /* SMARTCARD1_TX */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/* DMA channel descriptor */
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struct lpc54_dmachan_desc_s
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{
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uint32_t reserved;
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uint32_t srcend; /* Source data end address */
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uint32_t dstend; /* Destination end address */
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uint32_t link; /* Link to next descriptor */
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};
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#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_DMA_H */
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@@ -214,8 +214,32 @@
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/* Trigger select register for DMA channel 0-29 */
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#define ITRIG_INMUX_ADC0A (0) /* ADC0 Sequence A interrupt */
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#define ITRIG_INMUX_ADC0B (1) /* ADC0 Sequence B interrupt */
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#define ITRIG_INMUX_SCT0DMA0 (2) /* SCT0 DMA request 0 */
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#define ITRIG_INMUX_SCT0DMA1 (3) /* SCT0 DMA request 1 */
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#define ITRIG_INMUX_PININT0 (4) /* Pin interrupt 0 */
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#define ITRIG_INMUX_PININT1 (5) /* Pin interrupt 1 */
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#define ITRIG_INMUX_PININT2 (6) /* Pin interrupt 2 */
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#define ITRIG_INMUX_PININT3 (7) /* Pin interrupt 3 */
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#define ITRIG_INMUX_CTIMER0MAT0 (8) /* Timer CTIMER0 Match 0 */
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#define ITRIG_INMUX_CTIMER0MAT1 (9) /* Timer CTIMER0 Match 1 */
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#define ITRIG_INMUX_CTIMER1MAT0 (10) /* Timer CTIMER1 Match 0 */
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#define ITRIG_INMUX_CTIMER1MAT1 (11) /* Timer CTIMER1 Match 1 */
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#define ITRIG_INMUX_CTIMER2MAT0 (12) /* Timer CTIMER2 Match 0 */
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#define ITRIG_INMUX_CTIMER2MAT1 (13) /* Timer CTIMER2 Match 1 */
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#define ITRIG_INMUX_CTIMER3MAT0 (14) /* Timer CTIMER3 Match 0 */
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#define ITRIG_INMUX_CTIMER3MAT1 (15) /* Timer CTIMER3 Match 1 */
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#define ITRIG_INMUX_CTIMER4MAT0 (16) /* Timer CTIMER4 Match 0 */
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#define ITRIG_INMUX_CTIMER4MAT1 (17) /* Timer CTIMER4 Match 1 */
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#define ITRIG_INMUX_DMAMUX0 (18) /* DMA output trigger mux 0 */
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#define ITRIG_INMUX_DMAMUX1 (19) /* DMA output trigger mux 1 */
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#define ITRIG_INMUX_DMAMUX2 (20) /* DMA output trigger mux 2 */
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#define ITRIG_INMUX_DMAMUX3 (21) /* DMA output trigger mux 3 */
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#define MUX_DMA_ITRIG_INMUX_SHIFT (0) /* Bit 0-4: Trigger input number for DMA channel n (n = 0 to 29) */
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#define MUX_DMA_ITRIG_INMUX_MASK (31 << MUX_DMA_ITRIG_INMUX_SHIFT)
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# define MUX_DMA_ITRIG_INMUX(n) ((uint32_t)(n) << MUX_DMA_ITRIG_INMUX_SHIFT)
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# define MUX_DMA_ITRIG_INMUX_ADC0A (0 << MUX_DMA_ITRIG_INMUX_SHIFT) /* ADC0 Sequence A interrupt */
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# define MUX_DMA_ITRIG_INMUX_ADC0B (1 << MUX_DMA_ITRIG_INMUX_SHIFT) /* ADC0 Sequence B interrupt */
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# define MUX_DMA_ITRIG_INMUX_SCT0DMA0 (2 << MUX_DMA_ITRIG_INMUX_SHIFT) /* SCT0 DMA request 0 */
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+216
-222
File diff suppressed because it is too large
Load Diff
@@ -55,8 +55,7 @@
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#ifndef __ASSEMBLY__
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typedef FAR void *DMA_HANDLE;
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typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
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typedef void (*dma_callback_t)(int ch, void *arg, int result);
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/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
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@@ -116,46 +115,32 @@ extern "C"
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****************************************************************************/
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/****************************************************************************
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* Name: lpc54_dmachannel
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*
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* Description:
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* Allocate a DMA channel. This function sets aside a DMA channel and
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* gives the caller exclusive access to the DMA channel.
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*
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* Returned Value:
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* One success, this function returns a non-NULL, void* DMA channel
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* handle. NULL is returned on any failure. This function can fail only
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* if no DMA channel is available.
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*
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****************************************************************************/
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DMA_HANDLE lpc54_dmachannel(void);
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/****************************************************************************
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* Name: lpc54_dmafree
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*
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* Description:
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* Release a DMA channel. NOTE: The 'handle' used in this argument must
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* NEVER be used again until lpc54_dmachannel() is called again to re-gain
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* a valid handle.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void lpc54_dmafree(DMA_HANDLE handle);
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/****************************************************************************
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* Name: lpc54_dmasetup
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* Name: lpc54_dma_setup
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*
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* Description:
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* Configure DMA for one transfer.
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*
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* Input Parameters:
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* ch - DMA channel number
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* cfg - The content of the DMA channel configuration register. See
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* peripheral channel definitions in chip/lpc54_dma.h. The
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* caller must provide all fields: PERIPHREQEN, TRIGPOL,
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* TRIGTYPE, TRIGBURST, BURSTPOWER, SRCBURSTWRAP, DSTBURSTWRAP,
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* and CHPRIORITY.
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* xfrcfg - The content of the DMA channel configuration register. See
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* peripheral channel definitions in chip/lpc54_dma.h. The
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* caller must provide all fields: WIDTH, SRCINC, and DSTINC.\
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* All of fields are managed by the DMA driver
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* trigsrc - See input mux DMA trigger ITRIG_INMUX_* definitions in
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* chip/lpc54_inputmux.h.
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* srcaddr - Source address of the DMA transfer
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* dstaddr - Destination address of the DMA transfer
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* nbytes - Number of bytes to transfer
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*
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****************************************************************************/
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int lpc54_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
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uint32_t srcaddr, uint32_t destaddr, size_t nbytes);
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int lpc54_dma_setup(int ch, uint32_t cfg, uint32_t xfrcfg, uint8_t trigsrc,
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uintptr_t srcaddr, uintptr_t dstaddr, size_t nbytes);
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/****************************************************************************
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* Name: lpc54_dmastart
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@@ -165,7 +150,7 @@ int lpc54_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
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*
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****************************************************************************/
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int lpc54_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
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int lpc54_dmastart(int ch, dma_callback_t callback, void *arg);
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/****************************************************************************
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* Name: lpc54_dmastop
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@@ -177,7 +162,7 @@ int lpc54_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
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*
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****************************************************************************/
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void lpc54_dmastop(DMA_HANDLE handle);
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void lpc54_dmastop(int ch);
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/****************************************************************************
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* Name: lpc54_dmasample
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@@ -188,7 +173,7 @@ void lpc54_dmastop(DMA_HANDLE handle);
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****************************************************************************/
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#ifdef CONFIG_DEBUG_DMA
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void lpc54_dmasample(DMA_HANDLE handle, struct lpc54_dmaregs_s *regs);
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void lpc54_dmasample(int ch, struct lpc54_dmaregs_s *regs);
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#else
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# define lpc54_dmasample(handle,regs)
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#endif
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@@ -202,7 +187,7 @@ void lpc54_dmasample(DMA_HANDLE handle, struct lpc54_dmaregs_s *regs);
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****************************************************************************/
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#ifdef CONFIG_DEBUG_DMA
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void lpc54_dmadump(DMA_HANDLE handle, const struct lpc54_dmaregs_s *regs,
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void lpc54_dmadump(int ch, const struct lpc54_dmaregs_s *regs,
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const char *msg);
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#else
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# define lpc54_dmadump(handle,regs,msg)
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@@ -70,6 +70,7 @@ STATUS
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2017-12-23: SDMMC is still non-functional. The first DMA read of 512 bytes
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fails with a CRC error. Similar result if clock is reduced, if 1-bit bus
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is used, if DMA is disabled., if DEBUG output is disabled.
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2017-12-24: Added fragmentary DMA support. Much more still needed.
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There is still no support for the Accelerometer, SPIFI, Ethernet, or USB.
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There is a complete, but not-yet-functional SD card drirver. There is a
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