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arch/risc-v: Align prototype of riscv_exception with xcpt_t

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Thus we can attach it to irq handler without any cast.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi
2022-04-08 15:00:21 +08:00
committed by Xiang Xiao
parent c235c0fa43
commit 36bc8d2131
6 changed files with 11 additions and 7 deletions
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2
arch/risc-v/src/c906/c906_irq_dispatch.c
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@@ -58,7 +58,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
if (vector < RISCV_IRQ_ECALLU)
{
riscv_exception(irq, regs);
riscv_exception(irq, regs, NULL);
}
/* Firstly, check if the irq is machine external interrupt */

5
arch/risc-v/src/common/riscv_exception.c
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@@ -69,7 +69,7 @@ static const char *g_reasons_str[RISCV_MAX_EXCEPTION + 1] =
*
****************************************************************************/
void riscv_exception(uintptr_t mcause, uintptr_t *regs)
int riscv_exception(int mcause, void *regs, void *args)
{
uintptr_t cause = mcause & RISCV_IRQ_MASK;
@@ -87,5 +87,6 @@ void riscv_exception(uintptr_t mcause, uintptr_t *regs)
up_irq_save();
CURRENT_REGS = regs;
PANIC();
}
return 0;
}

2
arch/risc-v/src/common/riscv_internal.h
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@@ -286,7 +286,7 @@ void riscv_netinitialize(void);
/* Exception Handler ********************************************************/
uintptr_t *riscv_doirq(int irq, uintptr_t *regs);
void riscv_exception(uintptr_t mcause, uintptr_t *regs);
int riscv_exception(int mcause, void *regs, void *args);
int riscv_misaligned(int irq, void *context, void *arg);
/* Debug ********************************************************************/

3
arch/risc-v/src/k210/k210_irq_dispatch.c
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@@ -29,6 +29,7 @@
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <sys/types.h>
#include "riscv_internal.h"
#include "group/group.h"
@@ -58,7 +59,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
if (vector < RISCV_IRQ_ECALLU)
{
riscv_exception(irq, regs);
riscv_exception(irq, regs, NULL);
}
/* Firstly, check if the irq is machine external interrupt */

3
arch/risc-v/src/mpfs/mpfs_irq_dispatch.c
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@@ -29,6 +29,7 @@
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <sys/types.h>
#include "riscv_internal.h"
@@ -59,7 +60,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
vector == RISCV_IRQ_STOREPF ||
vector == RISCV_IRQ_RESERVED)
{
riscv_exception(irq, regs);
riscv_exception(irq, regs, NULL);
}
if ((vector & RISCV_IRQ_BIT) != 0)

3
arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c
View File

@@ -29,6 +29,7 @@
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <sys/types.h>
#include "riscv_internal.h"
#include "hardware/qemu_rv_memorymap.h"
@@ -59,7 +60,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
if (vector < RISCV_IRQ_ECALLM)
{
riscv_exception(irq, regs);
riscv_exception(irq, regs, NULL);
}
/* Firstly, check if the irq is machine external interrupt */