Merged nuttx/nuttx/master into master

2026-05-21 04:52:02 +08:00 · 2017-04-06 17:03:36 +09:00
parent eb5523d3a7 0de787b558
commit 34b9be8d01
145 changed files with 19088 additions and 1906 deletions
@@ -8,7 +8,7 @@
  <tr align="center" bgcolor="#e4e4e4">
    <td>
      <h1><big><font color="#3c34ec"><i>NuttShell (NSH)</i></font></big></h1>
-      <p>Last Updated: February 5, 2017</p>
+      <p>Last Updated: April 5, 2017</p>
    </td>
  </tr>
 </table>
@@ -2708,11 +2708,13 @@ nsh&gt;

 <p><b>Command Syntax:</b></p>
 <ul><pre>
-set &lt;name&gt; &lt;value&gt;
+set [{+|-}{e|x|xe|ex}] [&lt;name&gt; &lt;value&gt;]
 </pre></ul>
 <p>
  <b>Synopsis</b>.
-  Set the environment variable <code>&lt;name&gt;</code> to the string <code>&lt;value&gt;</code>.
+  Set the environment variable <code>&lt;name&gt;</code> to the string <code>&lt;value&gt;</code> and or set NSH
+  parser control options. For example,
+
  For example,
 </p>
 <ul><pre>
@@ -2724,6 +2726,51 @@ foovalue
 nsh&gt;
 </pre></ul>

+<p>
+    Set the 'exit on error control' and/or 'print a trace' of commands when parsing
+    scripts in NSH.  The settinngs are in effect from the point of exection, until
+    they are changed again, or in the case of the init script, the settings are
+    returned to the default settings when it exits. Included child scripts will run
+    with the parents settings and changes made in the child script will effect the
+    parent on return.
+</p>
+<p>
+    Use 'set -e' to enable and 'set +e' to disable (ignore) the exit condition on commands.
+    The default is -e. Errors cause script to exit.
+</p>
+<p>
+    Use 'set -x' to enable and 'set +x' to disable (silence) printing a trace of the script
+    commands as they are ececuted.
+    The default is +x. No printing of a trace of script commands as they are executed.
+
+</p>
+
+  Example 1 - no exit on command not found
+<ul><pre>
+    set +e
+    notacommand
+</pre></ul>
+
+  Example 2 - will exit on command not found
+<ul><pre>
+    set -e
+    notacommand
+</pre></ul>
+
+  Example 3 - will exit on command not found, and print a trace of the script commmands
+<ul><pre>
+    set -ex
+</pre></ul>
+
+  Example 4 - will exit on command not found, and print a trace of the script commmands
+              and set foobar to foovalue.
+<ul><pre>
+    set -ex foobar foovalue
+    nsh> echo $foobar
+    foovalue
+</pre></ul>
+
+
 <table width ="100%">
  <tr bgcolor="#e4e4e4">
  <td>
@@ -498,7 +498,7 @@ do_qconfig: dirlinks apps_preconfig

 qconfig: do_qconfig clean_context

-gconfig: dirlinks apps_preconfig
+do_gconfig: dirlinks apps_preconfig
 	$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-gconf Kconfig

 gconfig: do_gconfig clean_context
@@ -464,9 +464,9 @@ Notes about Header Files

    Certain header files, such as setjmp.h, stdarg.h, and math.h, may still
    be needed from your toolchain and your compiler may not, however, be able
-    to find these if you compile NuttX without using standard header file.
-    If that is the case, one solution is to copy those header file from
-    your toolchain into the NuttX include directory.
+    to find these if you compile NuttX without using standard header files
+    (ie., with -nostdinc).  If that is the case, one solution is to copy
+    those header file from your toolchain into the NuttX include directory.

  Duplicated Header Files.

@@ -64,12 +64,16 @@
 * STM32L15XCX -- 48-pins
 * STM32L15XRX -- 64-pins
 * STM32L15XVX -- 100-pins
+ * STM32L15XZX -- 144-pins
 *
 * STM32L15XX6 -- 32KB FLASH, 10KB SRAM, 4KB EEPROM
 * STM32L15XX8 -- 64KB FLASH, 10KB SRAM, 4KB EEPROM
 * STM32L15XXB -- 128KB FLASH, 16KB SRAM, 4KB EEPROM
 *
 * STM32L15XXC -- 256KB FLASH, 32KB SRAM, 8KB EEPROM (medium+ density)
+ *
+ * STM32L16XXD -- 384KB FLASH, 48KB SRAM, 12KB EEPROM (high density)
+ * STM32L16XXE -- 512KB FLASH, 80KB SRAM, 16KB EEPROM (high density)
 */

 #if defined(CONFIG_ARCH_CHIP_STM32L151C6) || defined(CONFIG_ARCH_CHIP_STM32L151C8) || \
@@ -320,7 +324,7 @@

 #elif defined(CONFIG_ARCH_CHIP_STM32L152RC)
 #  define CONFIG_STM32_STM32L15XX        1   /* STM32L151xx and STM32L152xx family */
-#  define CONFIG_STM32_ENERGYLITE        1   /* STM32L EnergyLite vamily */
+#  define CONFIG_STM32_ENERGYLITE        1   /* STM32L EnergyLite family */
 #  undef  CONFIG_STM32_STM32F10XX            /* STM32F10xxx family */
 #  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
                                              * and STM32L15xxx */
@@ -331,6 +335,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    0   /* No FSMC */
 #  define STM32_NATIM                    0   /* No advanced timers */
@@ -358,17 +363,18 @@

 #elif defined(CONFIG_ARCH_CHIP_STM32L162ZD)
 #  define CONFIG_STM32_STM32L15XX        1   /* STM32L151xx and STM32L152xx family */
-#  define CONFIG_STM32_ENERGYLITE        1   /* STM32L EnergyLite vamily */
+#  define CONFIG_STM32_ENERGYLITE        1   /* STM32L EnergyLite family */
 #  undef  CONFIG_STM32_STM32F10XX            /* STM32F10xxx family */
 #  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
                                              * and STM32L15xxx */
 #  undef  CONFIG_STM32_MEDIUMDENSITY         /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
 #  undef  CONFIG_STM32_MEDIUMPLUSDENSITY     /* STM32L15xxC w/ 32/256 Kbytes */
-#  define CONFIG_STM32_HIGHDENSITY       1   /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes, STM32L16x w/ 48/384 Kbytes. */
+#  define CONFIG_STM32_HIGHDENSITY       1   /* STM32L16xD w/ 48/384 Kbytes. */
 #  undef  CONFIG_STM32_VALUELINE             /* STM32F100x */
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    1   /* FSMC */
 #  define STM32_NATIM                    0   /* No advanced timers */
@@ -395,6 +401,48 @@
 #  define STM32_NRNG                     0   /* No random number generator (RNG) */
 #  define STM32_NDCMI                    0   /* No digital camera interface (DCMI) */

+#elif defined(CONFIG_ARCH_CHIP_STM32L162VE)
+#  define CONFIG_STM32_STM32L15XX        1   /* STM32L151xx and STM32L152xx family */
+#  define CONFIG_STM32_ENERGYLITE        1   /* STM32L EnergyLite family */
+#  undef  CONFIG_STM32_STM32F10XX            /* STM32F10xxx family */
+#  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes
+                                              * and STM32L15xxx */
+#  undef  CONFIG_STM32_MEDIUMDENSITY         /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+#  undef  CONFIG_STM32_MEDIUMPLUSDENSITY     /* STM32L15xxC w/ 32/256 Kbytes */
+#  define CONFIG_STM32_HIGHDENSITY       1   /* STM32L16xE w/ 80/512 Kbytes. */
+#  undef  CONFIG_STM32_VALUELINE             /* STM32F100x */
+#  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
+#  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
+#  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
+#  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
+#  define STM32_NFSMC                    0   /* No FSMC */
+#  define STM32_NATIM                    0   /* No advanced timers */
+#  define STM32_NGTIM                    4   /* 16-bit general timers TIM2-4 with DMA
+                                              * 32-bit general timer TIM5 with DMA */
+#  define STM32_NGTIMNDMA                3   /* 16-bit general timers TIM9-11 without DMA */
+#  define STM32_NBTIM                    2   /* 2 basic timers: TIM6, TIM7 with DMA */
+#  define STM32_NDMA                     2   /* DMA1, 12-channels */
+#  define STM32_NSPI                     3   /* SPI1-3 */
+#  define STM32_NI2S                     2   /* I2S1-2, overlapping with SPI2-3 */
+#  define STM32_NUSART                   5   /* USART1-3, UART4-5 */
+#  define STM32_NI2C                     2   /* I2C1-2 */
+#  define STM32_NCAN                     0   /* No CAN */
+#  define STM32_NSDIO                    0   /* No SDIO */
+#  define STM32_NLCD                     1   /* LCD 4x44, 8x40*/
+#  define STM32_NUSBOTG                  1   /* USB OTG FS/HS (only USB 2.0 device) */
+#  define STM32_NGPIO                    83  /* GPIOA-G,H */
+
+#  define STM32_NADC                     1   /* ADC1, up to 40-channels (medium+ and high density). See for more information RM0038 Reference manual  */
+#  define STM32_NDAC                     1   /* DAC 1, 2 channels. See for more information RM0038 Reference manual */
+                                             /* (2) Comparators */
+#  define STM32_NCAPSENSE                23  /* Capacitive sensing channels */
+#  define STM32_NCRC                     1   /* CRC */
+#  define STM32_NETHERNET                0   /* No ethernet */
+#  define STM32_NRNG                     0   /* No random number generator (RNG) */
+#  define STM32_NDCMI                    0   /* No digital camera interface (DCMI) */
+
+
 /* STM32 F100 Value Line ************************************************************/

 #elif defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \
@@ -562,7 +610,7 @@

 #elif defined(CONFIG_ARCH_CHIP_STM32F102CB)
 #  undef  CONFIG_STM32_STM32L15XX            /* STM32L151xx and STM32L152xx family */
-#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite vamily */
+#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite family */
 #  define CONFIG_STM32_STM32F10XX        1   /* STM32F10xx family */
 #  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
 #  define CONFIG_STM32_MEDIUMDENSITY     1   /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@@ -1129,7 +1177,7 @@

 #elif defined(CONFIG_ARCH_CHIP_STM32F302K6) || defined(CONFIG_ARCH_CHIP_STM32F302K8)
 #  undef  CONFIG_STM32_STM32L15XX            /* STM32L151xx and STM32L152xx family */
-#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite vamily */
+#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite family */
 #  undef  CONFIG_STM32_STM32F10XX            /* STM32F10xxx family */
 #  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
 #  undef  CONFIG_STM32_MEDIUMDENSITY         /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@@ -1668,7 +1716,7 @@

 #elif defined(CONFIG_ARCH_CHIP_STM32F373C8) || defined(CONFIG_ARCH_CHIP_STM32F373CB) || defined(CONFIG_ARCH_CHIP_STM32F373CC)
 #  undef  CONFIG_STM32_STM32L15XX            /* STM32L151xx and STM32L152xx family */
-#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite vamily */
+#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite family */
 #  undef  CONFIG_STM32_STM32F10XX            /* STM32F10xxx family */
 #  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
 #  undef  CONFIG_STM32_MEDIUMDENSITY         /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
@@ -59,16 +59,33 @@

 #if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT)
 #  if defined(CONFIG_STM32_STM32L15XX)
+#    if defined(CONFIG_STM32_HIGHDENSITY)

-/* The STM32 L15xx/L16xx can support up to 384KB of FLASH.  (In reality, supported
- * L15xx parts have no more than 128KB). The program memory block is divided into
- * 96 sectors of 4 Kbytes each, and each sector is further split up into 16 pages of
- * 256 bytes each. The sector is the write protection granularity. In total, the
+/* Different STM32L1xxx MCU version are now called by different 'categories' instead
+ * of 'densities'. Cat.5 MCU can have up to 512KB of FLASH. STM32L1xxx also have
+ * data EEPROM, up to 16KB.
+ */
+
+#      define STM32_FLASH_NPAGES        2048
+#      define STM32_FLASH_PAGESIZE      256
+#    else
+
+/* The STM32 (< Cat.5) L15xx/L16xx can support up to 384KB of FLASH. (In reality, most
+ * supported L15xx parts have no more than 128KB). The program memory block is divided
+ * into 96 sectors of 4 Kbytes each, and each sector is further split up into 16 pages
+ * of 256 bytes each. The sector is the write protection granularity. In total, the
 * program memory block contains 1536 pages.
 */

-#    define STM32_FLASH_NPAGES        1536
-#    define STM32_FLASH_PAGESIZE      256
+#      define STM32_FLASH_NPAGES        1536
+#      define STM32_FLASH_PAGESIZE      256
+#    endif
+
+     /* Maximum EEPROM size on Cat.5 MCU. TODO: this should be in chip config. */
+
+#    ifndef STM32_EEPROM_SIZE
+#      define STM32_EEPROM_SIZE         (16 * 1024)
+#    endif

 #  elif defined(CONFIG_STM32_LOWDENSITY)
 #    define STM32_FLASH_NPAGES        32
@@ -201,27 +218,40 @@
 #    elif defined(CONFIG_STM32_FLASH_CONFIG_I)
 #    endif
 #  endif
-#endif
+#endif /* !defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) */

 #ifdef STM32_FLASH_PAGESIZE
 #  define STM32_FLASH_SIZE            (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
-#endif /* def STM32_FLASH_PAGESIZE */
+#endif

 /* Register Offsets *****************************************************************/

-#define STM32_FLASH_ACR_OFFSET     0x0000
-#define STM32_FLASH_KEYR_OFFSET    0x0004
-#define STM32_FLASH_OPTKEYR_OFFSET 0x0008
-#define STM32_FLASH_SR_OFFSET      0x000c
-#define STM32_FLASH_CR_OFFSET      0x0010
-
-#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX)
-#  define STM32_FLASH_AR_OFFSET    0x0014
-#  define STM32_FLASH_OBR_OFFSET   0x001c
-#  define STM32_FLASH_WRPR_OFFSET  0x0020
-#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
-#  define STM32_FLASH_OPTCR_OFFSET 0x0014
+#define STM32_FLASH_ACR_OFFSET       0x0000
+#if defined(CONFIG_STM32_STM32L15XX)
+#  define STM32_FLASH_PECR_OFFSET    0x0004
+#  define STM32_FLASH_PDKEYR_OFFSET  0x0008
+#  define STM32_FLASH_PEKEYR_OFFSET  0x000c
+#  define STM32_FLASH_PRGKEYR_OFFSET 0x0010
+#  define STM32_FLASH_OPTKEYR_OFFSET 0x0014
+#  define STM32_FLASH_SR_OFFSET      0x0018
+#  define STM32_FLASH_OBR_OFFSET     0x001c
+#  define STM32_FLASH_WRPR1_OFFSET   0x0020
+#  define STM32_FLASH_WRPR2_OFFSET   0x0080
+#  define STM32_FLASH_WRPR3_OFFSET   0x0084
+#  define STM32_FLASH_WRPR4_OFFSET   0x0088
+#else
+#  define STM32_FLASH_KEYR_OFFSET    0x0004
+#  define STM32_FLASH_OPTKEYR_OFFSET 0x0008
+#  define STM32_FLASH_SR_OFFSET      0x000c
+#  define STM32_FLASH_CR_OFFSET      0x0010
+#  if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
+      defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX)
+#    define STM32_FLASH_AR_OFFSET    0x0014
+#    define STM32_FLASH_OBR_OFFSET   0x001c
+#    define STM32_FLASH_WRPR_OFFSET  0x0020
+#  elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#    define STM32_FLASH_OPTCR_OFFSET 0x0014
+#  endif
 #endif

 #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
@@ -230,22 +260,36 @@

 /* Register Addresses ***************************************************************/

-#define STM32_FLASH_ACR            (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
-#define STM32_FLASH_KEYR           (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
-#define STM32_FLASH_OPTKEYR        (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
-#define STM32_FLASH_SR             (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
-#define STM32_FLASH_CR             (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
+#define STM32_FLASH_ACR              (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
+#if defined(CONFIG_STM32_STM32L15XX)
+#  define STM32_FLASH_PECR           (STM32_FLASHIF_BASE+STM32_FLASH_PECR_OFFSET)
+#  define STM32_FLASH_PDKEYR         (STM32_FLASHIF_BASE+STM32_FLASH_PDKEYR_OFFSET)
+#  define STM32_FLASH_PEKEYR         (STM32_FLASHIF_BASE+STM32_FLASH_PEKEYR_OFFSET)
+#  define STM32_FLASH_PRGKEYR        (STM32_FLASHIF_BASE+STM32_FLASH_PRGKEYR_OFFSET)
+#  define STM32_FLASH_OPTKEYR        (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
+#  define STM32_FLASH_SR             (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
+#  define STM32_FLASH_OBR            (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
+#  define STM32_FLASH_WRPR1          (STM32_FLASHIF_BASE+STM32_FLASH_WRPR1_OFFSET)
+#  define STM32_FLASH_WRPR2          (STM32_FLASHIF_BASE+STM32_FLASH_WRPR2_OFFSET)
+#  define STM32_FLASH_WRPR3          (STM32_FLASHIF_BASE+STM32_FLASH_WRPR3_OFFSET)
+#  define STM32_FLASH_WRPR4          (STM32_FLASHIF_BASE+STM32_FLASH_WRPR4_OFFSET)
+#else
+#  define STM32_FLASH_KEYR           (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
+#  define STM32_FLASH_OPTKEYR        (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
+#  define STM32_FLASH_SR             (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
+#  define STM32_FLASH_CR             (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)

-#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX)
-#  define STM32_FLASH_AR           (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
-#  define STM32_FLASH_OBR          (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
-#  define STM32_FLASH_WRPR         (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
-#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
-#  define STM32_FLASH_OPTCR        (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET)
-#endif
-#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
-#  define STM32_FLASH_OPTCR1       (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET)
+#  if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
+      defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX)
+#    define STM32_FLASH_AR           (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
+#    define STM32_FLASH_OBR          (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
+#    define STM32_FLASH_WRPR         (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
+#  elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#    define STM32_FLASH_OPTCR        (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET)
+#  endif
+#  if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
+#    define STM32_FLASH_OPTCR1       (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET)
+#  endif
 #endif

 /* Register Bitfield Definitions ****************************************************/
@@ -303,6 +347,34 @@
 #  define FLASH_SR_PGPERR           (1 << 6)  /* Bit 6: Programming parallelism error */
 #  define FLASH_SR_PGSERR           (1 << 7)  /* Bit 7: Programming sequence error */
 #  define FLASH_SR_BSY              (1 << 16) /* Bit 16: Busy */
+#elif defined(CONFIG_STM32_STM32L15XX)
+#  define FLASH_SR_BSY              (1 << 0)  /* Bit 0: Busy */
+#  define FLASH_SR_EOP              (1 << 1)  /* Bit 1: End of operation */
+#  define FLASH_SR_ENDHV            (1 << 2)  /* Bit 2: End of high voltage */
+#  define FLASH_SR_READY            (1 << 3)  /* Bit 3: Flash memory module ready after low power mode */
+#  define FLASH_SR_WRPERR           (1 << 8)  /* Bit 8: Write protection error */
+#  define FLASH_SR_PGAERR           (1 << 9)  /* Bit 9: Programming alignment error  */
+#  define FLASH_SR_SIZERR           (1 << 10) /* Bit 10: Size error */
+#  define FLASH_SR_OPTVERR          (1 << 11) /* Bit 11: Option validity error */
+#  define FLASH_SR_OPTVERRUSR       (1 << 12) /* Bit 12: Option UserValidity Error */
+#  define FLASH_SR_RDERR            (1 << 13) /* Bit 13: Read protected error */
+#endif
+
+/* Program/Erase Control Register (PECR) */
+
+#if defined(CONFIG_STM32_STM32L15XX)
+#  define FLASH_PECR_PELOCK         (1 << 0)  /* Bit 0: PECR and data EEPROM lock */
+#  define FLASH_PECR_PRGLOCK        (1 << 1)  /* Bit 1: Program memory lock */
+#  define FLASH_PECR_OPTLOCK        (1 << 2)  /* Bit 2: Option bytes block lock */
+#  define FLASH_PECR_PROG           (1 << 3)  /* Bit 3: Program memory selection */
+#  define FLASH_PECR_DATA           (1 << 4)  /* Bit 4: Data EEPROM selection */
+#  define FLASH_PECR_FTDW           (1 << 8)  /* Bit 8: Fixed time data write for Byte, Half Word and Word programming */
+#  define FLASH_PECR_ERASE          (1 << 9)  /* Bit 9: Page or Double Word erase mode */
+#  define FLASH_PECR_FPRG           (1 << 10) /* Bit 10: Half Page/Double Word programming mode */
+#  define FLASH_PECR_PARALLBANK     (1 << 15) /* Bit 15: Parallel bank mode */
+#  define FLASH_PECR_EOPIE          (1 << 16) /* Bit 16: End of programming interrupt enable */
+#  define FLASH_PECR_ERRIE          (1 << 17) /* Bit 17: Error interrupt enable */
+#  define FLASH_PECR_OBL_LAUNCH     (1 << 18) /* Bit 18: Launch the option byte loading */
 #endif

 /* Flash Control Register (CR) */
@@ -380,7 +452,6 @@

 #  define FLASH_OPTCR1_BFB2_SHIFT    (4)                   /* Bits 4: Dual-bank Boot option byte */
 #  define FLASH_OPTCR1_BFB2_MASK     (1 << FLASH_OPTCR_NWRP_SHIFT)
-
 #endif

 #if defined(CONFIG_STM32_STM32F446)
@@ -424,6 +424,10 @@
 #define GPIO_I2C3_SCL_2       (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN7)
 #define GPIO_I2C3_SDA_1       (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTC|GPIO_PIN9)
 #define GPIO_I2C3_SDA_2       (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTH|GPIO_PIN8)
+#if defined(CONFIG_STM32_STM32F411)
+#  define GPIO_I2C3_SDA_3     (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN4)
+#  define GPIO_I2C3_SDA_4     (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)  
+#endif
 #define GPIO_I2C3_SMBA_1      (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
 #define GPIO_I2C3_SMBA_2      (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9)
 #if defined(CONFIG_STM32_STM32F446)
@@ -90,9 +90,7 @@
 #  error "Logic to support multiple Ethernet interfaces is incomplete"
 #endif

-/* If processing is not done at the interrupt level, then work queue support
- * is required.
- */
+/* Work queue support is required. */

 #if !defined(CONFIG_SCHED_WORKQUEUE)
 #  error Work queue support is required
@@ -59,10 +59,10 @@

 #include "up_arch.h"

-/* Only for the STM32F[1|3|4]0xx family for now */
+/* Only for the STM32F[1|3|4]0xx family and STM32L15xx (EEPROM only) for now */

 #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined (CONFIG_STM32_STM32F40XX)
+    defined (CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)

 #if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) && \
    (defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX))
@@ -73,15 +73,25 @@
 * Pre-processor Definitions
 ************************************************************************************/

-#define FLASH_KEY1      0x45670123
-#define FLASH_KEY2      0xCDEF89AB
+#if defined(CONFIG_STM32_STM32L15XX)
+#  define FLASH_KEY1      0x8C9DAEBF
+#  define FLASH_KEY2      0x13141516
+#else
+#  define FLASH_KEY1      0x45670123
+#  define FLASH_KEY2      0xCDEF89AB
+#endif

 #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
-#define FLASH_CR_PAGE_ERASE              FLASH_CR_PER
-#define FLASH_SR_WRITE_PROTECTION_ERROR  FLASH_SR_WRPRT_ERR
+#  define FLASH_CR_PAGE_ERASE              FLASH_CR_PER
+#  define FLASH_SR_WRITE_PROTECTION_ERROR  FLASH_SR_WRPRT_ERR
 #elif defined(CONFIG_STM32_STM32F40XX)
-#define FLASH_CR_PAGE_ERASE              FLASH_CR_SER
-#define FLASH_SR_WRITE_PROTECTION_ERROR  FLASH_SR_WRPERR
+#  define FLASH_CR_PAGE_ERASE              FLASH_CR_SER
+#  define FLASH_SR_WRITE_PROTECTION_ERROR  FLASH_SR_WRPERR
+#endif
+
+#if defined(CONFIG_STM32_STM32L15XX)
+#  define EEPROM_KEY1     0x89ABCDEF
+#  define EEPROM_KEY2     0x02030405
 #endif

 /************************************************************************************
@@ -107,6 +117,8 @@ static inline void sem_unlock(void)
  sem_post(&g_sem);
 }

+#if !defined(CONFIG_STM32_STM32L15XX)
+
 static void flash_unlock(void)
 {
  while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
@@ -128,6 +140,8 @@ static void flash_lock(void)
  modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK);
 }

+#endif /* !defined(CONFIG_STM32_STM32L15XX) */
+
 #if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
 static void data_cache_disable(void)
 {
@@ -146,6 +160,183 @@ static void data_cache_enable(void)
 }
 #endif /* defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */

+#if defined(CONFIG_STM32_STM32L15XX)
+
+static void stm32_eeprom_unlock(void)
+{
+  while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
+    {
+      up_waste();
+    }
+
+  if (getreg32(STM32_FLASH_PECR) & FLASH_PECR_PELOCK)
+    {
+      /* Unlock sequence */
+
+      putreg32(EEPROM_KEY1, STM32_FLASH_PEKEYR);
+      putreg32(EEPROM_KEY2, STM32_FLASH_PEKEYR);
+    }
+}
+
+static void stm32_eeprom_lock(void)
+{
+  modifyreg32(STM32_FLASH_PECR, 0, FLASH_PECR_PELOCK);
+}
+
+static void flash_unlock(void)
+{
+  if (getreg32(STM32_FLASH_PECR) & FLASH_PECR_PRGLOCK)
+    {
+      stm32_eeprom_unlock();
+
+      /* Unlock sequence */
+
+      putreg32(FLASH_KEY1, STM32_FLASH_PRGKEYR);
+      putreg32(FLASH_KEY2, STM32_FLASH_PRGKEYR);
+    }
+}
+
+static void flash_lock(void)
+{
+  modifyreg32(STM32_FLASH_PECR, 0, FLASH_PECR_PRGLOCK);
+  stm32_eeprom_lock();
+}
+
+static ssize_t stm32_eeprom_erase_write(size_t addr, const void *buf,
+                                        size_t buflen)
+{
+  const char *cbuf = buf;
+  size_t i;
+
+  if (buflen == 0)
+    {
+      return 0;
+    }
+
+  /* Check for valid address range */
+
+  if (addr >= STM32_EEPROM_BASE)
+    {
+      addr -= STM32_EEPROM_BASE;
+    }
+
+  if (addr >= STM32_EEPROM_SIZE)
+    {
+      return -EINVAL;
+    }
+
+  /* TODO: Voltage range must be range 1 or 2. Erase/program not allowed in
+   * range 3.
+   */
+
+  stm32_eeprom_unlock();
+
+  /* Clear pending status flags. */
+
+  putreg32(FLASH_SR_WRPERR | FLASH_SR_PGAERR |
+           FLASH_SR_SIZERR | FLASH_SR_OPTVERR |
+           FLASH_SR_OPTVERRUSR | FLASH_SR_RDERR, STM32_FLASH_SR);
+
+  /* Enable automatic erasing (by disabling 'fixed time' programming). */
+
+  modifyreg32(STM32_FLASH_PECR, FLASH_PECR_FTDW, 0);
+
+  /* Write buffer to EEPROM data memory. */
+
+  addr += STM32_EEPROM_BASE;
+  i = 0;
+  while (i < buflen)
+    {
+      uint32_t writeval;
+      size_t left = buflen - i;
+
+      if ((addr & 0x03) == 0x00 && left >= 4)
+        {
+          /* Read/erase/write word */
+
+          writeval = cbuf ? *(uint32_t *)cbuf : 0;
+          putreg32(writeval, addr);
+        }
+      else if ((addr & 0x01) == 0x00 && left >= 2)
+        {
+          /* Read/erase/write half-word */
+
+          writeval = cbuf ? *(uint16_t *)cbuf : 0;
+          putreg16(writeval, addr);
+        }
+      else
+        {
+          /* Read/erase/write byte */
+
+          writeval = cbuf ? *(uint8_t *)cbuf : 0;
+          putreg8(writeval, addr);
+        }
+
+      /* ... and wait to complete. */
+
+      while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
+        {
+          up_waste();
+        }
+
+      /* Verify */
+
+      /* We do not check Options Byte invalid flags FLASH_SR_OPTVERR
+       * and FLASH_SR_OPTVERRUSR for EEPROM erase/write. They are unrelated
+       * and STM32L standard library does not check for these either.
+       */
+
+      if (getreg32(STM32_FLASH_SR) & (FLASH_SR_WRPERR | FLASH_SR_PGAERR |
+                                      FLASH_SR_SIZERR | FLASH_SR_RDERR))
+        {
+          stm32_eeprom_lock();
+          return -EROFS;
+        }
+
+      if ((addr & 0x03) == 0x00 && left >= 4)
+        {
+          if (getreg32(addr) != writeval)
+            {
+              stm32_eeprom_lock();
+              return -EIO;
+            }
+
+          addr += 4;
+          i += 4;
+          cbuf += !!(cbuf) * 4;
+        }
+      else if ((addr & 0x01) == 0x00 && left >= 2)
+        {
+          if (getreg16(addr) != writeval)
+            {
+              stm32_eeprom_lock();
+              return -EIO;
+            }
+
+          addr += 2;
+          i += 2;
+          cbuf += !!(cbuf) * 2;
+        }
+      else
+        {
+          if (getreg8(addr) != writeval)
+            {
+              stm32_eeprom_lock();
+              return -EIO;
+            }
+
+          addr += 1;
+          i += 1;
+          cbuf += !!(cbuf) * 1;
+        }
+    }
+
+  stm32_eeprom_lock();
+  return buflen;
+}
+
+#endif /* defined(CONFIG_STM32_STM32L15XX) */
+
 /************************************************************************************
 * Public Functions
 ************************************************************************************/
@@ -164,6 +355,35 @@ void stm32_flash_lock(void)
  sem_unlock();
 }

+#if defined(CONFIG_STM32_STM32L15XX)
+
+size_t stm32_eeprom_size(void)
+{
+  return STM32_EEPROM_SIZE;
+}
+
+size_t stm32_eeprom_getaddress(void)
+{
+  return STM32_EEPROM_BASE;
+}
+
+ssize_t stm32_eeprom_write(size_t addr, const void *buf, size_t buflen)
+{
+  if (!buf)
+    {
+      return -EINVAL;
+    }
+
+  return stm32_eeprom_erase_write(addr, buf, buflen);
+}
+
+ssize_t stm32_eeprom_erase(size_t addr, size_t eraselen)
+{
+  return stm32_eeprom_erase_write(addr, NULL, eraselen);
+}
+
+#endif /* defined(CONFIG_STM32_STM32L15XX) */
+
 #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
 size_t up_progmem_pagesize(size_t page)
 {
@@ -260,6 +480,8 @@ size_t up_progmem_getaddress(size_t page)

 #endif /* def CONFIG_STM32_STM32F40XX */

+#if !defined(CONFIG_STM32_STM32L15XX)
+
 size_t up_progmem_npages(void)
 {
  return STM32_FLASH_NPAGES;
@@ -271,14 +493,14 @@ bool up_progmem_isuniform(void)
  return true;
 #else
  return false;
-#endif /* def STM32_FLASH_PAGESIZE */
+#endif
 }

 ssize_t up_progmem_erasepage(size_t page)
 {
 #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
  size_t page_address;
-#endif /* defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) */
+#endif

  if (page >= STM32_FLASH_NPAGES)
    {
@@ -438,5 +660,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
  return written;
 }

+#endif /* !defined(CONFIG_STM32_STM32L15XX) */
+
 #endif /* defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
-          defined (CONFIG_STM32_STM32F40XX) */
+          defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX) */
@@ -46,4 +46,60 @@
 #include "chip.h"
 #include "chip/stm32_flash.h"

+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_eeprom_size
+ *
+ * Description:
+ *   Get EEPROM data memory size
+ *
+ * Returns:
+ *  Length of EEPROM memory region
+ *
+ ************************************************************************************/
+
+size_t stm32_eeprom_size(void);
+
+/************************************************************************************
+ * Name: stm32_eeprom_getaddress
+ *
+ * Description:
+ *   Get EEPROM data memory address
+ *
+ * Returns:
+ *  Address of EEPROM memory region
+ *
+ ************************************************************************************/
+
+size_t stm32_eeprom_getaddress(void);
+
+/************************************************************************************
+ * Name: stm32_eeprom_write
+ *
+ * Description:
+ *    Write buffer to EEPROM data memory address
+ *
+ * Returns:
+ *  Number of written bytes or error code.
+ *
+ ************************************************************************************/
+
+ssize_t stm32_eeprom_write(size_t addr, const void *buf, size_t buflen);
+
+/************************************************************************************
+ * Name: stm32_eeprom_erase
+ *
+ * Description:
+ *    Erase memory on EEPROM data memory address
+ *
+ * Returns:
+ *  Number of erased bytes or error code.
+ *
+ ************************************************************************************/
+
+ssize_t stm32_eeprom_erase(size_t addr, size_t eraselen);
+
 #endif /* __ARCH_ARM_SRC_STM32_STM32_FLASH_H */
@@ -634,8 +634,8 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
 * Name: stm32_iwdginitialize
 *
 * Description:
- *   Initialize the IWDG watchdog time.  The watchdog timer is initialized and
- *   registers as 'devpath.  The initial state of the watchdog time is
+ *   Initialize the IWDG watchdog timer.  The watchdog timer is initialized and
+ *   registers as 'devpath'.  The initial state of the watchdog timer is
 *   disabled.
 *
 * Input Parameters:
@@ -665,7 +665,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
  priv->started = false;

  /* Make sure that the LSI oscillator is enabled.  NOTE:  The LSI oscillator
-   * is enabled here but is not disabled by this file (because this file does
+   * is enabled here but is not disabled by this file, because this file does
   * not know the global usage of the oscillator.  Any clock management
   * logic (say, as part of a power management scheme) needs handle other
   * LSI controls outside of this file.
@@ -685,9 +685,9 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)

  (void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);

-  /* When the microcontroller enters debug mode (Cortex™-M4F core halted),
+  /* When the microcontroller enters debug mode (Cortex-M4F core halted),
   * the IWDG counter either continues to work normally or stops, depending
-   * on DBG_WIDG_STOP configuration bit in DBG module.
+   * on DBG_IWDG_STOP configuration bit in DBG module.
   */

 #if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \
@@ -695,7 +695,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
    defined(CONFIG_STM32_JTAG_SW_ENABLE)
    {
 #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined(CONFIG_STM32_STM32F40XX)
+    defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
      uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ);
      cr |= DBGMCU_APB1_IWDGSTOP;
      putreg32(cr, STM32_DBGMCU_APB1_FZ);
@@ -734,8 +734,8 @@ static int stm32_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
 * Name: stm32_wwdginitialize
 *
 * Description:
- *   Initialize the WWDG watchdog time.  The watchdog timer is initialized and
- *   registers as 'devpath.  The initial state of the watchdog time is
+ *   Initialize the WWDG watchdog timer.  The watchdog timer is initialized and
+ *   registers as 'devpath'.  The initial state of the watchdog timer is
 *   disabled.
 *
 * Input Parameters:
@@ -753,7 +753,7 @@ void stm32_wwdginitialize(FAR const char *devpath)

  wdinfo("Entry: devpath=%s\n", devpath);

-  /* NOTE we assume that clocking to the IWDG has already been provided by
+  /* NOTE we assume that clocking to the WWDG has already been provided by
   * the RCC initialization logic.
   */

@@ -780,7 +780,7 @@ void stm32_wwdginitialize(FAR const char *devpath)

  (void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);

-  /* When the microcontroller enters debug mode (Cortex�-M4F core halted),
+  /* When the microcontroller enters debug mode (Cortex-M core halted),
   * the WWDG counter either continues to work normally or stops, depending
   * on DBG_WWDG_STOP configuration bit in DBG module.
   */
@@ -790,7 +790,7 @@ void stm32_wwdginitialize(FAR const char *devpath)
    defined(CONFIG_STM32_JTAG_SW_ENABLE)
    {
 #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined(CONFIG_STM32_STM32F40XX)
+    defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
      uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ);
      cr |= DBGMCU_APB1_WWDGSTOP;
      putreg32(cr, STM32_DBGMCU_APB1_FZ);
@@ -524,6 +524,8 @@ static void stm32_stdclockconfig(void)
 #if defined(CONFIG_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
  uint16_t pwrcr;
 #endif
+  uint32_t pwr_vos;
+  bool flash_1ws;

  /* Enable PWR clock from APB1 to give access to PWR_CR register */

@@ -537,12 +539,39 @@ static void stm32_stdclockconfig(void)
   * Range 1: PLLVCO up to 96MHz in range 1 (1.8V)
   * Range 2: PLLVCO up to 48MHz in range 2 (1.5V) (default)
   * Range 3: PLLVCO up to 24MHz in range 3 (1.2V)
+   *
+   * Range 1: SYSCLK up to 32Mhz
+   * Range 2: SYSCLK up to 16Mhz
+   * Range 3: SYSCLK up to 4.2Mhz
+   *
+   * Range 1: Flash 1WS if SYSCLK > 16Mhz
+   * Range 2: Flash 1WS if SYSCLK > 8Mhz
+   * Range 3: Flash 1WS if SYSCLK > 2.1Mhz
   */

-#if STM32_PLL_FREQUENCY > 48000000
-  stm32_pwr_setvos(PWR_CR_VOS_SCALE_1);
+  pwr_vos   = PWR_CR_VOS_SCALE_2;
+  flash_1ws = false;
+
+#ifdef STM32_PLL_FREQUENCY
+  if (STM32_PLL_FREQUENCY > 48000000)
+    {
+      pwr_vos = PWR_CR_VOS_SCALE_1;
+    }
 #endif

+  if (STM32_SYSCLK_FREQUENCY > 16000000)
+    {
+      pwr_vos = PWR_CR_VOS_SCALE_1;
+    }
+
+  if ((pwr_vos == PWR_CR_VOS_SCALE_1 && STM32_SYSCLK_FREQUENCY > 16000000) ||
+      (pwr_vos == PWR_CR_VOS_SCALE_2 && STM32_SYSCLK_FREQUENCY > 8000000))
+    {
+      flash_1ws = true;
+    }
+
+  stm32_pwr_setvos(pwr_vos);
+
 #if defined(CONFIG_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
  /* If RTC / LCD selects HSE as clock source, the RTC prescaler
   * needs to be set before HSEON bit is set.
@@ -579,12 +608,11 @@ static void stm32_stdclockconfig(void)

 #endif

-  /* Enable the source clock for the PLL (via HSE or HSI), HSE, and HSI.
-   * NOTE that only PLL, HSE, or HSI are supported for the system clock
-   * in this implementation
-   */
+  /* Enable the source clock for the PLL (via HSE or HSI), HSE, and HSI. */
+
+#if (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE) || \
+    ((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC))

-#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
  /* The PLL is using the HSE, or the HSE is the system clock.  In either
   * case, we need to enable HSE clocking.
   */
@@ -599,7 +627,9 @@ static void stm32_stdclockconfig(void)
      return;
    }

-#elif (STM32_CFGR_PLLSRC == 0) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSI)
+#elif (STM32_SYSCLK_SW == RCC_CFGR_SW_HSI) || \
+      ((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && STM32_CFGR_PLLSRC == 0)
+
  /* The PLL is using the HSI, or the HSI is the system clock.  In either
   * case, we need to enable HSI clocking.
   */
@@ -616,6 +646,8 @@ static void stm32_stdclockconfig(void)

 #endif

+#if (STM32_SYSCLK_SW != RCC_CFGR_SW_MSI)
+
  /* Increasing the CPU frequency (in the same voltage range):
   *
   * After reset, the used clock is the MSI (2 MHz) with 0 WS configured in the
@@ -643,7 +675,15 @@ static void stm32_stdclockconfig(void)
  regval |= FLASH_ACR_ACC64;          /* 64-bit access mode */
  putreg32(regval, STM32_FLASH_ACR);

-  regval |= FLASH_ACR_LATENCY;        /* One wait state */
+  if (flash_1ws)
+    {
+      regval |= FLASH_ACR_LATENCY;    /* One wait state */
+    }
+  else
+    {
+      regval &= ~FLASH_ACR_LATENCY;   /* Zero wait state */
+    }
+
  putreg32(regval, STM32_FLASH_ACR);

  /* Enable FLASH prefetch */
@@ -651,6 +691,8 @@ static void stm32_stdclockconfig(void)
  regval |= FLASH_ACR_PRFTEN;
  putreg32(regval, STM32_FLASH_ACR);

+#endif /* STM32_SYSCLK_SW != RCC_CFGR_SW_MSI */
+
  /* Set the HCLK source/divider */

  regval = getreg32(STM32_RCC_CFGR);
@@ -1823,7 +1823,7 @@ config STM32F7_HAVE_RTC_COUNTER

 config STM32F7_HAVE_RTC_SUBSECONDS
 	bool
-	default n
+	default y

 config RTC_MAGIC_REG
 	int "The BKP register used to store/check the Magic value to determine if RTC is set already"
@@ -149,6 +149,10 @@ ifeq ($(filter y,$(CONFIG_STM32F7_IWDG) $(CONFIG_STM32F7_RTC_LSICLOCK)),y)
 CHIP_CSRCS += stm32_lsi.c
 endif

+ifeq ($(CONFIG_STM32F7_RTC_LSECLOCK),y)
+CHIP_CSRCS += stm32_lse.c
+endif
+
 ifeq ($(CONFIG_STM32F7_I2C),y)
 CHIP_CSRCS += stm32_i2c.c
 endif
@@ -129,7 +129,7 @@ static int stm32_exti_pvd_isr(int irq, void *context, void *arg)
 ****************************************************************************/

 int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event,
-                   xcpt_t func, void *arg);
+                   xcpt_t func, void *arg)
 {
  /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */

@@ -1,8 +1,9 @@
 /****************************************************************************
- * net/sixlowpan/sixlowpan_sniffer.c
+ * arch/arm/src/stm32f7/stm32_lse.c
 *
 *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -39,43 +40,47 @@

 #include <nuttx/config.h>

-#include "nuttx/net/net.h"
-#include "nuttx/net/sixlowpan.h"
+#include "up_arch.h"

-#include "sixlowpan/sixlowpan_internal.h"
-
-#ifdef CONFIG_NET_6LOWPAN_SNIFFER
+#include "stm32_rcc.h"
+#include "stm32_pwr.h"

 /****************************************************************************
 * Public Functions
 ****************************************************************************/

 /****************************************************************************
- * Function: sixlowpan_set_sniffer
+ * Name: stm32_rcc_enablelse
 *
 * Description:
- *   Configure to use an architecture-specific sniffer to enable tracing of
- *   IP.
- *
- * Input parameters:
- *   sniffer - A reference to the new sniffer to be used.  This may
- *             be a NULL value to disable the sniffer.
- *
- * Returned Value:
- *   None
+ *   Enable the External Low-Speed (LSE) oscillator.
 *
 ****************************************************************************/

-void sixlowpan_set_sniffer(FAR struct sixlowpan_rime_sniffer_s *sniffer)
+void stm32_rcc_enablelse(void)
 {
-  /* Make sure that the sniffer is not in use */
+  uint32_t regval;

-  net_lock();
+  /* The LSE is in the RTC domain and write access is denied to this domain
+   * after reset, you have to enable write access using DBP bit in the PWR CR
+   * register before to configuring the LSE.
+   */

-  /* Then instantiate the new sniffer */
+  stm32_pwr_enablebkp(true);

-  g_sixlowpan_sniffer = sniffer;
-  net_unlock();
+  /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
+   * the RCC BDCR register.
+   */
+
+  regval  = getreg32(STM32_RCC_BDCR);
+  regval |= RCC_BDCR_LSEON;
+  putreg32(regval,STM32_RCC_BDCR);
+
+  /* Wait for the LSE clock to be ready */
+
+  while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0);
+
+  /* Disable backup domain access if it was disabled on entry */
+
+  stm32_pwr_enablebkp(false);
 }
-
-#endif /* CONFIG_NET_6LOWPAN_SNIFFER */
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f/stm32_lsi.c
+ * arch/arm/src/stm32f7/stm32_lsi.c
 *
 *   Copyright (C) 2012, 2015-2016 Gregory Nutt. All rights reserved.
 *   Authors: Gregory Nutt <gnutt@nuttx.org>
@@ -196,7 +196,7 @@ static void rtc_dumpregs(FAR const char *msg)
  rtcinfo("    TSDR: %08x\n", getreg32(STM32_RTC_TSDR));
  rtcinfo("   TSSSR: %08x\n", getreg32(STM32_RTC_TSSSR));
  rtcinfo("    CALR: %08x\n", getreg32(STM32_RTC_CALR));
-  rtcinfo("   TAFCR: %08x\n", getreg32(STM32_RTC_TAFCR));
+  rtcinfo("  TAMPCR: %08x\n", getreg32(STM32_RTC_TAMPCR));
  rtcinfo("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR));
  rtcinfo("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR));
  rtcinfo("MAGICREG: %08x\n", getreg32(RTC_MAGIC_REG));
@@ -227,7 +227,8 @@ static void rtc_dumpregs(FAR const char *msg)
 ****************************************************************************/

 #ifdef CONFIG_DEBUG_RTC_INFO
-static void rtc_dumptime(FAR const struct tm *tp, FAR const char *msg)
+static void rtc_dumptime(FAR const struct tm *tp, FAR const uint32_t *usecs,
+                         FAR const char *msg)
 {
  rtcinfo("%s:\n", msg);
  rtcinfo("  tm_sec: %08x\n", tp->tm_sec);
@@ -236,9 +237,14 @@ static void rtc_dumptime(FAR const struct tm *tp, FAR const char *msg)
  rtcinfo(" tm_mday: %08x\n", tp->tm_mday);
  rtcinfo("  tm_mon: %08x\n", tp->tm_mon);
  rtcinfo(" tm_year: %08x\n", tp->tm_year);
+
+  if (usecs != NULL)
+    {
+      rtcinfo("   usecs: %08x\n", (unsigned int)*usecs);
+    }
 }
 #else
-#  define rtc_dumptime(tp, msg)
+#  define rtc_dumptime(tp, usecs, msg)
 #endif

 /****************************************************************************
@@ -1069,34 +1075,48 @@ int up_rtc_initialize(void)
 *
 ****************************************************************************/

-#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
+#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS
 int stm32_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec)
 #else
 int up_rtc_getdatetime(FAR struct tm *tp)
 #endif
 {
-#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
-  uint32_t ssr;
-#endif
  uint32_t dr;
  uint32_t tr;
  uint32_t tmp;
+#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS
+  uint32_t ssr;
+  uint32_t prediv_s;
+  uint32_t usecs;
+#endif

  /* Sample the data time registers.  There is a race condition here... If
   * we sample the time just before midnight on December 31, the date could
-   * be wrong because the day rolled over while were sampling.
+   * be wrong because the day rolled over while were sampling. Thus loop for
+   * checking overflow here is needed.  There is a race condition with
+   * subseconds too. If we sample TR register just before second rolling
+   * and subseconds are read at wrong second, we get wrong time.
   */

  do
    {
      dr  = getreg32(STM32_RTC_DR);
      tr  = getreg32(STM32_RTC_TR);
-#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
+#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS
      ssr = getreg32(STM32_RTC_SSR);
+      tmp = getreg32(STM32_RTC_TR);
+      if (tmp != tr)
+        {
+          continue;
+        }
 #endif
      tmp = getreg32(STM32_RTC_DR);
+      if (tmp == dr)
+        {
+          break;
+        }
    }
-  while (tmp != dr);
+  while (1);

  rtc_dumpregs("Reading Time");

@@ -1141,31 +1161,31 @@ int up_rtc_getdatetime(FAR struct tm *tp)
  tp->tm_isdst = 0
 #endif

-#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
+#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS
  /* Return RTC sub-seconds if no configured and if a non-NULL value
   * of nsec has been provided to receive the sub-second value.
   */

-  if (nsec)
+  prediv_s   = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK;
+  prediv_s >>= RTC_PRER_PREDIV_S_SHIFT;
+
+  ssr &= RTC_SSR_MASK;
+
+  /* Maximum prediv_s is 0x7fff, thus we can multiply by 100000 and
+   * still fit 32-bit unsigned integer.
+   */
+
+  usecs = (((prediv_s - ssr) * 100000) / (prediv_s + 1)) * 10;
+  if (nsec != NULL)
    {
-      uint32_t prediv_s;
-      uint32_t usecs;
-
-      prediv_s   = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK;
-      prediv_s >>= RTC_PRER_PREDIV_S_SHIFT;
-
-      ssr &= RTC_SSR_MASK;
-
-      /* Maximum prediv_s is 0x7fff, thus we can multiply by 100000 and
-       * still fit 32-bit unsigned integer.
-       */
-
-      usecs = (((prediv_s - ssr) * 100000) / (prediv_s + 1)) * 10;
      *nsec = usecs * 1000;
    }
-#endif /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */

-  rtc_dumptime((FAR const struct tm *)tp, "Returning");
+  rtc_dumptime((FAR const struct tm *)tp, &usecs, "Returning");
+#else /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */
+  rtc_dumptime((FAR const struct tm *)tp, NULL, "Returning");
+#endif
+
  return OK;
 }

@@ -1192,7 +1212,7 @@ int up_rtc_getdatetime(FAR struct tm *tp)
 *
 ****************************************************************************/

-#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS
+#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS
 int up_rtc_getdatetime(FAR struct tm *tp)
 {
  return stm32_rtc_getdatetime_with_subseconds(tp, NULL);
@@ -1221,7 +1241,7 @@ int stm32_rtc_setdatetime(FAR const struct tm *tp)
  uint32_t dr;
  int ret;

-  rtc_dumptime(tp, "Setting time");
+  rtc_dumptime(tp, NULL, "Setting time");

  /* Then write the broken out values to the RTC */

@@ -1337,7 +1357,7 @@ int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo)

  /* REVISIT:  Should test that the time is in the future */

-  rtc_dumptime(&alminfo->as_time, "New alarm time");
+  rtc_dumptime(&alminfo->as_time, NULL, "New alarm time");

  /* Break out the values to the HW alarm register format.  The values in
   * all STM32 fields match the fields of struct tm in this case.  Notice
@@ -1510,7 +1510,7 @@ static int stm32_sdmmc_rdyinterrupt(int irq, void *context, void *arg)
 *
 ****************************************************************************/

-static int stm32_sdmmc_interrupt(int irq, void *context, void *arg);
+static int stm32_sdmmc_interrupt(int irq, void *context, void *arg)
 {
  struct stm32_dev_s *priv =(struct stm32_dev_s *)arg;
  uint32_t enabled;
@@ -1,8 +1,9 @@
 /****************************************************************************
 * arch/arm/src/stm32f7/stm32_serial.c
 *
- *   Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -189,16 +190,6 @@
               CONFIG_USART_DMAPRIO  | \
               DMA_SCR_PBURST_SINGLE | \
               DMA_SCR_MBURST_SINGLE)
-#  ifdef CONFIG_SERIAL_IFLOWCONTROL
-#    define SERIAL_DMA_IFLOW_CONTROL_WORD \
-              (DMA_SCR_DIR_P2M       | \
-               DMA_SCR_MINC          | \
-               DMA_SCR_PSIZE_8BITS   | \
-               DMA_SCR_MSIZE_8BITS   | \
-               CONFIG_USART_DMAPRIO  | \
-               DMA_SCR_PBURST_SINGLE | \
-               DMA_SCR_MBURST_SINGLE)
-#  endif
 #endif /* SERIAL_HAVE_DMA */

 /* Power management definitions */
@@ -286,8 +277,7 @@ struct up_dev_s
 #ifdef SERIAL_HAVE_DMA
  DMA_HANDLE        rxdma;     /* currently-open receive DMA stream */
  bool              rxenable;  /* DMA-based reception en/disable */
-  uint16_t          rxdmain;   /* Next byte in the DMA where hardware will write */
-  uint16_t          rxdmaout;  /* Next byte in the DMA buffer to be read */
+  uint32_t          rxdmanext; /* Next byte in the DMA buffer to be read */
  char      *const  rxfifo;    /* Receive DMA buffer */
 #endif

@@ -1139,7 +1129,22 @@ static void up_set_format(struct uart_dev_s *dev)
  uint32_t regval;
  uint32_t usartdiv8;
  uint32_t cr1;
+  uint32_t cr1_ue;
  uint32_t brr;
+  irqstate_t flags;
+
+  flags = enter_critical_section();
+
+  /* Get the original state of UE */
+
+  cr1  = up_serialin(priv, STM32_USART_CR1_OFFSET);
+  cr1_ue = cr1 & USART_CR1_UE;
+  cr1 &= ~USART_CR1_UE;
+
+  /* Disable UE as the format bits and baud rate registers can not be
+   * updated while UE = 1 */
+
+  up_serialout(priv, STM32_USART_CR1_OFFSET, cr1);

  /* In case of oversampling by 8, the equation is:
   *
@@ -1159,7 +1164,6 @@ static void up_set_format(struct uart_dev_s *dev)

  /* Use oversamply by 8 only if the divisor is small.  But what is small? */

-  cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET);
  if (usartdiv8 > 100)
    {
      /* Use usartdiv16 */
@@ -1188,30 +1192,44 @@ static void up_set_format(struct uart_dev_s *dev)

  /* Configure parity mode */

-  regval  = up_serialin(priv, STM32_USART_CR1_OFFSET);
-  regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0);
+  cr1 &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1);

  if (priv->parity == 1)       /* Odd parity */
    {
-      regval |= (USART_CR1_PCE | USART_CR1_PS);
+      cr1 |= (USART_CR1_PCE | USART_CR1_PS);
    }
  else if (priv->parity == 2)  /* Even parity */
    {
-      regval |= USART_CR1_PCE;
+      cr1 |= USART_CR1_PCE;
    }

-  /* Configure word length (Default: 8-bits) */
+  /* Configure word length (parity uses one of configured bits)
+   *
+   * Default: 1 start, 8 data (no parity), n stop, OR
+   *          1 start, 7 data + parity, n stop
+   */

-  if (priv->bits == 7)
+  if (priv->bits == 9 || (priv->bits == 8 && priv->parity != 0))
    {
-      regval |= USART_CR1_M1;
+      /* Select: 1 start, 8 data + parity, n stop, OR
+       *         1 start, 9 data (no parity), n stop.
+       */
+
+      cr1 |= USART_CR1_M0;
    }
-  else if (priv->bits == 9)
+  else if (priv->bits == 7 && priv->parity == 0)
    {
-      regval |= USART_CR1_M0;
+      /* Select: 1 start, 7 data (no parity), n stop, OR
+       */
+
+      cr1 |= USART_CR1_M1;
    }

-  up_serialout(priv, STM32_USART_CR1_OFFSET, regval);
+  /* Else Select: 1 start, 7 data + parity, n stop, OR
+   *              1 start, 8 data (no parity), n stop.
+   */
+
+  up_serialout(priv, STM32_USART_CR1_OFFSET, cr1);

  /* Configure STOP bits */

@@ -1230,7 +1248,8 @@ static void up_set_format(struct uart_dev_s *dev)
  regval  = up_serialin(priv, STM32_USART_CR3_OFFSET);
  regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE);

-#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN)
+#if defined(CONFIG_SERIAL_IFLOWCONTROL) && \
+   !defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN)
  if (priv->iflow && (priv->rts_gpio != 0))
    {
      regval |= USART_CR3_RTSE;
@@ -1245,6 +1264,8 @@ static void up_set_format(struct uart_dev_s *dev)
 #endif

  up_serialout(priv, STM32_USART_CR3_OFFSET, regval);
+  up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue);
+  leave_critical_section(flags);
 }
 #endif /* CONFIG_SUPPRESS_UART_CONFIG */

@@ -1473,35 +1494,19 @@ static int up_dma_setup(struct uart_dev_s *dev)

  priv->rxdma = stm32_dmachannel(priv->rxdma_channel);

-#ifdef CONFIG_SERIAL_IFLOWCONTROL
-  if (priv->iflow)
-    {
-      /* Configure for non-circular DMA reception into the RX FIFO */
+    /* Configure for circular DMA reception into the RX FIFO */

-      stm32_dmasetup(priv->rxdma,
-                     priv->usartbase + STM32_USART_RDR_OFFSET,
-                     (uint32_t)priv->rxfifo,
-                     RXDMA_BUFFER_SIZE,
-                     SERIAL_DMA_IFLOW_CONTROL_WORD);
-    }
-  else
-#endif
-    {
-      /* Configure for circular DMA reception into the RX FIFO */
-
-      stm32_dmasetup(priv->rxdma,
-                     priv->usartbase + STM32_USART_RDR_OFFSET,
-                     (uint32_t)priv->rxfifo,
-                     RXDMA_BUFFER_SIZE,
-                     SERIAL_DMA_CONTROL_WORD);
-    }
+    stm32_dmasetup(priv->rxdma,
+                   priv->usartbase + STM32_USART_RDR_OFFSET,
+                   (uint32_t)priv->rxfifo,
+                   RXDMA_BUFFER_SIZE,
+                   SERIAL_DMA_CONTROL_WORD);

  /* Reset our DMA shadow pointer to match the address just
   * programmed above.
   */

-  priv->rxdmaout = 0;
-  priv->rxdmain  = 0;
+  priv->rxdmanext = 0;

  /* Enable receive DMA for the UART */

@@ -1509,26 +1514,12 @@ static int up_dma_setup(struct uart_dev_s *dev)
  regval |= USART_CR3_DMAR;
  up_serialout(priv, STM32_USART_CR3_OFFSET, regval);

-#ifdef CONFIG_SERIAL_IFLOWCONTROL
-  if (priv->iflow)
-    {
-      /* Start the DMA channel, and arrange for callbacks at the full point
-       * in the FIFO. After buffer gets full, hardware flow-control kicks
-       * in and DMA transfer is stopped.
-       */
+    /* Start the DMA channel, and arrange for callbacks at the half and
+     * full points in the FIFO.  This ensures that we have half a FIFO
+     * worth of time to claim bytes before they are overwritten.
+     */

-      stm32_dmastart(priv->rxdma, up_dma_rxcallback, (void *)priv, false);
-    }
-  else
-#endif
-    {
-      /* Start the DMA channel, and arrange for callbacks at the half and
-       * full points in the FIFO.  This ensures that we have half a FIFO
-       * worth of time to claim bytes before they are overwritten.
-       */
-
-      stm32_dmastart(priv->rxdma, up_dma_rxcallback, (void *)priv, true);
-    }
+    stm32_dmastart(priv->rxdma, up_dma_rxcallback, (void *)priv, true);

  return OK;
 }
@@ -2226,49 +2217,27 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev,
 static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status)
 {
  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
-  uint32_t rxdmain;
  int c = 0;

  /* If additional bytes have been added to the DMA buffer, then we will need
   * to invalidate the DMA buffer before reading the byte.
   */

-  rxdmain = up_dma_nextrx(priv);
-  if (rxdmain != priv->rxdmain)
+  if (up_dma_nextrx(priv) != priv->rxdmanext)
    {
      /* Invalidate the DMA buffer */

      arch_invalidate_dcache((uintptr_t)priv->rxfifo,
                             (uintptr_t)priv->rxfifo + RXDMA_BUFFER_SIZE - 1);

-      /* Since DMA is ongoing, there are lots of race conditions here.  We
-       * just have to hope that the rxdmaout stays well ahead of rxdmain.
-       */
+      /* Now read from the DMA buffer */

-      priv->rxdmain = rxdmain;
-    }
+      c = priv->rxfifo[priv->rxdmanext];

-  /* Now check if there are any bytes to read from the DMA buffer */
-
-  if (rxdmain != priv->rxdmaout)
-    {
-      c = priv->rxfifo[priv->rxdmaout];
-
-      priv->rxdmaout++;
-      if (priv->rxdmaout == RXDMA_BUFFER_SIZE)
+      priv->rxdmanext++;
+      if (priv->rxdmanext == RXDMA_BUFFER_SIZE)
        {
-#ifdef CONFIG_SERIAL_IFLOWCONTROL
-          if (priv->iflow)
-            {
-              /* RX DMA buffer full. RX paused, RTS line pulled up to prevent
-               * more input data from other end.
-               */
-            }
-          else
-#endif
-            {
-              priv->rxdmaout = 0;
-            }
+          priv->rxdmanext = 0;
        }
    }

@@ -2276,41 +2245,6 @@ static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status)
 }
 #endif

-/****************************************************************************
- * Name: up_dma_reenable
- *
- * Description:
- *   Call to re-enable RX DMA.
- *
- ****************************************************************************/
-
-#if defined(SERIAL_HAVE_DMA) && defined(CONFIG_SERIAL_IFLOWCONTROL)
-static void up_dma_reenable(struct up_dev_s *priv)
-{
-  /* Configure for non-circular DMA reception into the RX FIFO */
-
-  stm32_dmasetup(priv->rxdma,
-                 priv->usartbase + STM32_USART_RDR_OFFSET,
-                 (uint32_t)priv->rxfifo,
-                 RXDMA_BUFFER_SIZE,
-                 SERIAL_DMA_IFLOW_CONTROL_WORD);
-
-  /* Reset our DMA shadow pointer to match the address just programmed
-   * above.
-   */
-
-  priv->rxdmaout = 0;
-  priv->rxdmain  = 0;
-
-  /* Start the DMA channel, and arrange for callbacks at the full point in
-   * the FIFO. After buffer gets full, hardware flow-control kicks in and
-   * DMA transfer is stopped.
-   */
-
-  stm32_dmastart(priv->rxdma, up_dma_rxcallback, (void *)priv, false);
-}
-#endif
-
 /****************************************************************************
 * Name: up_dma_rxint
 *
@@ -2333,15 +2267,6 @@ static void up_dma_rxint(struct uart_dev_s *dev, bool enable)
   */

  priv->rxenable = enable;
-
-#ifdef CONFIG_SERIAL_IFLOWCONTROL
-  if (priv->iflow && priv->rxenable && (priv->rxdmaout == RXDMA_BUFFER_SIZE))
-    {
-      /* Re-enable RX DMA. */
-
-      up_dma_reenable(priv);
-    }
-#endif
 }
 #endif

@@ -2362,7 +2287,7 @@ static bool up_dma_rxavailable(struct uart_dev_s *dev)
   * do not match, then there are bytes to be received.
   */

-  return (up_dma_nextrx(priv) != priv->rxdmaout);
+  return (up_dma_nextrx(priv) != priv->rxdmanext);
 }
 #endif

@@ -2486,16 +2411,6 @@ static void up_dma_rxcallback(DMA_HANDLE handle, uint8_t status, void *arg)
  if (priv->rxenable && up_dma_rxavailable(&priv->dev))
    {
      uart_recvchars(&priv->dev);
-
-#ifdef CONFIG_SERIAL_IFLOWCONTROL
-      if (priv->iflow && priv->rxenable &&
-          (priv->rxdmaout == RXDMA_BUFFER_SIZE))
-        {
-          /* Re-enable RX DMA. */
-
-          up_dma_reenable(priv);
-        }
-#endif
    }
 }
 #endif
@@ -100,10 +100,19 @@ config SIM_WALLTIME
 		correct for the system timer tick rate.  With this definition in the configuration,
 		sleep() behavior is more or less normal.

+config SIM_NETDEV
+	bool "Simulated Network Device"
+	default y
+	depends on NET
+	---help---
+		Build in support for a simulated network device using a TAP device on Linux or
+		WPCAP on Windows.
+
 if HOST_LINUX
 choice
 	prompt "Simulation Network Type"
 	default SIM_NET_HOST_ROUTE
+	depends on SIM_NETDEV

 config SIM_NET_HOST_ROUTE
 	bool "Use local host route"
@@ -119,6 +119,7 @@ ifeq ($(CONFIG_ARCH_ROMGETC),y)
  CSRCS += up_romgetc.c
 endif

+ifeq ($(CONFIG_SIM_NETDEV),y)
 ifeq ($(CONFIG_NET_ETHERNET),y)
  CSRCS += up_netdriver.c
  HOSTCFLAGS += -DNETDEV_BUFSIZE=$(CONFIG_NET_ETH_MTU)
@@ -131,11 +132,12 @@ endif
 ifeq ($(CONFIG_SIM_NET_HOST_ROUTE),y)
  HOSTCFLAGS += -DCONFIG_SIM_NET_HOST_ROUTE
 endif
-else
+else # HOSTOS != Cygwin
  HOSTSRCS += up_wpcap.c up_netdev.c
  DRVLIB = /lib/w32api/libws2_32.a /lib/w32api/libiphlpapi.a
-endif
-endif
+endif # HOSTOS != Cygwin
+endif # CONFIG_NET_ETHERNET
+endif # CONFIG_SIM_NETDEV

 ifeq ($(CONFIG_SMP),y)
  HOSTCFLAGS += -DCONFIG_SMP=1 -DCONFIG_SMP_NCPUS=$(CONFIG_SMP_NCPUS)
@@ -142,7 +142,7 @@ void up_idle(void)
    }
 #endif

-#ifdef CONFIG_NET_ETHERNET
+#if defined(CONFIG_NET_ETHERNET) && defined(CONFIG_SIM_NETDEV)
  /* Run the network if enabled */

  netdriver_loop();
@@ -270,7 +270,7 @@ void up_initialize(void)
  up_registerblockdevice(); /* Our FAT ramdisk at /dev/ram0 */
 #endif

-#ifdef CONFIG_NET_ETHERNET
+#if defined(CONFIG_NET_ETHERNET) && defined(CONFIG_SIM_NETDEV)
  netdriver_init();         /* Our "real" network driver */
 #endif

@@ -209,7 +209,7 @@ void netdriver_loop(void)
            {
              pkt_input(&g_sim_dev);
            }
-#endif
+#endif /* CONFIG_NET_PKT */

          /* We only accept IP packets of the configured type and ARP packets */

@@ -253,7 +253,7 @@ void netdriver_loop(void)
                }
            }
          else
-#endif
+#endif /* CONFIG_NET_IPv4 */
 #ifdef CONFIG_NET_IPv6
          if (eth->type == HTONS(ETHTYPE_IP6) && is_ours)
            {
@@ -283,7 +283,7 @@ void netdriver_loop(void)
                    {
                      neighbor_out(&g_sim_dev);
                    }
-#endif
+#endif /* CONFIG_NET_IPv6 */

                  /* And send the packet */

@@ -291,7 +291,7 @@ void netdriver_loop(void)
                }
            }
          else
-#endif
+#endif/* CONFIG_NET_IPv6 */
 #ifdef CONFIG_NET_ARP
          if (eth->type == htons(ETHTYPE_ARP))
            {
@@ -307,7 +307,11 @@ void netdriver_loop(void)
                  netdev_send(g_sim_dev.d_buf, g_sim_dev.d_len);
                }
            }
+          else
 #endif
+           {
+             nwarn("WARNING: Unsupported Ethernet type %u\n", eth->type)
+           }
        }
    }

@@ -807,6 +807,12 @@ pashello

  Configures to use apps/examples/pashello.

+sixlowpan
+
+  This configuration was intended only for unit-level testing of the
+  6loWPAN stack.  It enables networking with 6loWPAN support and uses
+  only a IEEE802.15.4 MAC loopback network device to supported testing.
+
 touchscreen

  This configuration uses the simple touchscreen test at
@@ -77,6 +77,7 @@ CONFIG_HOST_X86_64=y
 CONFIG_SIM_X8664_SYSTEMV=y
 # CONFIG_SIM_X8664_MICROSOFT is not set
 # CONFIG_SIM_WALLTIME is not set
+CONFIG_SIM_NETDEV=y
 CONFIG_SIM_NET_HOST_ROUTE=y
 # CONFIG_SIM_NET_BRIDGE is not set
 # CONFIG_SIM_FRAMEBUFFER is not set
@@ -203,6 +204,8 @@ CONFIG_MAX_TASKS=64
 #
 # CONFIG_PTHREAD_MUTEX_TYPES is not set
 CONFIG_PTHREAD_MUTEX_ROBUST=y
+# CONFIG_PTHREAD_MUTEX_UNSAFE is not set
+# CONFIG_PTHREAD_MUTEX_BOTH is not set
 CONFIG_NPTHREAD_KEYS=4
 # CONFIG_PTHREAD_CLEANUP is not set
 # CONFIG_CANCELLATION_POINTS is not set
@@ -368,6 +371,7 @@ CONFIG_SERIAL_CONSOLE=y
 # CONFIG_PSEUDOTERM is not set
 # CONFIG_USBDEV is not set
 # CONFIG_USBHOST is not set
+# CONFIG_USBMISC is not set
 # CONFIG_HAVE_USBTRACE is not set
 # CONFIG_DRIVERS_WIRELESS is not set
 # CONFIG_DRIVERS_CONTACTLESS is not set
@@ -408,10 +412,12 @@ CONFIG_NET_GUARDSIZE=2
 CONFIG_NET_ETHERNET=y
 # CONFIG_NET_LOOPBACK is not set
 # CONFIG_NET_TUN is not set
+# CONFIG_NET_USRSOCK is not set

 #
 # Network Device Operations
 #
+# CONFIG_NETDEV_IOCTL is not set
 # CONFIG_NETDEV_PHY_IOCTL is not set

 #
@@ -442,6 +448,7 @@ CONFIG_NET_SOCKOPTS=y
 # TCP/IP Networking
 #
 CONFIG_NET_TCP=y
+# CONFIG_NET_TCP_NO_STACK is not set
 # CONFIG_NET_TCPURGDATA is not set
 CONFIG_NET_TCP_CONNS=40
 CONFIG_NET_MAX_LISTENPORTS=40
@@ -456,6 +463,7 @@ CONFIG_NET_TCP_RECVDELAY=0
 # UDP Networking
 #
 # CONFIG_NET_UDP is not set
+# CONFIG_NET_UDP_NO_STACK is not set

 #
 # ICMP Networking Support
@@ -484,6 +492,10 @@ CONFIG_NET_IOB=y
 CONFIG_IOB_NBUFFERS=24
 CONFIG_IOB_BUFSIZE=196
 CONFIG_IOB_NCHAINS=8
+
+#
+# User-space networking stack API
+#
 # CONFIG_NET_ARCH_INCR32 is not set
 # CONFIG_NET_ARCH_CHKSUM is not set
 CONFIG_NET_STATISTICS=y
@@ -717,7 +729,6 @@ CONFIG_EXAMPLES_NETTEST_IPADDR=0xc0a80080
 CONFIG_EXAMPLES_NETTEST_DRIPADDR=0xc0a80001
 CONFIG_EXAMPLES_NETTEST_NETMASK=0xffffff00
 CONFIG_EXAMPLES_NETTEST_CLIENTIP=0xc0a8006a
-# CONFIG_EXAMPLES_NRF24L01TERM is not set
 # CONFIG_EXAMPLES_NSH is not set
 # CONFIG_EXAMPLES_NULL is not set
 # CONFIG_EXAMPLES_NX is not set
@@ -748,6 +759,7 @@ CONFIG_EXAMPLES_NETTEST_CLIENTIP=0xc0a8006a
 # CONFIG_EXAMPLES_WATCHDOG is not set
 # CONFIG_EXAMPLES_WEBSERVER is not set
 # CONFIG_EXAMPLES_WGET is not set
+# CONFIG_EXAMPLES_XBC_TEST is not set

 #
 # File System Utilities
@@ -0,0 +1,128 @@
+############################################################################
+# configs/sim/sixlowpan/Make.defs
+#
+#   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+
+HOSTOS			= ${shell uname -o 2>/dev/null || echo "Other"}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  ARCHOPTIMIZATION	= -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+  ARCHOPTIMIZATION	+= -O2
+endif
+
+ARCHCPUFLAGS		= -fno-builtin
+ARCHCPUFLAGSXX		= -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
+ARCHPICFLAGS		= -fpic
+ARCHWARNINGS		= -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX		= -Wall -Wshadow -Wundef
+ARCHDEFINES		=
+ARCHINCLUDES		= -I. -isystem $(TOPDIR)/include
+ARCHINCLUDESXX		= -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+ARCHSCRIPT		=
+
+ifeq ($(CONFIG_SIM_M32),y)
+  ARCHCPUFLAGS		+= -m32
+  ARCHCPUFLAGSXX	+= -m32
+endif
+
+CROSSDEV		=
+CC			= $(CROSSDEV)gcc
+CXX			= $(CROSSDEV)g++
+CPP			= $(CROSSDEV)gcc -E
+LD			= $(CROSSDEV)ld
+AR			= $(CROSSDEV)ar rcs
+NM			= $(CROSSDEV)nm
+OBJCOPY			= $(CROSSDEV)objcopy
+OBJDUMP			= $(CROSSDEV)objdump
+
+CFLAGS			= $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \
+			  $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXFLAGS		= $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) \
+			  $(ARCHCPUFLAGSXX) $(ARCHINCLUDESXX) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPPFLAGS		= $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS			= $(CFLAGS) -D__ASSEMBLY__
+
+
+# ELF module definitions
+
+CELFFLAGS = $(CFLAGS)
+CXXELFFLAGS = $(CXXFLAGS)
+
+LDELFFLAGS = -r -e main
+ifeq ($(WINTOOL),y)
+  LDELFFLAGS += -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/gnu-elf.ld}"
+else
+  LDELFFLAGS += -T $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/gnu-elf.ld
+endif
+
+
+ASMEXT			= .S
+OBJEXT			= .o
+LIBEXT			= .a
+
+ifeq ($(HOSTOS),Cygwin)
+  EXEEXT		= .exe
+else
+  EXEEXT		=
+endif
+
+LDLINKFLAGS		= $(ARCHSCRIPT)	# Link flags used with $(LD)
+CCLINKFLAGS		= $(ARCHSCRIPT)	# Link flags used with $(CC)
+LDFLAGS			= $(ARCHSCRIPT)	# For backward compatibility, same as CCLINKFLAGS
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  LDLINKFLAGS		+= -g
+  CCLINKFLAGS		+= -g
+  LDFLAGS			+= -g
+endif
+
+ifeq ($(CONFIG_SIM_M32),y)
+  LDLINKFLAGS		+= -melf_i386
+  CCLINKFLAGS		+= -m32
+  LDFLAGS			+= -m32
+endif
+
+
+MKDEP			= $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+
+HOSTCC			= gcc
+HOSTINCLUDES		= -I.
+HOSTCFLAGS		= $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \
+			  $(ARCHCPUFLAGS) $(HOSTINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+HOSTLDFLAGS		=
@@ -0,0 +1,45 @@
+#!/bin/bash
+# sim/sixlowpan/setenv.sh
+#
+#   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$(basename $0)" = "setenv.sh" ] ; then
+  echo "You must source this script, not run it!" 1>&2
+  exit 1
+fi
+
+if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi
+
+#export NUTTX_BIN=
+#export PATH=${NUTTX_BIN}:/sbin:/usr/sbin:${PATH_ORIG}
+
+echo "PATH : ${PATH}"
@@ -42,22 +42,6 @@

 #include "sim.h"

-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
 * Public Functions
 ****************************************************************************/
@@ -47,6 +47,7 @@
 #include <nuttx/board.h>
 #include <nuttx/clock.h>
 #include <nuttx/timers/oneshot.h>
+#include <nuttx/wireless/ieee802154/ieee802154_loopback.h>

 #include "up_internal.h"
 #include "sim.h"
@@ -139,5 +140,15 @@ int sim_bringup(void)
    }
 #endif

+#ifdef CONFIG_IEEE802154_LOOPBACK
+  /* Initialize and register the IEEE802.15.4 MAC network loop device */
+
+  ret = ieee8021514_loopback();
+  if (ret < 0)
+    {
+      _err("ERROR: ieee8021514_loopback() failed: %d\n", ret);
+    }
+#endif
+
  return OK;
 }
@@ -77,6 +77,7 @@ CONFIG_HOST_X86_64=y
 CONFIG_SIM_X8664_SYSTEMV=y
 # CONFIG_SIM_X8664_MICROSOFT is not set
 CONFIG_SIM_WALLTIME=y
+CONFIG_SIM_NETDEV=y
 CONFIG_SIM_NET_HOST_ROUTE=y
 # CONFIG_SIM_NET_BRIDGE is not set
 # CONFIG_SIM_FRAMEBUFFER is not set
@@ -210,6 +211,8 @@ CONFIG_SCHED_WAITPID=y
 #
 # CONFIG_PTHREAD_MUTEX_TYPES is not set
 CONFIG_PTHREAD_MUTEX_ROBUST=y
+# CONFIG_PTHREAD_MUTEX_UNSAFE is not set
+# CONFIG_PTHREAD_MUTEX_BOTH is not set
 CONFIG_NPTHREAD_KEYS=4
 # CONFIG_PTHREAD_CLEANUP is not set
 # CONFIG_CANCELLATION_POINTS is not set
@@ -380,6 +383,7 @@ CONFIG_SERIAL_CONSOLE=y
 # CONFIG_PSEUDOTERM is not set
 # CONFIG_USBDEV is not set
 # CONFIG_USBHOST is not set
+# CONFIG_USBMISC is not set
 # CONFIG_HAVE_USBTRACE is not set
 # CONFIG_DRIVERS_WIRELESS is not set
 # CONFIG_DRIVERS_CONTACTLESS is not set
@@ -418,10 +422,12 @@ CONFIG_NET_GUARDSIZE=2
 # CONFIG_NET_ETHERNET is not set
 # CONFIG_NET_LOOPBACK is not set
 # CONFIG_NET_TUN is not set
+# CONFIG_NET_USRSOCK is not set

 #
 # Network Device Operations
 #
+# CONFIG_NETDEV_IOCTL is not set
 # CONFIG_NETDEV_PHY_IOCTL is not set

 #
@@ -453,11 +459,13 @@ CONFIG_NET_LOCAL_DGRAM=y
 # TCP/IP Networking
 #
 # CONFIG_NET_TCP is not set
+# CONFIG_NET_TCP_NO_STACK is not set

 #
 # UDP Networking
 #
 # CONFIG_NET_UDP is not set
+# CONFIG_NET_UDP_NO_STACK is not set

 #
 # IGMPv2 Client Support
@@ -472,6 +480,10 @@ CONFIG_NET_LOCAL_DGRAM=y
 # Network I/O Buffer Support
 #
 # CONFIG_NET_IOB is not set
+
+#
+# User-space networking stack API
+#
 # CONFIG_NET_ARCH_INCR32 is not set
 # CONFIG_NET_ARCH_CHKSUM is not set
 # CONFIG_NET_STATISTICS is not set
@@ -715,7 +727,6 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048
 # CONFIG_EXAMPLES_MM is not set
 # CONFIG_EXAMPLES_MODBUS is not set
 # CONFIG_EXAMPLES_MOUNT is not set
-# CONFIG_EXAMPLES_NRF24L01TERM is not set
 CONFIG_EXAMPLES_NSH=y
 # CONFIG_EXAMPLES_NULL is not set
 # CONFIG_EXAMPLES_NX is not set
@@ -760,6 +771,7 @@ CONFIG_EXAMPLES_UDGRAM_CLIENT_PRIORITY=100
 # CONFIG_EXAMPLES_USTREAM is not set
 # CONFIG_EXAMPLES_WATCHDOG is not set
 # CONFIG_EXAMPLES_WEBSERVER is not set
+# CONFIG_EXAMPLES_XBC_TEST is not set

 #
 # File System Utilities
@@ -77,6 +77,7 @@ CONFIG_HOST_X86_64=y
 CONFIG_SIM_X8664_SYSTEMV=y
 # CONFIG_SIM_X8664_MICROSOFT is not set
 CONFIG_SIM_WALLTIME=y
+CONFIG_SIM_NETDEV=y
 CONFIG_SIM_NET_HOST_ROUTE=y
 # CONFIG_SIM_NET_BRIDGE is not set
 # CONFIG_SIM_FRAMEBUFFER is not set
@@ -210,6 +211,8 @@ CONFIG_SCHED_WAITPID=y
 #
 # CONFIG_PTHREAD_MUTEX_TYPES is not set
 CONFIG_PTHREAD_MUTEX_ROBUST=y
+# CONFIG_PTHREAD_MUTEX_UNSAFE is not set
+# CONFIG_PTHREAD_MUTEX_BOTH is not set
 CONFIG_NPTHREAD_KEYS=4
 # CONFIG_PTHREAD_CLEANUP is not set
 # CONFIG_CANCELLATION_POINTS is not set
@@ -380,6 +383,7 @@ CONFIG_SERIAL_CONSOLE=y
 # CONFIG_PSEUDOTERM is not set
 # CONFIG_USBDEV is not set
 # CONFIG_USBHOST is not set
+# CONFIG_USBMISC is not set
 # CONFIG_HAVE_USBTRACE is not set
 # CONFIG_DRIVERS_WIRELESS is not set
 # CONFIG_DRIVERS_CONTACTLESS is not set
@@ -418,10 +422,12 @@ CONFIG_NET_GUARDSIZE=2
 # CONFIG_NET_ETHERNET is not set
 # CONFIG_NET_LOOPBACK is not set
 # CONFIG_NET_TUN is not set
+# CONFIG_NET_USRSOCK is not set

 #
 # Network Device Operations
 #
+# CONFIG_NETDEV_IOCTL is not set
 # CONFIG_NETDEV_PHY_IOCTL is not set

 #
@@ -453,11 +459,13 @@ CONFIG_NET_LOCAL_STREAM=y
 # TCP/IP Networking
 #
 # CONFIG_NET_TCP is not set
+# CONFIG_NET_TCP_NO_STACK is not set

 #
 # UDP Networking
 #
 # CONFIG_NET_UDP is not set
+# CONFIG_NET_UDP_NO_STACK is not set

 #
 # IGMPv2 Client Support
@@ -472,6 +480,10 @@ CONFIG_NET_LOCAL_STREAM=y
 # Network I/O Buffer Support
 #
 # CONFIG_NET_IOB is not set
+
+#
+# User-space networking stack API
+#
 # CONFIG_NET_ARCH_INCR32 is not set
 # CONFIG_NET_ARCH_CHKSUM is not set
 # CONFIG_NET_STATISTICS is not set
@@ -715,7 +727,6 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048
 # CONFIG_EXAMPLES_MM is not set
 # CONFIG_EXAMPLES_MODBUS is not set
 # CONFIG_EXAMPLES_MOUNT is not set
-# CONFIG_EXAMPLES_NRF24L01TERM is not set
 CONFIG_EXAMPLES_NSH=y
 # CONFIG_EXAMPLES_NULL is not set
 # CONFIG_EXAMPLES_NX is not set
@@ -755,6 +766,7 @@ CONFIG_EXAMPLES_USTREAM_ADDR="/dev/fifo"
 # CONFIG_EXAMPLES_USTREAM_USE_POLL is not set
 # CONFIG_EXAMPLES_WATCHDOG is not set
 # CONFIG_EXAMPLES_WEBSERVER is not set
+# CONFIG_EXAMPLES_XBC_TEST is not set

 #
 # File System Utilities
@@ -367,7 +367,7 @@ static void rng_buf_internal(FAR void *bytes, size_t nbytes)

 static void rng_init(void)
 {
-  crypinfo("Initializing RNG\n");
+  cryptinfo("Initializing RNG\n");

  memset(&g_rng, 0, sizeof(struct rng_s));
  sem_init(&g_rng.rd_sem, 0, 1);
@@ -552,6 +552,16 @@ if USBHOST
 source drivers/usbhost/Kconfig
 endif # USBHOST

+menuconfig USBMISC
+	bool "USB Miscellaneous drivers"
+	default n
+	---help---
+		USB Miscellaneous drivers.
+
+if USBMISC
+source drivers/usbmisc/Kconfig
+endif # USBMISC
+
 config HAVE_USBTRACE
 	bool
 	default n
@@ -72,6 +72,7 @@ include syslog$(DELIM)Make.defs
 include timers$(DELIM)Make.defs
 include usbdev$(DELIM)Make.defs
 include usbhost$(DELIM)Make.defs
+include usbmisc$(DELIM)Make.defs
 include usbmonitor$(DELIM)Make.defs
 include video$(DELIM)Make.defs
 include wireless$(DELIM)Make.defs
@@ -158,8 +158,8 @@ static const struct file_operations btn_fops =
  btn_open,  /* open */
  btn_close, /* close */
  btn_read,  /* read */
-  0,          /* write */
-  0,          /* seek */
+  NULL,      /* write */
+  NULL,      /* seek */
  btn_ioctl  /* ioctl */
 #ifndef CONFIG_DISABLE_POLL
  , btn_poll /* poll */
@@ -437,8 +437,8 @@ static void skel_receive(FAR struct skel_driver_s *priv)
              skel_transmit(priv);
            }
        }
-#endif
      else
+#endif
        {
          NETDEV_RXDROPPED(&priv->sk_dev);
        }
@@ -33,11 +33,11 @@ config BMP180
 		Enable driver support for the Bosch BMP180 barometer sensor.

 config HTS221
-	bool "ST HTS221 humidity sensor"
+	bool "STMicro HTS221 humidity sensor"
 	default n
 	select I2C
 	---help---
-		Enable driver support for the ST HTS221 humidity sensor.
+		Enable driver support for the STMicro HTS221 humidity sensor.

 if HTS221

@@ -56,11 +56,11 @@ config HTS221_NPOLLWAITERS
 endif # HTS221

 config SENSORS_L3GD20
-	bool "ST L3GD20 Gyroscope Sensor support"
+	bool "STMicro L3GD20 Gyroscope Sensor support"
 	default n
 	select SPI
 	---help---
-		Enable driver support for the ST L3GD20 gyroscope sensor.
+		Enable driver support for the STMicro L3GD20 gyroscope sensor.

 config SENSOR_KXTJ9
 	bool "Kionix KXTJ9 Accelerometer support"
@@ -75,15 +75,44 @@ config SENSOR_KXTJ9_I2C_BUS_SPEED

 endif # SENSOR_KXTJ9

+config LIS2DH
+	bool "STMicro LIS2DH device support"
+	default n
+	select I2C
+	---help---
+		Enable driver support for the STMicro LIS2DH accelerometer
+
+if LIS2DH
+
+config DEBUG_LIS2DH
+	bool "Debug support for the LIS2DH"
+	default n
+	---help---
+		Enables debug features for the LIS2DH
+
+config LIS2DH_NPOLLWAITERS
+	int "Number of waiters to poll"
+	default 2
+	---help---
+		Maximum number of threads that can be waiting on poll()
+
+config LIS2DH_DRIVER_SELFTEST
+	bool "Enable selftest in LIS2DH driver"
+	default n
+	---help---
+		Enable selftest in LIS2DH driver
+
+endif # LIS2DH
+
 config LIS3DSH
-	bool "STMicro LIS3DSH 3-Axis acclerometer support"
+	bool "STMicro LIS3DSH 3-Axis accelerometer support"
 	default n
 	select SPI
 	---help---
-		Enable driver support for the STMicro LIS3DSH 3-Axis acclerometer.
+		Enable driver support for the STMicro LIS3DSH 3-Axis accelerometer.

 config LIS331DL
-	bool "ST LIS331DL device support"
+	bool "STMicro LIS331DL device support"
 	default n
 	select I2C

@@ -106,6 +135,23 @@ config LSM9DS1_I2C_FREQUENCY
 	range 1 400000
 	depends on SN_LSM9DS1

+config LPS25H
+	bool "STMicro LPS25H pressure sensor"
+	default n
+	select I2C
+	---help---
+		Enable driver support for the STMicro LPS25H barometer sensor.
+
+if LPS25H
+
+config DEBUG_LPS25H
+	bool "Debug support for the LPS25H"
+	default n
+	---help---
+		Enables debug features for the LPS25H
+
+endif # LPS25H
+
 config MB7040
 	bool "MaxBotix MB7040 Sonar support"
 	default n
@@ -209,7 +255,7 @@ endif # SENSORS_ADXL345
 config MAX31855
 	bool "Maxim MAX31855 Driver"
 	default n
-        select SPI
+	select SPI
 	---help---
 		Enables support for the MAX31855 driver

@@ -229,7 +275,7 @@ config LIS3MDL
 	default n
 	select SPI
 	---help---
-		Enable driver support for the ST LIS3MDL 3-axis magnetometer.
+		Enable driver support for the STMicro LIS3MDL 3-axis magnetometer.

 config LM75
 	bool "STMicro LM-75 Temperature Sensor support"
@@ -1,7 +1,7 @@
 ############################################################################
 # drivers/sensors/Make.defs
 #
-#   Copyright (C) 2011-2012, 2015-2016 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2011-2012, 2015-2017 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt <gnutt@nuttx.org>
 #
 # Redistribution and use in source and binary forms, with or without
@@ -53,6 +53,10 @@ ifeq ($(CONFIG_SENSOR_KXTJ9),y)
  CSRCS += kxtj9.c
 endif

+ifeq ($(CONFIG_LIS2DH),y)
+  CSRCS += lis2dh.c
+endif
+
 ifeq ($(CONFIG_LIS3DSH),y)
  CSRCS += lis3dsh.c
 endif
@@ -65,6 +69,10 @@ ifeq ($(CONFIG_SN_LSM9DS1),y)
  CSRCS += lsm9ds1.c
 endif

+ifeq ($(CONFIG_LPS25H),y)
+  CSRCS += lps25h.c
+endif
+
 ifeq ($(CONFIG_ADXL345_I2C),y)
  CSRCS += adxl345_i2c.c
 endif
@@ -174,13 +174,11 @@ static const struct file_operations g_humidityops =
 #endif
 };

-static struct hts221_dev_s *g_humid_data;
-
 /****************************************************************************
 * Private Functions
 ****************************************************************************/

-static int hts221_do_transfer(FAR struct hts221_dev_s *dev,
+static int hts221_do_transfer(FAR struct hts221_dev_s *priv,
                              FAR struct i2c_msg_s *msgv,
                              size_t nmsg)
 {
@@ -189,7 +187,7 @@ static int hts221_do_transfer(FAR struct hts221_dev_s *dev,

  for (retries = 0; retries < HTS221_I2C_RETRIES; retries++)
    {
-      ret = I2C_TRANSFER(dev->i2c, msgv, nmsg);
+      ret = I2C_TRANSFER(priv->i2c, msgv, nmsg);
      if (ret >= 0)
        {
          return 0;
@@ -203,7 +201,7 @@ static int hts221_do_transfer(FAR struct hts221_dev_s *dev,
              break;
            }

-          ret = up_i2creset(dev->i2c);
+          ret = up_i2creset(priv->i2c);
          if (ret < 0)
            {
              hts221_dbg("up_i2creset failed: %d\n", ret);
@@ -217,51 +215,51 @@ static int hts221_do_transfer(FAR struct hts221_dev_s *dev,
  return ret;
 }

-static int32_t hts221_write_reg8(FAR struct hts221_dev_s *dev,
+static int32_t hts221_write_reg8(FAR struct hts221_dev_s *priv,
                                 const uint8_t *command)
 {
  struct i2c_msg_s msgv[2] =
  {
    {
-      .addr   = dev->addr,
+      .addr   = priv->addr,
      .flags  = 0,
      .buffer = (FAR void *)&command[0],
      .length = 1
    },
    {
-      .addr   = dev->addr,
+      .addr   = priv->addr,
      .flags  = I2C_M_NORESTART,
      .buffer = (FAR void *)&command[1],
      .length = 1
    }
  };

-  return hts221_do_transfer(dev, msgv, 2);
+  return hts221_do_transfer(priv, msgv, 2);
 }

-static int hts221_read_reg(FAR struct hts221_dev_s *dev,
+static int hts221_read_reg(FAR struct hts221_dev_s *priv,
                           FAR const uint8_t *command, FAR uint8_t *value)
 {
  struct i2c_msg_s msgv[2] =
  {
    {
-      .addr   = dev->addr,
+      .addr   = priv->addr,
      .flags  = 0,
      .buffer = (FAR void *)command,
      .length = 1
    },
    {
-      .addr   = dev->addr,
+      .addr   = priv->addr,
      .flags  = I2C_M_READ,
      .buffer = value,
      .length = 1
    }
  };

-  return hts221_do_transfer(dev, msgv, 2);
+  return hts221_do_transfer(priv, msgv, 2);
 }

-static int hts221_get_id(FAR struct hts221_dev_s *priv, uint8_t * value)
+static int hts221_get_id(FAR struct hts221_dev_s *priv, uint8_t *value)
 {
  int ret = OK;
  uint8_t cmd = HTS221_WHO_AM_I;
@@ -362,7 +360,7 @@ static int hts221_config_ctrl_reg2(FAR struct hts221_dev_s *priv,
 }

 static int hts221_config_ctrl_reg1(FAR struct hts221_dev_s *priv,
-                                   FAR hts221_settings_t * settings)
+                                   FAR hts221_settings_t *settings)
 {
  int ret = OK;
  uint8_t regval = 0;
@@ -420,7 +418,7 @@ static int hts221_power_on_off(FAR struct hts221_dev_s *priv, bool on)
 }

 static int hts221_config(FAR struct hts221_dev_s *priv,
-                         FAR hts221_settings_t * cfgr)
+                         FAR hts221_settings_t *cfgr)
 {
  int ret = OK;

@@ -477,7 +475,7 @@ static int hts221_start_conversion(FAR struct hts221_dev_s *priv)
 }

 static int hts221_check_status(FAR struct hts221_dev_s *priv,
-                               FAR hts221_status_t * status)
+                               FAR hts221_status_t *status)
 {
  int ret = OK;
  uint8_t addr = HTS221_STATUS_REG;
@@ -498,7 +496,7 @@ static int hts221_check_status(FAR struct hts221_dev_s *priv,
 }

 static int hts221_read_raw_data(FAR struct hts221_dev_s *priv,
-                                FAR hts221_raw_data_t * data)
+                                FAR hts221_raw_data_t *data)
 {
  int ret = OK;
  uint8_t addr_humid_low = HTS221_HUM_OUT_L;
@@ -1069,13 +1067,14 @@ out:

 static int hts221_int_handler(int irq, FAR void *context, FAR void *arg)
 {
-  if (!g_humid_data)
-    return OK;
+  FAR struct hts221_dev_s *priv = (FAR struct hts221_dev_s *)arg;

-  g_humid_data->int_pending = true;
+  DEBUGASSERT(priv != NULL);
+
+  priv->int_pending = true;
  hts221_dbg("Hts221 interrupt\n");
 #ifndef CONFIG_DISABLE_POLL
-  hts221_notify(g_humid_data);
+  hts221_notify(priv);
 #endif

  return OK;
@@ -1095,7 +1094,6 @@ int hts221_register(FAR const char *devpath, FAR struct i2c_master_s *i2c,
      return -ENOMEM;
    }

-  g_humid_data = priv;
  priv->addr   = addr;
  priv->i2c    = i2c;
  priv->config = config;
@@ -1125,7 +1123,7 @@ int hts221_register(FAR const char *devpath, FAR struct i2c_master_s *i2c,
      priv->config->irq_clear(priv->config);
    }

-  priv->config->irq_attach(priv->config, hts221_int_handler);
+  priv->config->irq_attach(priv->config, hts221_int_handler, priv);
  priv->config->irq_enable(priv->config, false);
  return OK;
 }
@@ -0,0 +1,29 @@
+#
+# For a description of the syntax of this configuration file,
+# see misc/tools/kconfig-language.txt.
+#
+
+comment "USB Miscellaneous drivers"
+
+config FUSB301
+	bool "Fairchild FUSB301 USB type-C controller support"
+	default n
+	select I2C
+	---help---
+		Enable device driver for Fairchild USB type-C controller
+
+if FUSB301
+
+config DEBUG_FUSB301
+	bool "Enable debug support for the FUSB301"
+	default n
+	---help---
+		Enables debug support for the FUSB301
+
+config FUSB301_NPOLLWAITERS
+	int "Number of waiters to poll"
+	default 2
+	---help---
+		Maximum number of threads that can be waiting on poll()
+
+endif
@@ -0,0 +1,49 @@
+############################################################################
+# drivers/usbmisc/Make.defs
+#
+#   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+ifeq ($(CONFIG_USBMISC),y)
+
+# Include USB miscellaneous drivers
+
+ifeq ($(CONFIG_FUSB301),y)
+  CSRCS += fusb301.c
+endif
+
+# Include USB miscellaneous build support
+
+DEPPATH += --dep-path usbmisc
+VPATH += :usbmisc
+CFLAGS += ${shell $(INCDIR) $(INCDIROPT) "$(CC)" $(TOPDIR)$(DELIM)drivers$(DELIM)usbmisc}
+endif
@@ -86,6 +86,7 @@
 #define _SPIBASE        (0x2100) /* SPI driver commands */
 #define _GPIOBASE       (0x2200) /* GPIO driver commands */
 #define _CLIOCBASE      (0x2300) /* Contactless modules ioctl commands */
+#define _USBCBASE       (0x2400) /* USB-C controller ioctl commands */

 /* boardctl() commands share the same number space */

@@ -371,19 +372,19 @@
 #define _LOOPIOCVALID(c)  (_IOC_TYPE(c)==_LOOPBASE)
 #define _LOOPIOC(nr)      _IOC(_LOOPBASE,nr)

-/* Modem driver ioctl definitions ********************************************/
+/* Modem driver ioctl definitions *******************************************/
 /* see nuttx/include/modem/ioctl.h */

 #define _MODEMIOCVALID(c) (_IOC_TYPE(c)==_MODEMBASE)
 #define _MODEMIOC(nr)     _IOC(_MODEMBASE,nr)

-/* I2C driver ioctl definitions **********************************************/
+/* I2C driver ioctl definitions *********************************************/
 /* see nuttx/include/i2c/i2c_master.h */

 #define _I2CIOCVALID(c)   (_IOC_TYPE(c)==_I2CBASE)
 #define _I2CIOC(nr)       _IOC(_I2CBASE,nr)

-/* SPI driver ioctl definitions **********************************************/
+/* SPI driver ioctl definitions *********************************************/
 /* see nuttx/include/spi/spi_transfer.h */

 #define _SPIIOCVALID(c)   (_IOC_TYPE(c)==_SPIBASE)
@@ -395,12 +396,18 @@
 #define _GPIOCVALID(c)    (_IOC_TYPE(c)==_GPIOBASE)
 #define _GPIOC(nr)        _IOC(_GPIOBASE,nr)

-/* Contactless driver ioctl definitions ****************************************/
+/* Contactless driver ioctl definitions *************************************/
 /* (see nuttx/include/contactless/ioctl.h */

 #define _CLIOCVALID(c)    (_IOC_TYPE(c)==_CLIOCBASE)
 #define _CLIOC(nr)        _IOC(_CLIOCBASE,nr)

+/* USB-C controller driver ioctl definitions ********************************/
+/* (see nuttx/include/usb/xxx.h */
+
+#define _USBCIOCVALID(c)  (_IOC_TYPE(c)==_USBCBASE)
+#define _USBCIOC(nr)      _IOC(_USBCBASE,nr)
+
 /* boardctl() command definitions *******************************************/

 #define _BOARDIOCVALID(c) (_IOC_TYPE(c)==_BOARDBASE)
@@ -483,7 +483,7 @@ EXTERN const net_ipv6addr_t g_ipv6_llnetmask;   /* Netmask for local link addres
 #endif

 /****************************************************************************
- * Function: net_ipv4addr_maskcmp and net_ipv6addr_maskcmp
+ * Name: net_ipv4addr_maskcmp and net_ipv6addr_maskcmp
 *
 * Description:
 *   Compare two IP addresses under a netmask.  The mask is used to mask
@@ -527,7 +527,86 @@ bool net_ipv6addr_maskcmp(const net_ipv6addr_t addr1,
 #endif

 /****************************************************************************
- * Function: net_ipaddr_mask
+ * Name: net_ipv6addr_prefixcmp
+ *
+ * Description:
+ *   Compare two IPv6 address prefixes.
+ *
+ ****************************************************************************/
+
+#define net_ipv6addr_prefixcmp(addr1, addr2, length) \
+  (memcmp(addr1, addr2, length >> 3) == 0)
+
+/****************************************************************************
+ * Name: net_is_addr_loopback
+ *
+ * Description:
+ *   Is Ithe Pv6 address a the loopback address?
+ *
+ ****************************************************************************/
+
+#define net_is_addr_loopback(a) \
+  ((a)[0] == 0 && (a)[1] == 0 && (a)[2] == 0 && (a)[3] == 0 && \
+   (a)[4] == 0 && (a)[5] == 0 && (a)[6] == 0 && (a)[7] == HTONS(0x0001))
+
+/****************************************************************************
+ * Name: net_is_addr_unspecified
+ *
+ * Description:
+ *   Is Ithe Pv6 address the unspecified address?
+ *
+ ****************************************************************************/
+
+#define net_is_addr_unspecified(a) \
+  ((a)[0] == 0 && (a)[1] == 0 && (a)[2] == 0 && (a)[3] == 0 && \
+   (a)[4] == 0 && (a)[5] == 0 && (a)[6] == 0 && (a)[7] == 0)
+
+/****************************************************************************
+ * Name: net_is_addr_mcast
+ *
+ * Description:
+ *   s address a multicast address? see RFC 3513.
+ *
+ ****************************************************************************/
+
+#define net_is_addr_mcast(a) (((a)[0] & HTONS(0xff00)) == HTONS(0xff00))
+
+/****************************************************************************
+ * Name: net_is_addr_linklocal_allnodes_mcast
+ *
+ * Description:
+ *   Is IPv6 address a the link local all-nodes multicast address?
+ *
+ ****************************************************************************/
+
+#define net_is_addr_linklocal_allnodes_mcast(a) \
+  ((a)[0] == HTONS(0xff02) && (a)[1] == 0 && (a)[2] == 0 && (a)[3] == 0 && \
+   (a)[4] == 0 && (a)[5] == 0 && (a)[6] == 0 && (a)[7] == HTONS(0x0001))
+
+/****************************************************************************
+ * Name: net_is_addr_linklocal_allrouters_mcast
+ *
+ * Description:
+ *   Is IPv6 address a the link local all-routers multicast address?
+ *
+ ****************************************************************************/
+
+#define net_is_addr_linklocal_allrouters_mcast(a) \
+  ((a)[0] == HTONS(0xff02) && (a)[1] == 0 && (a)[2] == 0 && (a)[3] == 0 && \
+   (a)[4] == 0 && (a)[5] == 0 && (a)[6] == 0 && (a)[7] == HTOS(0x0002))
+
+/****************************************************************************
+ * Name: net_is_addr_linklocal
+ *
+ * Description:
+ *   Checks whether the address a is link local.
+ *
+ ****************************************************************************/
+
+#define net_is_addr_linklocal(a) ((a)[0] == HTONS(0xfe80))
+
+/****************************************************************************
+ * Name: net_ipaddr_mask
 *
 * Description:
 *    Mask out the network part of an IP address, given the address and
@@ -79,7 +79,7 @@ enum net_lltype_e
  NET_LL_SLIP,         /* Serial Line Internet Protocol (SLIP) */
  NET_LL_TUN,          /* TUN Virtual Network Device */
  NET_LL_IEEE80211,    /* IEEE 802.11 */
-  NET_LL_IEEE805154    /* IEEE 802.15.4 MAC */
+  NET_LL_IEEE802154    /* IEEE 802.15.4 MAC */
 };

 /* This defines a bitmap big enough for one bit for each socket option */
--- a/Show More
+++ b/Show More