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arch/arm/src/stm32: Add support for the STM32F401xB and STM32F401xC families.

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This commit is contained in:
Gregory Nutt
2018-03-05 13:45:01 -06:00
parent cb31a37c69
commit 33adf2c64d
3 changed files with 67 additions and 9 deletions
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arch/arm/include/stm32/chip.h
+41 -4
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@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/include/stm32/chip.h
*
* Copyright (C) 2009, 2011-2014, 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011-2014, 2017-2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -1838,10 +1838,47 @@
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
/* STM23 F4 Family ******************************************************************/
#elif defined(CONFIG_ARCH_CHIP_STM32F401RC) /* LQFP64 package, 256Kb FLASH, 64Kb SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F4XXX 1 /* STM32F4xxxx family */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* One advanced timers TIM1 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 0 /* No basic timers */
# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */
# define STM32_NUSART 3 /* USART1, 2 and 6 */
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 1 /* One SDIO interface */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS (only) */
# define STM32_NGPIO 50 /* GPIOA-H */
# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */
# define STM32_NDAC 0 /* No DAC */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* No CRC */
# define STM32_NETHERNET 0 /* No Ethernet MAC */
# define STM32_NRNG 0 /* No Random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F401RE) /* LQFP64 package, 512Kb FLASH, 96KiB SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
@@ -1865,7 +1902,7 @@
# define STM32_NBTIM 0 /* No basic timers */
# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
# define STM32_NSPI 4 /* SPI1-4 */
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */
# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 0 /* No CAN */
arch/arm/src/stm32/Kconfig
+17
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@@ -965,10 +965,19 @@ config ARCH_CHIP_STM32F373VC
select STM32_STM32F37XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F401RC
bool "STM32F401RC"
select ARCH_CORTEXM4
select STM32_STM32F4XXX
select STM32_STM32F401xBC
select STM32_STM32F401
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F401RE
bool "STM32F401RE"
select ARCH_CORTEXM4
select STM32_STM32F4XXX
select STM32_STM32F401xDE
select STM32_STM32F401
select ARCH_HAVE_FPU
@@ -1530,6 +1539,14 @@ config STM32_STM32F4XXX
select STM32_HAVE_SPI2
select STM32_HAVE_I2C2
config STM32_STM32F401xBC
bool
default n
config STM32_STM32F401xDE
bool
default n
config STM32_STM32F401
bool
default n
arch/arm/src/stm32/stm32_allocateheap.c
+9 -5
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@@ -322,19 +322,21 @@
* 1) 112KiB of System SRAM beginning at address 0x2000:0000
* 2) 16KiB of System SRAM beginning at address 0x2001:c000
*
* The STM32F401 family is an exception and has only 96Kib total on one bank:
* The STM32F401 family is an exception and has only 64KiB or 96Kib total on one
* bank:
*
* 3) 96KiB of System SRAM beginning at address 0x2000:0000
* 3) 64KiB (STM32F401xB/C) or 96KiB (STM32401xD/E) of System SRAM beginning
* at address 0x2000:0000
*
* Members of the STM32F40xxx family have an additional 64Kib of CCM RAM
* for a total of 192KB.
*
* 4) 64Kib of CCM SRAM beginning at address 0x1000:0000
* 4) 64Kib of CCM SRAM beginning at address 0x1000:0000
*
* The STM32F427/437/429/439 parts have another 64KiB of System SRAM for a total
* of 256KiB.
*
* 5) 64Kib of System SRAM beginning at address 0x2002:0000
* 5) 64Kib of System SRAM beginning at address 0x2002:0000
*
* As determined by the linker script, g_heapbase lies in the 112KiB memory
* region and that extends to 0x2001:0000. But the first and second memory
@@ -360,7 +362,9 @@
/* Set the end of system SRAM */
# if defined(CONFIG_STM32_STM32F401)
# if defined(CONFIG_STM32_STM32F401xBC)
# define SRAM1_END 0x20010000
# elif defined(CONFIG_STM32_STM32F401xDE)
# define SRAM1_END 0x20018000
# elif defined(CONFIG_STM32_STM32F410)
# define SRAM1_END 0x20008000