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Merged nuttx/nuttx into master

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This commit is contained in:
Masayuki Ishikawa
2017-04-24 09:39:20 +09:00
parent 9fe8d0ccbb ca7d88f6bb
commit 33923d962d
294 changed files with 2175 additions and 1285 deletions
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arch/Kconfig
+4
View File
@@ -190,6 +190,10 @@ config ARCH_HAVE_RESET
bool
default n
config ARCH_HAVE_RTC_SUBSECONDS
bool
default n
config ARCH_USE_MMU
bool "Enable MMU"
default n
arch/arm/include/stm32f0/chip.h
+79 -6
View File
@@ -52,6 +52,7 @@
#if defined(CONFIG_ARCH_CHIP_STM32F051R8)
# define STM32F051x 1 /* STM32F051x family */
# undef STM32F072x /* Not STM32F072x family */
# undef STM32F091x /* Not STM32F091x family */
# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */
# define STM32F0_SRAM_SIZE (8*1024) /* 8Kb */
@@ -71,6 +72,7 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB)
# undef STM32F051x /* Not STM32F051x family */
# define STM32F072x 1 /* STM32F072x family */
# undef STM32F091x /* Not STM32F091x family */
# ifdef CONFIG_ARCH_CHIP_STM32F072C8
# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */
@@ -90,9 +92,9 @@
# define STM32F0_NCAN 1 /* One CAN controller */
# define STM32F0_NUSBDEV 1 /* One USB device controller */
# define STM32F0_NCEC 1 /* One HDMI-CEC controller */
# define STM32F0_NADC16 1 /* One 16-bit module */
# define STM32F0_NADC12 1 /* One 12-bit module */
# define STM32F0_NADCCHAN 10 /* Ten external channels */
# define STM32F0_NADCEXT 3 /* Three external channels */
# define STM32F0_NADCINT 3 /* Three internal channels */
# define STM32F0_NDAC 1 /* One DAC module */
# define STM32F0_NDACCHAN 2 /* Two DAC channels */
# define STM32F0_NCOMP 2 /* Two Analog Comparators */
@@ -102,6 +104,7 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB)
# undef STM32F051x /* Not STM32F051x family */
# define STM32F072x 1 /* STM32F072x family */
# undef STM32F091x /* Not STM32F091x family */
# ifdef CONFIG_ARCH_CHIP_STM32F072R8
# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */
@@ -121,9 +124,9 @@
# define STM32F0_NCAN 1 /* One CAN controller */
# define STM32F0_NUSBDEV 1 /* One USB device controller */
# define STM32F0_NCEC 1 /* One HDMI-CEC controller */
# define STM32F0_NADC16 1 /* One 16-bit module */
# define STM32F0_NADC12 1 /* One 12-bit module */
# define STM32F0_NADCCHAN 16 /* 16 external channels */
# define STM32F0_NADCEXT 3 /* Three external channels */
# define STM32F0_NADCINT 3 /* Three internal channels */
# define STM32F0_NDAC 1 /* One DAC module */
# define STM32F0_NDACCHAN 2 /* Two DAC channels */
# define STM32F0_NCOMP 2 /* Two Analog Comparators */
@@ -133,6 +136,7 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB)
# undef STM32F051x /* Not STM32F051x family */
# define STM32F072x 1 /* STM32F072x family */
# undef STM32F091x /* Not STM32F091x family */
# ifdef CONFIG_ARCH_CHIP_STM32F072V8
# define STM32F0_FLASH_SIZE (64*1024) /* 64Kb */
@@ -152,15 +156,84 @@
# define STM32F0_NCAN 1 /* One CAN controller */
# define STM32F0_NUSBDEV 1 /* One USB device controller */
# define STM32F0_NCEC 1 /* One HDMI-CEC controller */
# define STM32F0_NADC16 1 /* One 16-bit module */
# define STM32F0_NADC12 1 /* One 12-bit module */
# define STM32F0_NADCCHAN 16 /* 16 external channels */
# define STM32F0_NADCEXT 3 /* Three external channels */
# define STM32F0_NADCINT 3 /* Three internal channels */
# define STM32F0_NDAC 1 /* One DAC module */
# define STM32F0_NDACCHAN 2 /* Two DAC channels */
# define STM32F0_NCOMP 2 /* Two Analog Comparators */
# define STM32F0_NCAP 24 /* Capacitive sensing channels */
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC)
# undef STM32F051x /* Not STM32F051x family */
# undef STM32F072x /* Not STM32F072x family */
# define STM32F091x 1 /* STM32F091x family */
# ifdef CONFIG_ARCH_CHIP_STM32F091CB
# define STM32F0_FLASH_SIZE (128*1024) /* 128Kb */
# else
# define STM32F0_FLASH_SIZE (256*1024) /* 256Kb */
# endif
# define STM32F0_SRAM_SIZE (32*1024) /* 32Kb */
# define STM32F0_NATIM 1 /* One advanced timer TIM1 */
# define STM32F0_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
# define STM32F0_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
# define STM32F0_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32F0_NI2C 2 /* Two I2C modules */
# define STM32F0_NUSART 6 /* Six USARTs modules */
# define STM32F0_NCAN 1 /* One CAN controller */
# define STM32F0_NUSBDEV 0 /* No USB device controller */
# define STM32F0_NCEC 1 /* One HDMI-CEC controller */
# define STM32F0_NADC12 1 /* One 12-bit module */
# define STM32F0_NADCCHAN 10 /* 10 external channels */
# define STM32F0_NADCINT 3 /* Three internal channels */
# define STM32F0_NDAC 1 /* One DAC module */
# define STM32F0_NDACCHAN 2 /* Two DAC channels */
# define STM32F0_NCOMP 2 /* Two Analog Comparators */
# define STM32F0_NCAP 17 /* Capacitive sensing channels */
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) \
|| defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
# undef STM32F051x /* Not STM32F051x family */
# undef STM32F072x /* Not STM32F072x family */
# define STM32F091x 1 /* STM32F091x family */
# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB)
# define STM32F0_FLASH_SIZE (128*1024) /* 128Kb */
# else
# define STM32F0_FLASH_SIZE (256*1024) /* 256Kb */
# endif
# define STM32F0_SRAM_SIZE (32*1024) /* 32Kb */
# define STM32F0_NATIM 1 /* One advanced timer TIM1 */
# define STM32F0_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
# define STM32F0_NGTIM32 1 /* 32-bit general up/down timers TIM2 */
# define STM32F0_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
# define STM32F0_NSPI 2 /* Two SPI modules (SPI or I2S) */
# define STM32F0_NI2S 2 /* Two I2S modules (SPI or I2S) */
# define STM32F0_NI2C 2 /* Two I2C modules */
# define STM32F0_NUSART 8 /* Eight USARTs modules */
# define STM32F0_NCAN 1 /* One CAN controller */
# define STM32F0_NUSBDEV 0 /* No USB device controller */
# define STM32F0_NCEC 1 /* One HDMI-CEC controller */
# define STM32F0_NADC12 1 /* One 12-bit module */
# define STM32F0_NADCCHAN 16 /* 16 external channels */
# define STM32F0_NADCINT 3 /* Three internal channels */
# define STM32F0_NDAC 1 /* One DAC module */
# define STM32F0_NDACCHAN 2 /* Two DAC channels */
# define STM32F0_NCOMP 2 /* Two Analog Comparators */
# if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
# define STM32F0_NCAP 24 /* Capacitive sensing channels */
# else
# define STM32F0_NCAP 18 /* Capacitive sensing channels */
# endif
# define STM32F0_NPORTS 6 /* Six GPIO ports, GPIOA-F */
#else
# error "Unsupported STM32F0xx chip"
#endif
arch/arm/src/c5471/c5471_ethernet.c
+1 -1
View File
@@ -2364,7 +2364,7 @@ static void c5471_reset(struct c5471_driver_s *priv)
static void c5471_macassign(struct c5471_driver_s *priv)
{
struct net_driver_s *dev = &priv->c_dev;
uint8_t *mptr = dev->d_mac.ether_addr_octet;
uint8_t *mptr = dev->d_mac.ether.ether_addr_octet;
register uint32_t tmp;
ninfo("MAC: %0x:%0x:%0x:%0x:%0x:%0x\n",
arch/arm/src/common/up_udelay.c
+1 -1
View File
@@ -59,7 +59,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***
arch/arm/src/kinetis/kinetis_enet.c
+2 -2
View File
@@ -1125,7 +1125,7 @@ static int kinetis_ifup(struct net_driver_s *dev)
{
FAR struct kinetis_driver_s *priv =
(FAR struct kinetis_driver_s *)dev->d_private;
uint8_t *mac = dev->d_mac.ether_addr_octet;
uint8_t *mac = dev->d_mac.ether.ether_addr_octet;
uint32_t regval;
int ret;
@@ -2144,7 +2144,7 @@ int kinetis_netinitialize(int intf)
uidl = getreg32(KINETIS_SIM_UIDL);
uidml = getreg32(KINETIS_SIM_UIDML);
mac = priv->dev.d_mac.ether_addr_octet;
mac = priv->dev.d_mac.ether.ether_addr_octet;
uidml |= 0x00000200;
uidml &= 0x0000FEFF;
arch/arm/src/lpc11xx/Kconfig
+1 -1
View File
@@ -222,7 +222,7 @@ config CAN_SAM
The bus is sampled 3 times (recommended for low to medium speed buses to spikes on the bus-line).
config CAN_LOOPBACK
bool "CAN looopback mode"
bool "CAN loopback mode"
default n
---help---
Enable CAN loopback mode
arch/arm/src/lpc17xx/Kconfig
+1 -1
View File
@@ -589,7 +589,7 @@ config CAN_SAM
The bus is sampled 3 times (recommended for low to medium speed buses to spikes on the bus-line).
config CAN_LOOPBACK
bool "CAN looopback mode"
bool "CAN loopback mode"
default n
---help---
Enable CAN loopback mode
arch/arm/src/lpc17xx/lpc17_ethernet.c
+6 -6
View File
@@ -1591,16 +1591,16 @@ static int lpc17_ifup(struct net_driver_s *dev)
/* Configure the MAC station address */
regval = (uint32_t)priv->lp_dev.d_mac.ether_addr_octet[5] << 8 |
(uint32_t)priv->lp_dev.d_mac.ether_addr_octet[4];
regval = (uint32_t)priv->lp_dev.d_mac.ether.ether_addr_octet[5] << 8 |
(uint32_t)priv->lp_dev.d_mac.ether.ether_addr_octet[4];
lpc17_putreg(regval, LPC17_ETH_SA0);
regval = (uint32_t)priv->lp_dev.d_mac.ether_addr_octet[3] << 8 |
(uint32_t)priv->lp_dev.d_mac.ether_addr_octet[2];
regval = (uint32_t)priv->lp_dev.d_mac.ether.ether_addr_octet[3] << 8 |
(uint32_t)priv->lp_dev.d_mac.ether.ether_addr_octet[2];
lpc17_putreg(regval, LPC17_ETH_SA1);
regval = (uint32_t)priv->lp_dev.d_mac.ether_addr_octet[1] << 8 |
(uint32_t)priv->lp_dev.d_mac.ether_addr_octet[0];
regval = (uint32_t)priv->lp_dev.d_mac.ether.ether_addr_octet[1] << 8 |
(uint32_t)priv->lp_dev.d_mac.ether.ether_addr_octet[0];
lpc17_putreg(regval, LPC17_ETH_SA2);
#ifdef CONFIG_NET_ICMPv6
arch/arm/src/lpc43xx/lpc43_ethernet.c
+9 -9
View File
@@ -3535,22 +3535,22 @@ static void lpc43_macaddress(FAR struct lpc43_ethmac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address high register */
regval = ((uint32_t)dev->d_mac.ether_addr_octet[5] << 8) |
(uint32_t)dev->d_mac.ether_addr_octet[4];
regval = ((uint32_t)dev->d_mac.ether.ether_addr_octet[5] << 8) |
(uint32_t)dev->d_mac.ether.ether_addr_octet[4];
lpc43_putreg(regval, LPC43_ETH_MACA0HI);
/* Set the MAC address low register */
regval = ((uint32_t)dev->d_mac.ether_addr_octet[3] << 24) |
((uint32_t)dev->d_mac.ether_addr_octet[2] << 16) |
((uint32_t)dev->d_mac.ether_addr_octet[1] << 8) |
(uint32_t)dev->d_mac.ether_addr_octet[0];
regval = ((uint32_t)dev->d_mac.ether.ether_addr_octet[3] << 24) |
((uint32_t)dev->d_mac.ether.ether_addr_octet[2] << 16) |
((uint32_t)dev->d_mac.ether.ether_addr_octet[1] << 8) |
(uint32_t)dev->d_mac.ether.ether_addr_octet[0];
lpc43_putreg(regval, LPC43_ETH_MACA0LO);
}
arch/arm/src/sam34/Kconfig
+35 -1
View File
@@ -572,7 +572,6 @@ config SAM34_TWIS
bool
default n
config SAM34_TWIM0
bool "Two-wire Master Interface 0 (TWIM0)"
default n
@@ -1142,6 +1141,41 @@ config SAM34_SPI_REGDEBUG
endmenu # AT91SAM3/4 SPI device driver options
endif # SAM34_SPI0 || SAM34_SPI1
if SAM34_TWIM
menu "AT91SAM3/4 TWI master device driver options"
config SAM34_TWIM0_FREQUENCY
int "TWI0 Frequency"
default 100000
depends on SAM34_TWIM0
config SAM34_TWIM1_FREQUENCY
int "TWI1 Frequency"
default 100000
depends on SAM34_TWIM1
config SAM34_TWIM2_FREQUENCY
int "TWI2 Frequency"
default 100000
depends on SAM34_TWIM2
config SAM34_TWIM3_FREQUENCY
int "TWI3 Frequency"
default 100000
depends on SAM34_TWIM3
config SAM34_TWI_REGDEBUG
bool "TWI register level debug"
depends on DEBUG_I2C_INFO
default n
---help---
Output detailed register-level TWI device debug information.
Very invasive! Requires also CONFIG_DEBUG_I2C_INFO.
endmenu # TWI device driver options
endif # SAM34_TWIM
menu "AT91SAM3/4 EMAC device driver options"
depends on SAM34_EMAC
arch/arm/src/sam34/sam_emac.c
+9 -9
View File
@@ -3416,20 +3416,20 @@ static void sam_macaddress(struct sam_emac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address */
regval = (uint32_t)dev->d_mac.ether_addr_octet[0] |
(uint32_t)dev->d_mac.ether_addr_octet[1] << 8 |
(uint32_t)dev->d_mac.ether_addr_octet[2] << 16 |
(uint32_t)dev->d_mac.ether_addr_octet[3] << 24;
regval = (uint32_t)dev->d_mac.ether.ether_addr_octet[0] |
(uint32_t)dev->d_mac.ether.ether_addr_octet[1] << 8 |
(uint32_t)dev->d_mac.ether.ether_addr_octet[2] << 16 |
(uint32_t)dev->d_mac.ether.ether_addr_octet[3] << 24;
sam_putreg(priv, SAM_EMAC_SAB1, regval);
regval = (uint32_t)dev->d_mac.ether_addr_octet[4] |
(uint32_t)dev->d_mac.ether_addr_octet[5] << 8;
regval = (uint32_t)dev->d_mac.ether.ether_addr_octet[4] |
(uint32_t)dev->d_mac.ether.ether_addr_octet[5] << 8;
sam_putreg(priv, SAM_EMAC_SAT1, regval);
}
arch/arm/src/sam34/sam_twi.c
+16 -14
View File
@@ -71,19 +71,21 @@
#include "sam_gpio.h"
#include "sam_twi.h"
#if defined(CONFIG_SAM34_TWI0) || defined(CONFIG_SAM34_TWI1)
/* REVISIT: Missing support for TWI2 master */
#if defined(CONFIG_SAM34_TWIM0) || defined(CONFIG_SAM34_TWIM1)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ***************************************************************/
#ifndef CONFIG_SAM34_TWI0_FREQUENCY
# define CONFIG_SAM34_TWI0_FREQUENCY 100000
#ifndef CONFIG_SAM34_TWIM0_FREQUENCY
# define CONFIG_SAM34_TWIM0_FREQUENCY 100000
#endif
#ifndef CONFIG_SAM34_TWI1_FREQUENCY
# define CONFIG_SAM34_TWI1_FREQUENCY 100000
#ifndef CONFIG_SAM34_TWIM1_FREQUENCY
# define CONFIG_SAM34_TWIM1_FREQUENCY 100000
#endif
#ifndef CONFIG_DEBUG_I2C_INFO
@@ -187,11 +189,11 @@ static void twi_hw_initialize(struct twi_dev_s *priv, unsigned int pid,
* Private Data
****************************************************************************/
#ifdef CONFIG_SAM34_TWI0
#ifdef CONFIG_SAM34_TWIM0
static struct twi_dev_s g_twi0;
#endif
#ifdef CONFIG_SAM34_TWI1
#ifdef CONFIG_SAM34_TWIM1
static struct twi_dev_s g_twi1;
#endif
@@ -430,7 +432,7 @@ static void twi_wakeup(struct twi_dev_s *priv, int result)
*
****************************************************************************/
static int twi_interrupt(int irq, FAR void *context, FAR void *arg);
static int twi_interrupt(int irq, FAR void *context, FAR void *arg)
{
struct twi_dev_s *priv = (struct twi_dev_s *)arg;
struct i2c_msg_s *msg;
@@ -901,7 +903,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
flags = enter_critical_section();
#ifdef CONFIG_SAM34_TWI0
#ifdef CONFIG_SAM34_TWIM0
if (bus == 0)
{
/* Set up TWI0 register base address and IRQ number */
@@ -922,18 +924,18 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
/* Select the TWI frequency, and peripheral ID */
frequency = CONFIG_SAM34_TWI0_FREQUENCY;
frequency = CONFIG_SAM34_TWIM0_FREQUENCY;
pid = SAM_PID_TWI0;
}
else
#endif
#ifdef CONFIG_SAM34_TWI1
#ifdef CONFIG_SAM34_TWIM1
if (bus == 1)
{
/* Set up TWI1 register base address and IRQ number */
priv = &g_twi1;
priv->base = SAM_TWI0_BASE;
priv->base = SAM_TWI1_BASE;
priv->irq = SAM_IRQ_TWI1;
priv->twi = 1;
@@ -948,7 +950,7 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
/* Select the TWI frequency, and peripheral ID */
frequency = CONFIG_SAMA5_TWI1_FREQUENCY;
frequency = CONFIG_SAM34_TWIM1_FREQUENCY;
pid = SAM_PID_TWI1;
}
else
@@ -1029,4 +1031,4 @@ int sam_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
return OK;
}
#endif /* CONFIG_SAM34_TWI0 || CONFIG_SAM34_TWI1 */
#endif /* CONFIG_SAM34_TWIM0 || CONFIG_SAM34_TWIM1 */
arch/arm/src/sama5/sam_emaca.c
+9 -9
View File
@@ -3458,20 +3458,20 @@ static void sam_macaddress(struct sam_emac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address */
regval = (uint32_t)dev->d_mac.ether_addr_octet[0] |
(uint32_t)dev->d_mac.ether_addr_octet[1] << 8 |
(uint32_t)dev->d_mac.ether_addr_octet[2] << 16 |
(uint32_t)dev->d_mac.ether_addr_octet[3] << 24;
regval = (uint32_t)dev->d_mac.ether.ether_addr_octet[0] |
(uint32_t)dev->d_mac.ether.ether_addr_octet[1] << 8 |
(uint32_t)dev->d_mac.ether.ether_addr_octet[2] << 16 |
(uint32_t)dev->d_mac.ether.ether_addr_octet[3] << 24;
sam_putreg(priv, SAM_EMAC_SA1B, regval);
regval = (uint32_t)dev->d_mac.ether_addr_octet[4] |
(uint32_t)dev->d_mac.ether_addr_octet[5] << 8;
regval = (uint32_t)dev->d_mac.ether.ether_addr_octet[4] |
(uint32_t)dev->d_mac.ether.ether_addr_octet[5] << 8;
sam_putreg(priv, SAM_EMAC_SA1T, regval);
}
arch/arm/src/sama5/sam_emacb.c
+9 -9
View File
@@ -4106,20 +4106,20 @@ static void sam_macaddress(struct sam_emac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address */
regval = (uint32_t)dev->d_mac.ether_addr_octet[0] |
(uint32_t)dev->d_mac.ether_addr_octet[1] << 8 |
(uint32_t)dev->d_mac.ether_addr_octet[2] << 16 |
(uint32_t)dev->d_mac.ether_addr_octet[3] << 24;
regval = (uint32_t)dev->d_mac.ether.ether_addr_octet[0] |
(uint32_t)dev->d_mac.ether.ether_addr_octet[1] << 8 |
(uint32_t)dev->d_mac.ether.ether_addr_octet[2] << 16 |
(uint32_t)dev->d_mac.ether.ether_addr_octet[3] << 24;
sam_putreg(priv, SAM_EMAC_SAB1_OFFSET, regval);
regval = (uint32_t)dev->d_mac.ether_addr_octet[4] |
(uint32_t)dev->d_mac.ether_addr_octet[5] << 8;
regval = (uint32_t)dev->d_mac.ether.ether_addr_octet[4] |
(uint32_t)dev->d_mac.ether.ether_addr_octet[5] << 8;
sam_putreg(priv, SAM_EMAC_SAT1_OFFSET, regval);
}
arch/arm/src/sama5/sam_gmac.c
+9 -9
View File
@@ -3506,20 +3506,20 @@ static void sam_macaddress(struct sam_gmac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address */
regval = (uint32_t)dev->d_mac.ether_addr_octet[0] |
(uint32_t)dev->d_mac.ether_addr_octet[1] << 8 |
(uint32_t)dev->d_mac.ether_addr_octet[2] << 16 |
(uint32_t)dev->d_mac.ether_addr_octet[3] << 24;
regval = (uint32_t)dev->d_mac.ether.ether_addr_octet[0] |
(uint32_t)dev->d_mac.ether.ether_addr_octet[1] << 8 |
(uint32_t)dev->d_mac.ether.ether_addr_octet[2] << 16 |
(uint32_t)dev->d_mac.ether.ether_addr_octet[3] << 24;
sam_putreg(priv, SAM_GMAC_SAB1, regval);
regval = (uint32_t)dev->d_mac.ether_addr_octet[4] |
(uint32_t)dev->d_mac.ether_addr_octet[5] << 8;
regval = (uint32_t)dev->d_mac.ether.ether_addr_octet[4] |
(uint32_t)dev->d_mac.ether.ether_addr_octet[5] << 8;
sam_putreg(priv, SAM_GMAC_SAT1, regval);
}
arch/arm/src/samv7/sam_emac.c
+13 -13
View File
@@ -4668,20 +4668,20 @@ static void sam_macaddress(struct sam_emac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address */
regval = (uint32_t)dev->d_mac.ether_addr_octet[0] |
(uint32_t)dev->d_mac.ether_addr_octet[1] << 8 |
(uint32_t)dev->d_mac.ether_addr_octet[2] << 16 |
(uint32_t)dev->d_mac.ether_addr_octet[3] << 24;
regval = (uint32_t)dev->d_mac.ether.ether_addr_octet[0] |
(uint32_t)dev->d_mac.ether.ether_addr_octet[1] << 8 |
(uint32_t)dev->d_mac.ether.ether_addr_octet[2] << 16 |
(uint32_t)dev->d_mac.ether.ether_addr_octet[3] << 24;
sam_putreg(priv, SAM_EMAC_SAB1_OFFSET, regval);
regval = (uint32_t)dev->d_mac.ether_addr_octet[4] |
(uint32_t)dev->d_mac.ether_addr_octet[5] << 8;
regval = (uint32_t)dev->d_mac.ether.ether_addr_octet[4] |
(uint32_t)dev->d_mac.ether.ether_addr_octet[5] << 8;
sam_putreg(priv, SAM_EMAC_SAT1_OFFSET, regval);
}
@@ -5160,13 +5160,13 @@ int sam_emac_setmacaddr(int intf, uint8_t mac[6])
/* Copy the MAC address into the device structure */
dev = &priv->dev;
memcpy(dev->d_mac.ether_addr_octet, mac, 6);
memcpy(dev->d_mac.ether.ether_addr_octet, mac, 6);
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
return OK;
}
arch/arm/src/stm32/Kconfig
+1
View File
@@ -6362,6 +6362,7 @@ config STM32_HAVE_RTC_COUNTER
config STM32_HAVE_RTC_SUBSECONDS
bool
select ARCH_HAVE_RTC_SUBSECONDS
default n
config RTC_MAGIC_REG
arch/arm/src/stm32/stm32_eth.c
+9 -9
View File
@@ -3674,22 +3674,22 @@ static void stm32_macaddress(FAR struct stm32_ethmac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address high register */
regval = ((uint32_t)dev->d_mac.ether_addr_octet[5] << 8) |
(uint32_t)dev->d_mac.ether_addr_octet[4];
regval = ((uint32_t)dev->d_mac.ether.ether_addr_octet[5] << 8) |
(uint32_t)dev->d_mac.ether.ether_addr_octet[4];
stm32_putreg(regval, STM32_ETH_MACA0HR);
/* Set the MAC address low register */
regval = ((uint32_t)dev->d_mac.ether_addr_octet[3] << 24) |
((uint32_t)dev->d_mac.ether_addr_octet[2] << 16) |
((uint32_t)dev->d_mac.ether_addr_octet[1] << 8) |
(uint32_t)dev->d_mac.ether_addr_octet[0];
regval = ((uint32_t)dev->d_mac.ether.ether_addr_octet[3] << 24) |
((uint32_t)dev->d_mac.ether.ether_addr_octet[2] << 16) |
((uint32_t)dev->d_mac.ether.ether_addr_octet[1] << 8) |
(uint32_t)dev->d_mac.ether.ether_addr_octet[0];
stm32_putreg(regval, STM32_ETH_MACA0LR);
}
arch/arm/src/stm32/stm32_rtcc.c
+34
View File
@@ -928,6 +928,40 @@ int up_rtc_getdatetime(FAR struct tm *tp)
}
#endif
/************************************************************************************
* Name: up_rtc_getdatetime_with_subseconds
*
* Description:
* Get the current date and time from the date/time RTC. This interface
* is only supported by the date/time RTC hardware implementation.
* It is used to replace the system timer. It is only used by the RTOS during
* initialization to set up the system time when CONFIG_RTC and CONFIG_RTC_DATETIME
* are selected (and CONFIG_RTC_HIRES is not).
*
* NOTE: This interface exposes sub-second accuracy capability of RTC hardware.
* This interface allow maintaining timing accuracy when system time needs constant
* resynchronization with RTC, for example on MCU with low-power state that
* stop system timer.
*
* Input Parameters:
* tp - The location to return the high resolution time value.
* nsec - The location to return the subsecond time value.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
************************************************************************************/
#ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS
# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS
# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS."
# endif
int up_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec)
{
return stm32_rtc_getdatetime_with_subseconds(tp, nsec);
}
#endif
/************************************************************************************
* Name: stm32_rtc_setdatetime
*
arch/arm/src/stm32f0/chip/stm32f05xf07x_memorymap.h → arch/arm/src/stm32f0/chip/stm32f05xf07xf09x_memorymap.h
+4 -4
View File
@@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f05xf07x_memorymap.h
* arch/arm/src/stm32f0/chip/stm32f05xf07xf09x_memorymap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -34,8 +34,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_ST32F05XF07X_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_ST32F05XF07X_MEMORYMAP_H
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H
/************************************************************************************
* Pre-processor Definitions
@@ -154,4 +154,4 @@
#define STM32F0_SCS_BASE 0xe000e000
#define STM32F0_DEBUGMCU_BASE 0xe0042000
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_ST32F05XF07X_MEMORYMAP_H */
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H */
arch/arm/src/stm32f0/chip/stm32f09x_pinmap.h
+430
View File
@@ -0,0 +1,430 @@
/************************************************************************************
* arch/arm/src/stm32f0/chip/stm32f09x_pinmap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Alan Carvalho de Assis <acassis@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_STM32F09X_PINMAP_H
#define __ARCH_ARM_SRC_STM32F0_CHIP_STM32F09X_PINMAP_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "stm32f0_gpio.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file. For example, if
* CAN1_RX connects vis PD0 on some board, then the following definition should
* appear inthe board.h header file for that board:
*
* #define GPIO_CAN1_RX GPIO_CAN1_RX_1
*
* The driver will then automatically configre PD0 as the CAN1 RX pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file.
*/
/* ADC */
#define GPIO_ADC_IN0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0)
#define GPIO_ADC_IN1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1)
#define GPIO_ADC_IN2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2)
#define GPIO_ADC_IN3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3)
#define GPIO_ADC_IN4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4)
#define GPIO_ADC_IN5 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5)
#define GPIO_ADC_IN6 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6)
#define GPIO_ADC_IN7 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7)
#define GPIO_ADC_IN8 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0)
#define GPIO_ADC_IN9 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1)
#define GPIO_ADC_IN10 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0)
#define GPIO_ADC_IN11 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1)
#define GPIO_ADC_IN12 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2)
#define GPIO_ADC_IN13 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3)
#define GPIO_ADC_IN14 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4)
#define GPIO_ADC_IN15 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5)
/* CAN */
#define GPIO_CAN_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN0)
#define GPIO_CAN_RX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_CAN_RX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN8)
#define GPIO_CAN_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN1)
#define GPIO_CAN_TX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_CAN_TX_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN9)
/* HDMI-CEC */
#define GPIO_CEC_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_CEC_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN8)
#define GPIO_CEC_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN5)
/* Analog Comparators */
#define GPIO_COMP1_OUT_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN0)
#define GPIO_COMP1_OUT_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_COMP1_OUT_3 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_COMP2_OUT_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_COMP2_OUT_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_COMP2_OUT_3 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN7)
/* CRS */
#define GPIO_CRS_SYNC_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN15)
#define GPIO_CRS_SYNC_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTF | GPIO_PIN0)
#define GPIO_CRS_SYNC_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN8)
/* Events */
#define GPIO_EVENTOUT_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_EVENTOUT_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_EVENTOUT_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_EVENTOUT_4 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN0)
#define GPIO_EVENTOUT_5 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN11)
#define GPIO_EVENTOUT_6 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN0)
#define GPIO_EVENTOUT_7 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN1)
#define GPIO_EVENTOUT_8 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN2)
#define GPIO_EVENTOUT_9 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN3)
#define GPIO_EVENTOUT_10 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN4)
#define GPIO_EVENTOUT_11 (GPIO_ALT | GPIO_AF0 | GPIO_PORTF | GPIO_PIN2)
#define GPIO_EVENTOUT_12 (GPIO_ALT | GPIO_AF0 | GPIO_PORTF | GPIO_PIN3)
#define GPIO_EVENTOUT_13 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_EVENTOUT_14 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_EVENTOUT_15 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN0)
#define GPIO_EVENTOUT_16 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN1)
#define GPIO_EVENTOUT_17 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_EVENTOUT_18 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_EVENTOUT_19 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN8)
#define GPIO_EVENTOUT_20 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN9)
#define GPIO_EVENTOUT_21 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_EVENTOUT_22 (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN7)
/* I2C */
#define GPIO_I2C1_SCL_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN6)
#define GPIO_I2C1_SCL_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN8)
#define GPIO_I2C1_SDA_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN7)
#define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN9)
#define GPIO_I2C1_SMBA (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_I2C2_SCL_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_I2C2_SCL_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_I2C2_SDA_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN11)
#define GPIO_I2C2_SDA_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN14)
/* I2S */
#define GPIO_I2S1_CK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN5)
#define GPIO_I2S1_CK_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_I2S1_CK_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN13)
#define GPIO_I2S1_MCK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_I2S1_MCK_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_I2S1_MCK_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN14)
#define GPIO_I2S1_SD_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_I2S1_SD_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_I2S1_SD_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN15)
#define GPIO_I2S1_WS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_I2S1_WS_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_I2S1_WS_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN12)
#define GPIO_I2S2_CK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_I2S2_CK_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN1)
#define GPIO_I2S2_CK_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_I2S2_MCK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_I2S2_MCK_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN2)
#define GPIO_I2S2_MCK_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN3)
#define GPIO_I2S2_SD_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_I2S2_SD_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN3)
#define GPIO_I2S2_SD_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN4)
#define GPIO_I2S2_WS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_I2S2_WS_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN0)
#define GPIO_I2S2_WS_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN9)
/* IR */
#define GPIO_IR_OUT_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN9)
#define GPIO_IR_OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN13)
/* Clock output */
#define GPIO_MCO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN8)
/* SPI */
#define GPIO_SPI1_MISO_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_SPI1_MISO_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_SPI1_MISO_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN14)
#define GPIO_SPI1_MOSI_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_SPI1_MOSI_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_SPI1_MOSI_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN15)
#define GPIO_SPI1_NSS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_SPI1_NSS_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_SPI1_NSS_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN12)
#define GPIO_SPI1_SCK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN5)
#define GPIO_SPI1_SCK_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_SPI1_SCK_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN13)
#define GPIO_SPI2_MISO_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_SPI2_MISO_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN2)
#define GPIO_SPI2_MISO_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN3)
#define GPIO_SPI2_MOSI_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_SPI2_MOSI_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN3)
#define GPIO_SPI2_MOSI_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN4)
#define GPIO_SPI2_NSS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_SPI2_NSS_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN0)
#define GPIO_SPI2_NSS_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN9)
#define GPIO_SPI2_SCK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_SPI2_SCK_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN1)
#define GPIO_SPI2_SCK_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN10)
/* SWD */
#define GPIO_SWCLK (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN14)
#define GPIO_SWDIO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN13)
/* Timers */
#define GPIO_TIM1_BKIN_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN15)
#define GPIO_TIM1_BKIN_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_TIM1_BKIN_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_TIM1_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN9)
#define GPIO_TIM1_CH1_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN8)
#define GPIO_TIM1_CH1N_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN8)
#define GPIO_TIM1_CH1N_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_TIM1_CH1N_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_TIM1_CH2_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN11)
#define GPIO_TIM1_CH2_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN9)
#define GPIO_TIM1_CH2N_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN10)
#define GPIO_TIM1_CH2N_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN0)
#define GPIO_TIM1_CH2N_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_TIM1_CH3_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN13)
#define GPIO_TIM1_CH3_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN10)
#define GPIO_TIM1_CH3N_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN12)
#define GPIO_TIM1_CH3N_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN1)
#define GPIO_TIM1_CH3N_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_TIM1_CH4_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN14)
#define GPIO_TIM1_CH4_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_TIM1_ETR_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN7)
#define GPIO_TIM1_ETR_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_TIM2_CH1_ETR_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN0)
#define GPIO_TIM2_CH1_ETR_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_TIM2_CH1_ETR_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN5)
#define GPIO_TIM2_CH2_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_TIM2_CH2_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_TIM2_CH3_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_TIM2_CH3_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_TIM2_CH4_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN3)
#define GPIO_TIM2_CH4_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN11)
#define GPIO_TIM3_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN6)
#define GPIO_TIM3_CH1_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN3)
#define GPIO_TIM3_CH1_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_TIM3_CH1_4 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_TIM3_CH2_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN7)
#define GPIO_TIM3_CH2_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN4)
#define GPIO_TIM3_CH2_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_TIM3_CH2_4 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_TIM3_CH3_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN8)
#define GPIO_TIM3_CH3_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN5)
#define GPIO_TIM3_CH3_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN0)
#define GPIO_TIM3_CH4_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN9)
#define GPIO_TIM3_CH4_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN6)
#define GPIO_TIM3_CH4_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN1)
#define GPIO_TIM3_ETR_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN2)
#define GPIO_TIM3_ETR_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN2)
#define GPIO_TIM14_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN1)
#define GPIO_TIM14_CH1_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_TIM14_CH1_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_TIM15_BKIN_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN9)
#define GPIO_TIM15_BKIN_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_TIM15_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_TIM15_CH1_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTF | GPIO_PIN9)
#define GPIO_TIM15_CH1_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_TIM15_CH1N_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_TIM15_CH1N_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_TIM15_CH2_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN3)
#define GPIO_TIM15_CH2_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTF | GPIO_PIN10)
#define GPIO_TIM15_CH2_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_TIM16_BKIN (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_TIM16_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN0)
#define GPIO_TIM16_CH1_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN8)
#define GPIO_TIM16_CH1_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_TIM16_CH1N (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN6)
#define GPIO_TIM17_BKIN_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN10)
#define GPIO_TIM17_BKIN_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_TIM17_CH1_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN1)
#define GPIO_TIM17_CH1_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN9)
#define GPIO_TIM17_CH1_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_TIM17_CH1N (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN7)
/* TSC */
#define GPIO_TSC_G1_IO1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN0)
#define GPIO_TSC_G1_IO2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_TSC_G1_IO3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_TSC_G1_IO4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN3)
#define GPIO_TSC_G2_IO1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_TSC_G2_IO2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN5)
#define GPIO_TSC_G2_IO3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_TSC_G2_IO4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_TSC_G3_IO1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN5)
#define GPIO_TSC_G3_IO2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN0)
#define GPIO_TSC_G3_IO3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN1)
#define GPIO_TSC_G3_IO4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN2)
#define GPIO_TSC_G4_IO1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN9)
#define GPIO_TSC_G4_IO2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN10)
#define GPIO_TSC_G4_IO3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_TSC_G4_IO4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_TSC_G5_IO1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_TSC_G5_IO2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_TSC_G5_IO3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN6)
#define GPIO_TSC_G5_IO4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN7)
#define GPIO_TSC_G6_IO1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN11)
#define GPIO_TSC_G6_IO2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_TSC_G6_IO3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_TSC_G6_IO4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_TSC_G7_IO1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN2)
#define GPIO_TSC_G7_IO2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN3)
#define GPIO_TSC_G7_IO3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN4)
#define GPIO_TSC_G7_IO4 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN5)
#define GPIO_TSC_G8_IO1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN12)
#define GPIO_TSC_G8_IO2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN13)
#define GPIO_TSC_G8_IO3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN14)
#define GPIO_TSC_G8_IO4 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN15)
#define GPIO_TSC_SYNC_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_TSC_SYNC_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN8)
/* USARTs */
#define GPIO_USART1_CK (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN8)
#define GPIO_USART1_CTS (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_USART1_RTS (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN12)
#define GPIO_USART1_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN7)
#define GPIO_USART1_RX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN10)
#define GPIO_USART1_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN6)
#define GPIO_USART1_TX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN9)
#define GPIO_USART2_CK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN7)
#define GPIO_USART2_CK_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_USART2_CTS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN3)
#define GPIO_USART2_CTS_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN0)
#define GPIO_USART2_RTS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN4)
#define GPIO_USART2_RTS_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_USART2_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN6)
#define GPIO_USART2_RX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_USART2_RX_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN3)
#define GPIO_USART2_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN5)
#define GPIO_USART2_TX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN14)
#define GPIO_USART2_TX_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN2)
#define GPIO_USART3_CK_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN10)
#define GPIO_USART3_CK_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN12)
#define GPIO_USART3_CK_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN0)
#define GPIO_USART3_CK_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_USART3_CTS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN11)
#define GPIO_USART3_CTS_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_USART3_CTS_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_USART3_RTS_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN12)
#define GPIO_USART3_RTS_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTD | GPIO_PIN2)
#define GPIO_USART3_RTS_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN1)
#define GPIO_USART3_RTS_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_USART3_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN9)
#define GPIO_USART3_RX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN11)
#define GPIO_USART3_RX_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN5)
#define GPIO_USART3_RX_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN11)
#define GPIO_USART3_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN8)
#define GPIO_USART3_TX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN10)
#define GPIO_USART3_TX_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN4)
#define GPIO_USART3_TX_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN10)
#define GPIO_USART4_CK (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN12)
#define GPIO_USART4_CTS (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN7)
#define GPIO_USART4_RTS (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN15)
#define GPIO_USART4_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN11)
#define GPIO_USART4_RX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN1)
#define GPIO_USART4_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN10)
#define GPIO_USART4_TX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN0)
#define GPIO_USART5_CK_RST_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN5)
#define GPIO_USART5_CK_RST_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN7)
#define GPIO_USART5_RX_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN4)
#define GPIO_USART5_RX_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN2)
#define GPIO_USART5_RX_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN11)
#define GPIO_USART5_TX_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_USART5_TX_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN12)
#define GPIO_USART5_TX_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN10)
#define GPIO_USART6_TX_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN4)
#define GPIO_USART6_RX_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN5)
#define GPIO_USART6_TX_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN0)
#define GPIO_USART6_RX_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN1)
#define GPIO_USART6_TX_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTF | GPIO_PIN9)
#define GPIO_USART6_RX_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTF | GPIO_PIN10)
#define GPIO_USART6_CK_RST (GPIO_ALT | GPIO_AF2 | GPIO_PORTF | GPIO_PIN3)
#define GPIO_USART7_TX_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN0)
#define GPIO_USART7_RX_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN1)
#define GPIO_USART7_TX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN6)
#define GPIO_USART7_RX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN7)
#define GPIO_USART7_TX_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTF | GPIO_PIN2)
#define GPIO_USART7_RX_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTF | GPIO_PIN3)
#define GPIO_USART7_CK_RST_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN15)
#define GPIO_USART7_CK_RST_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTF | GPIO_PIN2)
#define GPIO_USART8_TX_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN2)
#define GPIO_USART8_RX_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN3)
#define GPIO_USART8_TX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN8)
#define GPIO_USART8_RX_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN9)
#define GPIO_USART8_TX_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN8)
#define GPIO_USART8_RX_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN13)
#define GPIO_USART8_CK_RST (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN14)
#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_STM32F09X_PINMAP_H */
arch/arm/src/stm32f0/chip/stm32f0_memorymap.h
+3 -2
View File
@@ -44,8 +44,9 @@
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32F0_STM32F05X) || defined(CONFIG_STM32F0_STM32F07X)
# include "chip/stm32f05xf07x_memorymap.h"
#if defined(CONFIG_STM32F0_STM32F05X) || defined(CONFIG_STM32F0_STM32F07X) \
|| defined(CONFIG_STM32F0_STM32F09X)
# include "chip/stm32f05xf07xf09x_memorymap.h"
#else
# error "Unsupported STM32 memory map"
#endif
arch/arm/src/stm32f0/chip/stm32f0_pinmap.h
+2
View File
@@ -47,6 +47,8 @@
# include "chip/stm32f05x_pinmap.h"
#elif defined(CONFIG_STM32F0_STM32F07X)
# include "chip/stm32f07x_pinmap.h"
#elif defined(CONFIG_STM32F0_STM32F09X)
# include "chip/stm32f09x_pinmap.h"
#else
# error "Unsupported STM32F0 pin map"
#endif
arch/arm/src/stm32f7/Kconfig
+1
View File
@@ -1821,6 +1821,7 @@ config STM32F7_HAVE_RTC_COUNTER
config STM32F7_HAVE_RTC_SUBSECONDS
bool
select ARCH_HAVE_RTC_SUBSECONDS
default y
config RTC_MAGIC_REG
arch/arm/src/stm32f7/stm32_ethernet.c
+9 -9
View File
@@ -3780,22 +3780,22 @@ static void stm32_macaddress(struct stm32_ethmac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address high register */
regval = ((uint32_t)dev->d_mac.ether_addr_octet[5] << 8) |
(uint32_t)dev->d_mac.ether_addr_octet[4];
regval = ((uint32_t)dev->d_mac.ether.ether_addr_octet[5] << 8) |
(uint32_t)dev->d_mac.ether.ether_addr_octet[4];
stm32_putreg(regval, STM32_ETH_MACA0HR);
/* Set the MAC address low register */
regval = ((uint32_t)dev->d_mac.ether_addr_octet[3] << 24) |
((uint32_t)dev->d_mac.ether_addr_octet[2] << 16) |
((uint32_t)dev->d_mac.ether_addr_octet[1] << 8) |
(uint32_t)dev->d_mac.ether_addr_octet[0];
regval = ((uint32_t)dev->d_mac.ether.ether_addr_octet[3] << 24) |
((uint32_t)dev->d_mac.ether.ether_addr_octet[2] << 16) |
((uint32_t)dev->d_mac.ether.ether_addr_octet[1] << 8) |
(uint32_t)dev->d_mac.ether.ether_addr_octet[0];
stm32_putreg(regval, STM32_ETH_MACA0LR);
}
arch/arm/src/stm32f7/stm32_rtc.c
+35 -1
View File
@@ -1178,7 +1178,7 @@ int up_rtc_getdatetime(FAR struct tm *tp)
}
rtc_dumptime((FAR const struct tm *)tp, &usecs, "Returning");
#else /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */
#else /* CONFIG_STM32F7_HAVE_RTC_SUBSECONDS */
rtc_dumptime((FAR const struct tm *)tp, NULL, "Returning");
#endif
@@ -1215,6 +1215,40 @@ int up_rtc_getdatetime(FAR struct tm *tp)
}
#endif
/************************************************************************************
* Name: up_rtc_getdatetime_with_subseconds
*
* Description:
* Get the current date and time from the date/time RTC. This interface
* is only supported by the date/time RTC hardware implementation.
* It is used to replace the system timer. It is only used by the RTOS during
* initialization to set up the system time when CONFIG_RTC and CONFIG_RTC_DATETIME
* are selected (and CONFIG_RTC_HIRES is not).
*
* NOTE: This interface exposes sub-second accuracy capability of RTC hardware.
* This interface allow maintaining timing accuracy when system time needs constant
* resynchronization with RTC, for example with board level power-save mode utilizing
* deep-sleep modes such as STOP on STM32 MCUs.
*
* Input Parameters:
* tp - The location to return the high resolution time value.
* nsec - The location to return the subsecond time value.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
************************************************************************************/
#ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS
# ifndef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS
# error "Invalid config, enable CONFIG_STM32F7_HAVE_RTC_SUBSECONDS."
# endif
int up_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec)
{
return stm32_rtc_getdatetime_with_subseconds(tp, nsec);
}
#endif
/****************************************************************************
* Name: stm32_rtc_setdatetime
*
arch/arm/src/tiva/lm3s_ethernet.c
+8 -8
View File
@@ -1389,14 +1389,14 @@ static int tiva_ifup(struct net_driver_s *dev)
/* Program the hardware with it's MAC address (for filtering) */
regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[3] << 24 |
(uint32_t)priv->ld_dev.d_mac.ether_addr_octet[2] << 16 |
(uint32_t)priv->ld_dev.d_mac.ether_addr_octet[1] << 8 |
(uint32_t)priv->ld_dev.d_mac.ether_addr_octet[0];
regval = (uint32_t)priv->ld_dev.d_mac.ether.ether_addr_octet[3] << 24 |
(uint32_t)priv->ld_dev.d_mac.ether.ether_addr_octet[2] << 16 |
(uint32_t)priv->ld_dev.d_mac.ether.ether_addr_octet[1] << 8 |
(uint32_t)priv->ld_dev.d_mac.ether.ether_addr_octet[0];
tiva_ethout(priv, TIVA_MAC_IA0_OFFSET, regval);
regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[5] << 8 |
(uint32_t)priv->ld_dev.d_mac.ether_addr_octet[4];
regval = (uint32_t)priv->ld_dev.d_mac.ether.ether_addr_octet[5] << 8 |
(uint32_t)priv->ld_dev.d_mac.ether.ether_addr_octet[4];
tiva_ethout(priv, TIVA_MAC_IA1_OFFSET, regval);
/* Set and activate a timer process */
@@ -1696,13 +1696,13 @@ static inline int tiva_ethinitialize(int intf)
priv->ld_txpoll = wd_create(); /* Create periodic poll timer */
priv->ld_txtimeout = wd_create(); /* Create TX timeout timer */
#ifdef CONFIG_TIVA_BOARDMAC
/* If the board can provide us with a MAC address, get the address
* from the board now. The MAC will not be applied until tiva_ifup()
* is called (and the MAC can be overwritten with a netdev ioctl call).
*/
#ifdef CONFIG_TIVA_BOARDMAC
tiva_ethernetmac(&priv->ld_dev.d_mac);
tiva_ethernetmac(&priv->ld_dev.d_mac.ether);
#endif
/* Perform minimal, one-time initialization -- just reset the controller and
arch/arm/src/tiva/tm4c_ethernet.c
+10 -10
View File
@@ -3755,22 +3755,22 @@ static void tiva_macaddress(FAR struct tiva_ethmac_s *priv)
ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_ifname,
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
/* Set the MAC address high register */
regval = ((uint32_t)dev->d_mac.ether_addr_octet[5] << 8) |
(uint32_t)dev->d_mac.ether_addr_octet[4];
regval = ((uint32_t)dev->d_mac.ether.ether_addr_octet[5] << 8) |
(uint32_t)dev->d_mac.ether.ether_addr_octet[4];
tiva_putreg(regval, TIVA_EMAC_ADDR0H);
/* Set the MAC address low register */
regval = ((uint32_t)dev->d_mac.ether_addr_octet[3] << 24) |
((uint32_t)dev->d_mac.ether_addr_octet[2] << 16) |
((uint32_t)dev->d_mac.ether_addr_octet[1] << 8) |
(uint32_t)dev->d_mac.ether_addr_octet[0];
regval = ((uint32_t)dev->d_mac.ether.ether_addr_octet[3] << 24) |
((uint32_t)dev->d_mac.ether.ether_addr_octet[2] << 16) |
((uint32_t)dev->d_mac.ether.ether_addr_octet[1] << 8) |
(uint32_t)dev->d_mac.ether.ether_addr_octet[0];
tiva_putreg(regval, TIVA_EMAC_ADDR0L);
}
@@ -4056,7 +4056,7 @@ int tiva_ethinitialize(int intf)
* is called (and the MAC can be overwritten with a netdev ioctl call).
*/
tiva_ethernetmac(&priv->dev.d_mac);
tiva_ethernetmac(&priv->dev.d_mac.ether);
#endif
/* Enable power and clocking to the Ethernet MAC
arch/avr/src/common/up_udelay.c
+1 -1
View File
@@ -75,7 +75,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***
arch/hc/src/common/up_udelay.c
+1 -1
View File
@@ -75,7 +75,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***
arch/hc/src/m9s12/m9s12_ethernet.c
+1 -1
View File
@@ -781,7 +781,7 @@ int emac_initialize(int intf)
* the device and/or calling emac_ifdown().
*/
/* Read the MAC address from the hardware into priv->d_dev.d_mac.ether_addr_octet */
/* Read the MAC address from the hardware into priv->d_dev.d_mac.ether.ether_addr_octet */
/* Register the device with the OS so that socket IOCTLs can be performed */
arch/mips/src/common/up_udelay.c
+1 -1
View File
@@ -75,7 +75,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***
arch/mips/src/pic32mx/pic32mx-ethernet.c
+12 -12
View File
@@ -2216,29 +2216,29 @@ static int pic32mx_ifup(struct net_driver_s *dev)
*/
#if 0
regval = (uint32_t)priv->pd_dev.d_mac.ether_addr_octet[5] << 8 |
(uint32_t)priv->pd_dev.d_mac.ether_addr_octet[4];
regval = (uint32_t)priv->pd_dev.d_mac.ether.ether_addr_octet[5] << 8 |
(uint32_t)priv->pd_dev.d_mac.ether.ether_addr_octet[4];
pic32mx_putreg(regval, PIC32MX_EMAC1_SA0);
regval = (uint32_t)priv->pd_dev.d_mac.ether_addr_octet[3] << 8 |
(uint32_t)priv->pd_dev.d_mac.ether_addr_octet[2];
regval = (uint32_t)priv->pd_dev.d_mac.ether.ether_addr_octet[3] << 8 |
(uint32_t)priv->pd_dev.d_mac.ether.ether_addr_octet[2];
pic32mx_putreg(regval, PIC32MX_EMAC1_SA1);
regval = (uint32_t)priv->pd_dev.d_mac.ether_addr_octet[1] << 8 |
(uint32_t)priv->pd_dev.d_mac.ether_addr_octet[0];
regval = (uint32_t)priv->pd_dev.d_mac.ether.ether_addr_octet[1] << 8 |
(uint32_t)priv->pd_dev.d_mac.ether.ether_addr_octet[0];
pic32mx_putreg(regval, PIC32MX_EMAC1_SA2);
#else
regval = pic32mx_getreg(PIC32MX_EMAC1_SA0);
priv->pd_dev.d_mac.ether_addr_octet[4] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether_addr_octet[5] = (uint32_t)((regval >> 8) & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[4] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[5] = (uint32_t)((regval >> 8) & 0xff);
regval = pic32mx_getreg(PIC32MX_EMAC1_SA1);
priv->pd_dev.d_mac.ether_addr_octet[2] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether_addr_octet[3] = (uint32_t)((regval >> 8) & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[2] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[3] = (uint32_t)((regval >> 8) & 0xff);
regval = pic32mx_getreg(PIC32MX_EMAC1_SA2);
priv->pd_dev.d_mac.ether_addr_octet[0] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether_addr_octet[1] = (uint32_t)((regval >> 8) & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[0] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[1] = (uint32_t)((regval >> 8) & 0xff);
#endif
/* Continue Ethernet Controller Initialization ****************************/
arch/mips/src/pic32mz/pic32mz-ethernet.c
+15 -15
View File
@@ -2243,34 +2243,34 @@ static int pic32mz_ifup(struct net_driver_s *dev)
*/
#if 0
regval = (uint32_t)priv->pd_dev.d_mac.ether_addr_octet[5] << 8 |
(uint32_t)priv->pd_dev.d_mac.ether_addr_octet[4];
regval = (uint32_t)priv->pd_dev.d_mac.ether.ether_addr_octet[5] << 8 |
(uint32_t)priv->pd_dev.d_mac.ether.ether_addr_octet[4];
pic32mz_putreg(regval, PIC32MZ_EMAC1_SA0);
regval = (uint32_t)priv->pd_dev.d_mac.ether_addr_octet[3] << 8 |
(uint32_t)priv->pd_dev.d_mac.ether_addr_octet[2];
regval = (uint32_t)priv->pd_dev.d_mac.ether.ether_addr_octet[3] << 8 |
(uint32_t)priv->pd_dev.d_mac.ether.ether_addr_octet[2];
pic32mz_putreg(regval, PIC32MZ_EMAC1_SA1);
regval = (uint32_t)priv->pd_dev.d_mac.ether_addr_octet[1] << 8 |
(uint32_t)priv->pd_dev.d_mac.ether_addr_octet[0];
regval = (uint32_t)priv->pd_dev.d_mac.ether.ether_addr_octet[1] << 8 |
(uint32_t)priv->pd_dev.d_mac.ether.ether_addr_octet[0];
pic32mz_putreg(regval, PIC32MZ_EMAC1_SA2);
#else
regval = pic32mz_getreg(PIC32MZ_EMAC1_SA0);
priv->pd_dev.d_mac.ether_addr_octet[4] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether_addr_octet[5] = (uint32_t)((regval >> 8) & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[4] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[5] = (uint32_t)((regval >> 8) & 0xff);
regval = pic32mz_getreg(PIC32MZ_EMAC1_SA1);
priv->pd_dev.d_mac.ether_addr_octet[2] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether_addr_octet[3] = (uint32_t)((regval >> 8) & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[2] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[3] = (uint32_t)((regval >> 8) & 0xff);
regval = pic32mz_getreg(PIC32MZ_EMAC1_SA2);
priv->pd_dev.d_mac.ether_addr_octet[0] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether_addr_octet[1] = (uint32_t)((regval >> 8) & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[0] = (uint32_t)(regval & 0xff);
priv->pd_dev.d_mac.ether.ether_addr_octet[1] = (uint32_t)((regval >> 8) & 0xff);
ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
#endif
/* Continue Ethernet Controller Initialization ****************************/
arch/misoc/src/common/misoc_net.c
+2 -2
View File
@@ -833,7 +833,7 @@ static int misoc_net_ifup(FAR struct net_driver_s *dev)
/* Initialize PHYs, the Ethernet interface, and setup up Ethernet interrupts */
/* Instantiate the MAC address from priv->misoc_net_dev.d_mac.ether_addr_octet */
/* Instantiate the MAC address from priv->misoc_net_dev.d_mac.ether.ether_addr_octet */
#ifdef CONFIG_NET_ICMPv6
/* Set up IPv6 multicast address filtering */
@@ -1182,7 +1182,7 @@ int misoc_net_initialize(int intf)
*/
/* Read the MAC address from the hardware into
* priv->misoc_net_dev.d_mac.ether_addr_octet
* priv->misoc_net_dev.d_mac.ether.ether_addr_octet
*/
/* Register the device with the OS so that socket IOCTLs can be performed */
arch/misoc/src/common/misoc_udelay.c
+1 -1
View File
@@ -59,7 +59,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***
arch/renesas/src/common/up_udelay.c
+1 -1
View File
@@ -75,7 +75,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***
arch/sim/src/up_netdriver.c
+2 -2
View File
@@ -198,7 +198,7 @@ void netdriver_loop(void)
* up_comparemac will always return 0.
*/
is_ours = (up_comparemac(eth->dest, &g_sim_dev.d_mac) == 0);
is_ours = (up_comparemac(eth->dest, &g_sim_dev.d_mac.ether) == 0);
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet
@@ -359,7 +359,7 @@ int netdriver_init(void)
int netdriver_setmacaddr(unsigned char *macaddr)
{
(void)memcpy(g_sim_dev.d_mac.ether_addr_octet, macaddr, IFHWADDRLEN);
(void)memcpy(g_sim_dev.d_mac.ether.ether_addr_octet, macaddr, IFHWADDRLEN);
return 0;
}
arch/x86/src/common/up_udelay.c
+1 -1
View File
@@ -75,7 +75,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***
arch/xtensa/src/common/xtensa_udelay.c
+1 -1
View File
@@ -59,7 +59,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***
arch/z16/src/common/up_udelay.c
+1 -1
View File
@@ -77,7 +77,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***
arch/z80/src/common/up_udelay.c
+1 -1
View File
@@ -77,7 +77,7 @@
* Description:
* Delay inline for the requested number of microseconds. NOTE: Because
* of all of the setup, several microseconds will be lost before the actual
* timing looop begins. Thus, the delay will always be a few microseconds
* timing loop begins. Thus, the delay will always be a few microseconds
* longer than requested.
*
* *** NOT multi-tasking friendly ***
arch/z80/src/ez80/ez80_emac.c
+10 -10
View File
@@ -1999,9 +1999,9 @@ static int ez80emac_ifup(FAR struct net_driver_s *dev)
int ret;
ninfo("Bringing up: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1],
dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3],
dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]);
dev->d_mac.ether.ether_addr_octet[0], dev->d_mac.ether.ether_addr_octet[1],
dev->d_mac.ether.ether_addr_octet[2], dev->d_mac.ether.ether_addr_octet[3],
dev->d_mac.ether.ether_addr_octet[4], dev->d_mac.ether.ether_addr_octet[5]);
ninfo(" IP %d.%d.%d.%d\n",
dev->d_ipaddr >> 24, (dev->d_ipaddr >> 16) & 0xff,
(dev->d_ipaddr >> 8) & 0xff, dev->d_ipaddr & 0xff);
@@ -2028,12 +2028,12 @@ static int ez80emac_ifup(FAR struct net_driver_s *dev)
/* Set the MAC address */
outp(EZ80_EMAC_STAD_0, priv->dev.d_mac.ether_addr_octet[0]);
outp(EZ80_EMAC_STAD_1, priv->dev.d_mac.ether_addr_octet[1]);
outp(EZ80_EMAC_STAD_2, priv->dev.d_mac.ether_addr_octet[2]);
outp(EZ80_EMAC_STAD_3, priv->dev.d_mac.ether_addr_octet[3]);
outp(EZ80_EMAC_STAD_4, priv->dev.d_mac.ether_addr_octet[4]);
outp(EZ80_EMAC_STAD_5, priv->dev.d_mac.ether_addr_octet[5]);
outp(EZ80_EMAC_STAD_0, priv->dev.d_mac.ether.ether_addr_octet[0]);
outp(EZ80_EMAC_STAD_1, priv->dev.d_mac.ether.ether_addr_octet[1]);
outp(EZ80_EMAC_STAD_2, priv->dev.d_mac.ether.ether_addr_octet[2]);
outp(EZ80_EMAC_STAD_3, priv->dev.d_mac.ether.ether_addr_octet[3]);
outp(EZ80_EMAC_STAD_4, priv->dev.d_mac.ether.ether_addr_octet[4]);
outp(EZ80_EMAC_STAD_5, priv->dev.d_mac.ether.ether_addr_octet[5]);
/* Enable/disable promiscuous mode */
@@ -2542,7 +2542,7 @@ int up_netinitialize(void)
priv->txpoll = wd_create(); /* Create periodic poll timer */
priv->txtimeout = wd_create(); /* Create TX timeout timer */
/* Read the MAC address from the hardware into priv->dev.d_mac.ether_addr_octet */
/* Read the MAC address from the hardware into priv->dev.d_mac.ether.ether_addr_octet */
/* Register the device with the OS so that socket IOCTLs can be performed */
configs/nucleo-f072rb/README.txt
+7 -7
View File
@@ -1,9 +1,9 @@
Nucleo-F072RB README
====================
This README file discusess the port of NuttX to the STMicro Nucleo-F4072RB
board. That board features the STM32F072RBT6 MCU with 128KiB with 128KiB
of FLASH and 16KiB of SRAM.
This README file discusses the port of NuttX to the STMicro Nucleo-F072RB
board. That board features the STM32F072RBT6 MCU with 128KiB of FLASH
and 16KiB of SRAM.
Contents
========
@@ -53,8 +53,8 @@ LEDs
These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
defined. In that case, the usage by the board port is defined in
include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
events as follows when the red LED (PE24) is available:
include/board.h and src/stm32_autoleds.c. The LEDs are used to encode
OS-related events as follows when the red LED (PE24) is available:
SYMBOL Meaning LD2
------------------- ----------------------- -----------
@@ -192,11 +192,11 @@ Configurations
Information Common to All Configurations
----------------------------------------
Each Clicker2 configuration is maintained in a sub-directory and can be
Each configuration is maintained in a sub-directory and can be
selected as follow:
cd tools
./configure.sh nucleo-f702rb/<subdir>
./configure.sh nucleo-f072rb/<subdir>
cd -
. ./setenv.sh
crypto/random_pool.c
+7 -7
View File
@@ -136,7 +136,7 @@ static const uint32_t pool_twist[8] =
****************************************************************************/
/****************************************************************************
* Function: addentropy
* Name: addentropy
*
* Description:
*
@@ -201,7 +201,7 @@ static void addentropy(FAR const uint32_t *buf, size_t n, bool inc_new)
}
/****************************************************************************
* Function: getentropy
* Name: getentropy
*
* Description:
* Hash entropy pool to BLAKE2s context. This is an internal interface for
@@ -385,7 +385,7 @@ static void rng_init(void)
****************************************************************************/
/****************************************************************************
* Function: up_rngaddint
* Name: up_rngaddint
*
* Description:
* Add one integer to entropy pool, contributing a specific kind
@@ -410,7 +410,7 @@ void up_rngaddint(enum rnd_source_t kindof, int val)
}
/****************************************************************************
* Function: up_rngaddentropy
* Name: up_rngaddentropy
*
* Description:
* Add buffer of integers to entropy pool.
@@ -490,7 +490,7 @@ void up_rngaddentropy(enum rnd_source_t kindof, FAR const uint32_t *buf,
}
/****************************************************************************
* Function: up_rngreseed
* Name: up_rngreseed
*
* Description:
* Force reseeding random number generator from entropy pool
@@ -513,7 +513,7 @@ void up_rngreseed(void)
}
/****************************************************************************
* Function: up_randompool_initialize
* Name: up_randompool_initialize
*
* Description:
* Initialize entropy pool and random number generator
@@ -530,7 +530,7 @@ void up_randompool_initialize(void)
}
/****************************************************************************
* Function: getrandom
* Name: getrandom
*
* Description:
* Fill a buffer of arbitrary length with randomness. This is the
drivers/input/ads7843e.c
+2 -2
View File
@@ -159,7 +159,7 @@ static struct ads7843e_dev_s *g_ads7843elist;
****************************************************************************/
/****************************************************************************
* Function: ads7843e_lock
* Name: ads7843e_lock
*
* Description:
* Lock the SPI bus and re-configure as necessary. This function must be
@@ -198,7 +198,7 @@ static void ads7843e_lock(FAR struct spi_dev_s *spi)
}
/****************************************************************************
* Function: ads7843e_unlock
* Name: ads7843e_unlock
*
* Description:
* Un-lock the SPI bus after each transfer, possibly losing the current
drivers/input/max11802.c
+2 -2
View File
@@ -159,7 +159,7 @@ static struct max11802_dev_s *g_max11802list;
****************************************************************************/
/****************************************************************************
* Function: max11802_lock
* Name: max11802_lock
*
* Description:
* Lock the SPI bus and re-configure as necessary. This function must be
@@ -196,7 +196,7 @@ static void max11802_lock(FAR struct spi_dev_s *spi)
}
/****************************************************************************
* Function: max11802_unlock
* Name: max11802_unlock
*
* Description:
* Un-lock the SPI bus after each transfer, possibly losing the current
drivers/iob/iob_dump.c
+1 -1
View File
@@ -61,7 +61,7 @@
****************************************************************************/
/****************************************************************************
* Function: iob_dump
* Name: iob_dump
*
* Description:
* Dump the contents of a I/O buffer chain
drivers/lcd/nokia6100.c
+2 -2
View File
@@ -637,7 +637,7 @@ static const uint8_t g_setcon[] =
**************************************************************************************/
/**************************************************************************************
* Function: nokia_select
* Name: nokia_select
*
* Description:
* Select the SPI, locking and re-configuring if necessary
@@ -674,7 +674,7 @@ static void nokia_select(FAR struct spi_dev_s *spi)
}
/**************************************************************************************
* Function: nokia_deselect
* Name: nokia_deselect
*
* Description:
* De-select the SPI
drivers/lcd/st7567.c
+2 -2
View File
@@ -343,7 +343,7 @@ static struct st7567_dev_s g_st7567dev =
**************************************************************************************/
/**************************************************************************************
* Function: st7567_select
* Name: st7567_select
*
* Description:
* Select the SPI, locking and re-configuring if necessary
@@ -380,7 +380,7 @@ static void st7567_select(FAR struct spi_dev_s *spi)
}
/**************************************************************************************
* Function: st7567_deselect
* Name: st7567_deselect
*
* Description:
* De-select the SPI

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