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s32k1xx:LPI2C Add DMA support

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This commit is contained in:
David Sidrane
2022-08-01 10:11:15 -07:00
committed by Xiang Xiao
parent fa2e1897ea
commit 32c4bdb7a6
3 changed files with 598 additions and 34 deletions
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arch/arm/src/s32k1xx/Kconfig
+63
View File
@@ -641,6 +641,58 @@ config S32K1XX_LPSPI_HWPCS
endmenu # LPSPI Configuration
menu "LPI2C Configuration"
depends on S32K1XX_LPI2C
config S32K1XX_LPI2C_DMA
bool "I2C DMA Support"
default n
depends on S32K1XX_LPI2C && S32K1XX_EDMA && !I2C_POLLED
---help---
This option enables the DMA for I2C transfers.
Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value
for the I2C dma streams, else the default priority level is set to
medium.
config S32K1XX_LPI2C_DMA_MAXMSG
int "Maximum number messages that will be DMAed"
default 8
depends on S32K1XX_LPI2C_DMA
---help---
This option set the mumber of mesg that can be in a transfer.
It is used to allocate space for the 16 bit LPI2C commands
that will be DMA-ed to the LPI2C device.
config S32K1XX_LPI2C_DYNTIMEO
bool "Use dynamic timeouts"
default n
depends on S32K1XX_LPI2C
config S32K1XX_LPI2C_DYNTIMEO_USECPERBYTE
int "Timeout Microseconds per Byte"
default 500
depends on S32K1XX_LPI2C_DYNTIMEO
config S32K1XX_LPI2C_DYNTIMEO_STARTSTOP
int "Timeout for Start/Stop (Milliseconds)"
default 1000
depends on S32K1XX_LPI2C_DYNTIMEO
config S32K1XX_LPI2C_TIMEOSEC
int "Timeout seconds"
default 0
depends on S32K1XX_LPI2C
config S32K1XX_LPI2C_TIMEOMS
int "Timeout Milliseconds"
default 500
depends on S32K1XX_LPI2C && !S32K1XX_LPI2C_DYNTIMEO
config S32K1XX_LPI2C_TIMEOTICKS
int "Timeout for Done and Stop (ticks)"
default 500
depends on S32K1XX_LPI2C && !S32K1XX_LPI2C_DYNTIMEO
menu "LPI2C0 Master Configuration"
depends on S32K1XX_LPI2C0
@@ -648,6 +700,11 @@ config LPI2C0_BUSYIDLE
int "Bus idle timeout period in clock cycles"
default 0
config LPI2C0_DMA
bool "Enable DMA for I2C0"
default n
depends on S32K1XX_LPI2C_DMA
config LPI2C0_FILTSCL
int "I2C master digital glitch filters for SCL input in clock cycles"
default 0
@@ -678,6 +735,11 @@ endmenu # LPI2C0 Slave Configuration
menu "LPI2C1 Master Configuration"
depends on S32K1XX_LPI2C1
config LPI2C1_DMA
bool "Enable DMA for I2C1"
default n
depends on S32K1XX_LPI2C_DMA
config LPI2C1_BUSYIDLE
int "Bus idle timeout period in clock cycles"
default 0
@@ -708,6 +770,7 @@ config LPI2C1_SLAVE_BUS
the LPI2C master. These pins need to be defined in the board.h.
endmenu # LPI2C1 Slave Configuration
endmenu # LPI2C Configuration
menu "Ethernet Configuration"
depends on S32K1XX_ENET
arch/arm/src/s32k1xx/hardware/s32k1xx_lpi2c.h
+30 -30
View File
@@ -239,7 +239,7 @@
/* LPI2C Master Config Register 1 */
#define LPI2C_MCFGR1_PRESCALE_MASK (7 << 0) /* Clock Prescaler Bit Mask */
# define LPI2C_MCFGR1_PRESCALE(n) (n & LPI2C_MCFGR1_PRESCALE_MASK)
# define LPI2C_MCFGR1_PRESCALE(n) ((n) & LPI2C_MCFGR1_PRESCALE_MASK)
# define LPI2C_MCFGR1_PRESCALE_1 (0)
# define LPI2C_MCFGR1_PRESCALE_2 (1)
# define LPI2C_MCFGR1_PRESCALE_4 (2)
@@ -254,7 +254,7 @@
/* Bits 15-11 Reserved */
#define LPI2C_MCFGR1_MATCFG_SHIFT (16)
#define LPI2C_MCFGR1_MATCFG_MASK (7 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match Configuration Bit Mask */
# define LPI2C_MCFGR1_MATCFG(n) ((n << LPI2C_MCFGR1_MATCFG_SHIFT) & LPI2C_MCFGR1_MATCFG_MASK)
# define LPI2C_MCFGR1_MATCFG(n) (((n) << LPI2C_MCFGR1_MATCFG_SHIFT) & LPI2C_MCFGR1_MATCFG_MASK)
# define LPI2C_MCFGR1_MATCFG_DISABLE (0 << LPI2C_MCFGR1_MATCFG_SHIFT)
/* LPI2C_MCFG1_MATCFG = 001b Reserved */
# define LPI2C_MCFGR1_MATCFG2 (2 << LPI2C_MCFGR1_MATCFG_SHIFT)
@@ -266,7 +266,7 @@
/* Bits 23-19 Reserved */
#define LPI2C_MCFGR1_PINCFG_SHIFT (24)
#define LPI2C_MCFGR1_PINCFG_MASK (7 << LPI2C_MCFGR1_PINCFG_SHIFT) /* Pin Configuration Bit Mask */
# define LPI2C_MCFGR1_PINCFG(n) ((n << LPI2C_MCFGR1_PINCFG_SHIFT) & LPI2C_MCFGR1_PINCFG_MASK)
# define LPI2C_MCFGR1_PINCFG(n) (((n) << LPI2C_MCFGR1_PINCFG_SHIFT) & LPI2C_MCFGR1_PINCFG_MASK)
# define LPI2C_MCFGR1_PINCFG0 (0 << LPI2C_MCFGR1_PINCFG_SHIFT)
# define LPI2C_MCFGR1_PINCFG1 (1 << LPI2C_MCFGR1_PINCFG_SHIFT)
# define LPI2C_MCFGR1_PINCFG2 (2 << LPI2C_MCFGR1_PINCFG_SHIFT)
@@ -281,17 +281,17 @@
#define LPI2C_MCFG2_BUSIDLE_MASK (0xfff << 0) /* Bus Idle Timeout Period in Clock Cycles */
#define LPI2C_MCFG2_BUSIDLE_DISABLE (0)
# define LPI2C_MCFG2_BUSIDLE(n) (n & LPI2C_MCFG2_BUSIDLE_MASK)
# define LPI2C_MCFG2_BUSIDLE(n) ((n) & LPI2C_MCFG2_BUSIDLE_MASK)
/* Bits 15-12 Reserved */
#define LPI2C_MCFG2_FILTSCL_SHIFT (16)
#define LPI2C_MCFG2_FILTSCL_MASK (15 << LPI2C_MCFG2_FILTSCL_SHIFT) /* Glitch Filter SCL */
#define LPI2C_MCFG2_FILTSCL_DISABLE (0 << LPI2C_MCFG2_FILTSCL_SHIFT)
# define LPI2C_MCFG2_FILTSCL_CYCLES(n) ((n << LPI2C_MCFG2_FILTSCL_SHIFT) & LPI2C_MCFG2_FILTSCL_MASK)
# define LPI2C_MCFG2_FILTSCL_CYCLES(n) (((n) << LPI2C_MCFG2_FILTSCL_SHIFT) & LPI2C_MCFG2_FILTSCL_MASK)
/* Bits 23-20 Reserved */
#define LPI2C_MCFG2_FILTSDA_SHIFT (24)
#define LPI2C_MCFG2_FILTSDA_MASK (15 << LPI2C_MCFG2_FILTSDA_SHIFT) /* Glitch Filter SDA */
#define LPI2C_MCFG2_FILTSDA_DISABLE (0 << LPI2C_MCFG2_FILTSDA_SHIFT)
# define LPI2C_MCFG2_FILTSDA_CYCLES(n) ((n << LPI2C_MCFG2_FILTSDA_SHIFT) & LPI2C_MCFG2_FILTSDA_MASK)
# define LPI2C_MCFG2_FILTSDA_CYCLES(n) (((n) << LPI2C_MCFG2_FILTSDA_SHIFT) & LPI2C_MCFG2_FILTSDA_MASK)
/* Bits 31-28 Reserved */
/* LPI2C Master Config Register 3 */
@@ -299,56 +299,56 @@
/* Bits 7-0 Reserved */
#define LPI2C_MCFG3_PINLOW_SHIFT (8)
#define LPI2C_MCFG3_PINLOW_MASK (0xfff << LPI2C_MCFG3_PINLOW_SHIFT) /* Configure The Pin Low Timeout in Clock Cycles */
# define LPI2C_MCFG3_PINLOW_CYCLES(n) ((n << LPI2C_MCFG3_PINLOW_SHIFT) & LPI2C_MCFG3_PINLOW_MASK)
# define LPI2C_MCFG3_PINLOW_CYCLES(n) (((n) << LPI2C_MCFG3_PINLOW_SHIFT) & LPI2C_MCFG3_PINLOW_MASK)
/* Bits 31-20 Reserved */
/* LPI2C Master Data Match Register */
#define LPI2C_MDMR_MATCH0_SHIFT (0)
#define LPI2C_MDMR_MATCH0_MASK (0xff << LPI2C_MDMR_MATCH0_SHIFT) /* Match 0 Value */
# define LPI2C_MDMR_MATCH0(n) ((n << LPI2C_MDMR_MATCH0_SHIFT) & LPI2C_MDMR_MATCH0_MASK)
# define LPI2C_MDMR_MATCH0(n) (((n) << LPI2C_MDMR_MATCH0_SHIFT) & LPI2C_MDMR_MATCH0_MASK)
/* Bits 15-8 Reserved */
#define LPI2C_MDMR_MATCH1_SHIFT (16)
#define LPI2C_MDMR_MATCH1_MASK (0xff << LPI2C_MDMR_MATCH1_SHIFT) /* Match 1 Value */
# define LPI2C_MDMR_MATCH1(n) ((n << LPI2C_MDMR_MATCH1_SHIFT) & LPI2C_MDMR_MATCH1_MASK)
# define LPI2C_MDMR_MATCH1(n) (((n) << LPI2C_MDMR_MATCH1_SHIFT) & LPI2C_MDMR_MATCH1_MASK)
/* Bits 31-24 Reserved */
/* LPI2C Master Clock Configuration Register 0 */
#define LPI2C_MCCR0_CLKLO_SHIFT (0)
#define LPI2C_MCCR0_CLKLO_MASK (0x3f << LPI2C_MCCR0_CLKLO_SHIFT) /* Clock Low Period */
# define LPI2C_MCCR0_CLKLO(n) ((n << LPI2C_MCCR0_CLKLO_SHIFT) & LPI2C_MCCR0_CLKLO_MASK)
# define LPI2C_MCCR0_CLKLO(n) (((n) << LPI2C_MCCR0_CLKLO_SHIFT) & LPI2C_MCCR0_CLKLO_MASK)
/* Bits 7-6 Reserved */
#define LPI2C_MCCR0_CLKHI_SHIFT (8)
#define LPI2C_MCCR0_CLKHI_MASK (0x3f << LPI2C_MCCR0_CLKHI_SHIFT) /* Clock High Period */
# define LPI2C_MCCR0_CLKHI(n) ((n << LPI2C_MCCR0_CLKHI_SHIFT) & LPI2C_MCCR0_CLKHI_MASK)
# define LPI2C_MCCR0_CLKHI(n) (((n) << LPI2C_MCCR0_CLKHI_SHIFT) & LPI2C_MCCR0_CLKHI_MASK)
/* Bits 15-14 Reserved */
#define LPI2C_MCCR0_SETHOLD_SHIFT (16)
#define LPI2C_MCCR0_SETHOLD_MASK (0x3f << LPI2C_MCCR0_SETHOLD_SHIFT) /* Setup Hold Delay */
# define LPI2C_MCCR0_SETHOLD(n) ((n << LPI2C_MCCR0_SETHOLD_SHIFT) & LPI2C_MCCR0_SETHOLD_MASK)
# define LPI2C_MCCR0_SETHOLD(n) (((n) << LPI2C_MCCR0_SETHOLD_SHIFT) & LPI2C_MCCR0_SETHOLD_MASK)
/* Bits 23-22 Reserved */
#define LPI2C_MCCR0_DATAVD_SHIFT (24)
#define LPI2C_MCCR0_DATAVD_MASK (0x3f << LPI2C_MCCR0_DATAVD_SHIFT) /* Setup Hold Delay */
# define LPI2C_MCCR0_DATAVD(n) ((n << LPI2C_MCCR0_DATAVD_SHIFT) & LPI2C_MCCR0_DATAVD_MASK)
# define LPI2C_MCCR0_DATAVD(n) (((n) << LPI2C_MCCR0_DATAVD_SHIFT) & LPI2C_MCCR0_DATAVD_MASK)
/* Bits 31-30 Reserved */
/* LPI2C Master Clock Configuration Register 1 */
#define LPI2C_MCCR1_CLKLO_SHIFT (0)
#define LPI2C_MCCR1_CLKLO_MASK (0x3f << LPI2C_MCCR1_CLKLO_SHIFT) /* Clock Low Period */
# define LPI2C_MCCR1_CLKLO(n) ((n << LPI2C_MCCR1_CLKLO_SHIFT) & LPI2C_MCCR1_CLKLO_MASK)
# define LPI2C_MCCR1_CLKLO(n) (((n) << LPI2C_MCCR1_CLKLO_SHIFT) & LPI2C_MCCR1_CLKLO_MASK)
/* Bits 7-6 Reserved */
#define LPI2C_MCCR1_CLKHI_SHIFT (8)
#define LPI2C_MCCR1_CLKHI_MASK (0x3f << LPI2C_MCCR1_CLKHI_SHIFT) /* Clock High Period */
# define LPI2C_MCCR1_CLKHI(n) ((n << LPI2C_MCCR1_CLKHI_SHIFT) & LPI2C_MCCR1_CLKHI_MASK)
# define LPI2C_MCCR1_CLKHI(n) (((n) << LPI2C_MCCR1_CLKHI_SHIFT) & LPI2C_MCCR1_CLKHI_MASK)
/* Bits 15-14 Reserved */
#define LPI2C_MCCR1_SETHOLD_SHIFT (16)
#define LPI2C_MCCR1_SETHOLD_MASK (0x3f << LPI2C_MCCR1_SETHOLD_SHIFT) /* Setup Hold Delay */
# define LPI2C_MCCR1_SETHOLD(n) ((n << LPI2C_MCCR1_SETHOLD_SHIFT) & LPI2C_MCCR1_SETHOLD_MASK)
# define LPI2C_MCCR1_SETHOLD(n) (((n) << LPI2C_MCCR1_SETHOLD_SHIFT) & LPI2C_MCCR1_SETHOLD_MASK)
/* Bits 23-22 Reserved */
#define LPI2C_MCCR1_DATAVD_SHIFT (24)
#define LPI2C_MCCR1_DATAVD_MASK (0x3f << LPI2C_MCCR1_DATAVD_SHIFT) /* Setup Hold Delay */
# define LPI2C_MCCR1_DATAVD(n) ((n << LPI2C_MCCR1_DATAVD_SHIFT) & LPI2C_MCCR1_DATAVD_MASK)
# define LPI2C_MCCR1_DATAVD(n) (((n) << LPI2C_MCCR1_DATAVD_SHIFT) & LPI2C_MCCR1_DATAVD_MASK)
/* Bits 31-30 Reserved */
/* LPI2C Master FIFO Control Register */
@@ -356,13 +356,13 @@
#define LPI2C_MFCR_TXWATER_SHIFT (0)
#define LPI2C_MFCR_TXWATER_MASK (3 << LPI2C_MFCR_TXWATER_SHIFT) /* Transmit FIFO Watermark*/
# define LPI2C_MFCR_TXWATER(n) ((n << LPI2C_MFCR_TXWATER_SHIFT) & LPI2C_MFCR_TXWATER_MASK) /* Transmit FIFO Watermark*/
# define LPI2C_MFCR_TXWATER(n) (((n) << LPI2C_MFCR_TXWATER_SHIFT) & LPI2C_MFCR_TXWATER_MASK) /* Transmit FIFO Watermark*/
/* Bits 15-2 Reserved */
#define LPI2C_MFCR_RXWATER_SHIFT (16)
#define LPI2C_MFCR_RXWATER_MASK (3 << LPI2C_MFCR_RXWATER_SHIFT) /* Receive FIFO Watermark */
# define LPI2C_MFCR_RXWATER(n) ((n << LPI2C_MFCR_RXWATER_SHIFT) & LPI2C_MFCR_RXWATER_MASK) /* Transmit FIFO Watermark*/
# define LPI2C_MFCR_RXWATER(n) (((n) << LPI2C_MFCR_RXWATER_SHIFT) & LPI2C_MFCR_RXWATER_MASK) /* Transmit FIFO Watermark*/
/* Bits 31-18 Reserved */
@@ -381,10 +381,10 @@
#define LPI2C_MTDR_DATA_SHIFT (0)
#define LPI2C_MTDR_DATA_MASK (0xff << LPI2C_MTDR_DATA_SHIFT) /* Transmit Data */
# define LPI2C_MTDR_DATA(n) (n & LPI2C_MTDR_DATA_MASK)
# define LPI2C_MTDR_DATA(n) ((n) & LPI2C_MTDR_DATA_MASK)
#define LPI2C_MTDR_CMD_SHIFT (8)
#define LPI2C_MTDR_CMD_MASK (7 << LPI2C_MTDR_CMD_SHIFT) /* Command Data */
# define LPI2C_MTDR_CMD(n) ((n << LPI2C_MTDR_CMD_SHIFT) & LPI2C_MTDR_CMD_MASK)
# define LPI2C_MTDR_CMD(n) (((n) << LPI2C_MTDR_CMD_SHIFT) & LPI2C_MTDR_CMD_MASK)
# define LPI2C_MTDR_CMD_TXD (0 << LPI2C_MTDR_CMD_SHIFT)
# define LPI2C_MTDR_CMD_RXD (1 << LPI2C_MTDR_CMD_SHIFT)
# define LPI2C_MTDR_CMD_STOP (2 << LPI2C_MTDR_CMD_SHIFT)
@@ -478,7 +478,7 @@
/* Bits 15-14 Reserved */
#define LPI2C_SCFG1_ADDRCFG_SHIFT (16)
#define LPI2C_SCFG1_ADDRCFG_MASK (7 << LPI2C_SCFG1_ADDRCFG_SHIFT) /* Address Configuration Bit Mask */
# define LPI2C_SCFG1_ADDRCFG(n) ((n << LPI2C_SCFG1_ADDRCFG_SHIFT) & LPI2C_SCFG1_ADDRCFG_MASK)
# define LPI2C_SCFG1_ADDRCFG(n) (((n) << LPI2C_SCFG1_ADDRCFG_SHIFT) & LPI2C_SCFG1_ADDRCFG_MASK)
# define LPI2C_SCFG1_ADDRCFG0 (0 << LPI2C_SCFG1_ADDRCFG_SHIFT)
# define LPI2C_SCFG1_ADDRCFG1 (2 << LPI2C_SCFG1_ADDRCFG_SHIFT)
# define LPI2C_SCFG1_ADDRCFG2 (2 << LPI2C_SCFG1_ADDRCFG_SHIFT)
@@ -492,21 +492,21 @@
/* LPI2C Slave Configuration Register 2 */
#define LPI2C_SCFG2_CLKHOLD_MASK (15 << 0) /* Clock Hold Time */
# define LPI2C_SCFG2_CLKHOLD(n) (n & LPI2C_SCFG2_CLKHOLD_MASK)
# define LPI2C_SCFG2_CLKHOLD(n) ((n) & LPI2C_SCFG2_CLKHOLD_MASK)
/* Bits 7-4 Reserved */
#define LPI2C_SCFG2_DATAVD_SHIFT (8)
#define LPI2C_SCFG2_DATAVD_MASK (0x3f << LPI2C_SCFG2_DATAVD_SHIFT) /* Data Valid Delay */
# define LPI2C_SCFG2_DATAVD(n) ((n << LPI2C_SCFG2_DATAVD_SHIFT) & LPI2C_SCFG2_DATAVD_MASK)
# define LPI2C_SCFG2_DATAVD(n) (((n) << LPI2C_SCFG2_DATAVD_SHIFT) & LPI2C_SCFG2_DATAVD_MASK)
/* Bits 15-14 Reserved */
#define LPI2C_SCFG2_FILTSCL_SHIFT (16)
#define LPI2C_SCFG2_FILTSCL_MASK (15 << LPI2C_SCFG2_FILTSCL_SHIFT) /* Glitch Filter SCL */
#define LPI2C_SCFG2_FILTSCL_DISABLE (0 << LPI2C_SCFG2_FILTSCL_SHIFT)
# define LPI2C_SCFG2_FILTSCL_CYCLES(n) ((n << LPI2C_SCFG2_FILTSCL_SHIFT) & LPI2C_SCFG2_FILTSCL_MASK)
# define LPI2C_SCFG2_FILTSCL_CYCLES(n) (((n) << LPI2C_SCFG2_FILTSCL_SHIFT) & LPI2C_SCFG2_FILTSCL_MASK)
/* Bits 23-20 Reserved */
#define LPI2C_SCFG2_FILTSDA_SHIFT (24)
#define LPI2C_SCFG2_FILTSDA_MASK (15 << LPI2C_SCFG2_FILTSDA_SHIFT) /* Glitch Filter SDA */
#define LPI2C_SCFG2_FILTSDA_DISABLE (0 << LPI2C_SCFG2_FILTSDA_SHIFT)
# define LPI2C_SCFG2_FILTSDA_CYCLES(n) ((n << LPI2C_SCFG2_FILTSDA_SHIFT) & LPI2C_SCFG2_FILTSDA_MASK)
# define LPI2C_SCFG2_FILTSDA_CYCLES(n) (((n) << LPI2C_SCFG2_FILTSDA_SHIFT) & LPI2C_SCFG2_FILTSDA_MASK)
/* Bits 31-28 Reserved */
/* LPI2C Slave Address Match Register */
@@ -514,11 +514,11 @@
/* Bit 0 Reserved */
#define LPI2C_SAMR_ADDR0_SHIFT (1)
#define LPI2C_SAMR_ADDR0_MASK (0x3ff << LPI2C_SAMR_ADDR0_SHIFT) /* Address 0 Value */
# define LPI2C_SAMR_ADDR0(n) ((n << LPI2C_SAMR_ADDR0_SHIFT) & LPI2C_SAMR_ADDR0_MASK)
# define LPI2C_SAMR_ADDR0(n) (((n) << LPI2C_SAMR_ADDR0_SHIFT) & LPI2C_SAMR_ADDR0_MASK)
/* Bits 16-11 Reserved */
#define LPI2C_SAMR_ADDR1_SHIFT (17)
#define LPI2C_SAMR_ADDR1_MASK (0x3ff << LPI2C_SAMR_ADDR1_SHIFT) /* Address 1 Value */
# define LPI2C_SAMR_ADDR1(n) ((n << LPI2C_SAMR_ADDR1_SHIFT) & LPI2C_SAMR_ADDR1_MASK)
# define LPI2C_SAMR_ADDR1(n) (((n) << LPI2C_SAMR_ADDR1_SHIFT) & LPI2C_SAMR_ADDR1_MASK)
/* Bits 31-27 Reserved */
/* LPI2C Slave Address Status Register */
@@ -538,14 +538,14 @@
#define LPI2C_STDR_DATA_SHIFT (0)
#define LPI2C_STDR_DATA_MASK (0xff << LPI2C_STDR_DATA_SHIFT) /* Transmit Data */
# define LPI2C_STDR_DATA(n) ((n << LPI2C_STDR_DATA_SHIFT) & LPI2C_STDR_DATA_MASK)
# define LPI2C_STDR_DATA(n) (((n) << LPI2C_STDR_DATA_SHIFT) & LPI2C_STDR_DATA_MASK)
/* Bits 31-8 Reserved */
/* LPI2C Slave Receive Data Register */
#define LPI2C_SRDR_DATA_SHIFT (0)
#define LPI2C_SRDR_DATA_MASK (0xff << LPI2C_SRDR_DATA_SHIFT) /* Receive Data */
# define LPI2C_SRDR_DATA(n) ((n << LPI2C_SRDR_DATA_SHIFT) & LPI2C_SRDR_DATA_MASK)
# define LPI2C_SRDR_DATA(n) (((n) << LPI2C_SRDR_DATA_SHIFT) & LPI2C_SRDR_DATA_MASK)
/* Bits 8-31 Reserved */
#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_LPI2C_H */
arch/arm/src/s32k1xx/s32k1xx_lpi2c.c
+505 -4
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