arch/risc-v/src/mpfs/mpfs_coremmc: MPFS_FPGA_FIC0_CLK defined as config value

arch/risc-v/src/mpfs/Kconfig

@@ -397,6 +397,12 @@ config MPFS_COREMMC_WRCOMPLETE_IRQNUM
 		design, select CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE and configure the
 		correct IRQ line here.
 
+config MPFS_FPGA_FIC0_CLK_FREQ
+	int "FIC0 clk freq"
+	default 125000000
+	---help---
+		Frequency of FPGA FIC0 clock.
+
 config MPFS_IHC_CLIENT
 	bool "IHC slave"
 	depends on RPTUN && !MPFS_BOOTLOADER

arch/risc-v/src/mpfs/mpfs_coremmc.c

@@ -125,7 +125,7 @@
 
 /* Clocks and timing */
 
-#define MPFS_FPGA_FIC0_CLK                 (125000000)
+#define MPFS_FPGA_FIC0_CLK                 (CONFIG_MPFS_FPGA_FIC0_CLK_FREQ)
 
 #define COREMMC_CMDTIMEOUT                 (100000)
 #define COREMMC_LONGTIMEOUT                (100000000)