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arch: rename xxxx_pause.c to xxxx_smpcall.c

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Signed-off-by: hujun5 <hujun5@xiaomi.com>
This commit is contained in:
hujun5
2024-09-19 21:41:40 +08:00
committed by Xiang Xiao
parent d8cb7759b6
commit 31a3cea64a
60 changed files with 268 additions and 402 deletions
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arch/arm/include/cxd56xx/irq.h
+1 -1
View File
@@ -158,7 +158,7 @@
#define CXD56_IRQ_SPH13 (CXD56_IRQ_EXTINT+93) /* SPH13 IRQ number */
#define CXD56_IRQ_SPH14 (CXD56_IRQ_EXTINT+94) /* SPH14 IRQ number */
#define CXD56_IRQ_SPH15 (CXD56_IRQ_EXTINT+95) /* SPH15 IRQ number */
#define CXD56_IRQ_SW_INT (CXD56_IRQ_EXTINT+96) /* SW_INT IRQ number */
#define CXD56_IRQ_SMP_CALL (CXD56_IRQ_EXTINT+96) /* SMP_CALL IRQ number */
#define CXD56_IRQ_TIMER0 (CXD56_IRQ_EXTINT+97) /* TIMER0 IRQ number */
#define CXD56_IRQ_TIMER1 (CXD56_IRQ_EXTINT+98) /* TIMER1 IRQ number */
#define CXD56_IRQ_TIMER2 (CXD56_IRQ_EXTINT+99) /* TIMER2 IRQ number */
arch/arm/include/lc823450/irq.h
+2 -2
View File
@@ -59,11 +59,11 @@
#define LC823450_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
#define LC823450_IRQ_CTXM3_00 (LC823450_IRQ_INTERRUPTS+0) /* 16: CortexM3_00 interrupt */
#define LC823450_IRQ_CTXM3_01 (LC823450_IRQ_INTERRUPTS+1) /* 17: CortexM3_01 interrupt */
#define LC823450_IRQ_SMP_CALL_01 (LC823450_IRQ_INTERRUPTS+1) /* 17: CortexM3_01 interrupt */
#define LC823450_IRQ_CTXM3_02 (LC823450_IRQ_INTERRUPTS+2) /* 18: CortexM3_02 interrupt */
#define LC823450_IRQ_CTXM3_03 (LC823450_IRQ_INTERRUPTS+3) /* 19: CortexM3_03 interrupt */
#define LC823450_IRQ_CTXM3_10 (LC823450_IRQ_INTERRUPTS+4) /* 20: CortexM3_00 interrupt */
#define LC823450_IRQ_CTXM3_11 (LC823450_IRQ_INTERRUPTS+5) /* 21: CortexM3_01 interrupt */
#define LC823450_IRQ_SMP_CALL_11 (LC823450_IRQ_INTERRUPTS+5) /* 21: CortexM3_01 interrupt */
#define LC823450_IRQ_CTXM3_12 (LC823450_IRQ_INTERRUPTS+6) /* 22: CortexM3_02 interrupt */
#define LC823450_IRQ_CTXM3_13 (LC823450_IRQ_INTERRUPTS+7) /* 23: CortexM3_03 interrupt */
#define LC823450_IRQ_LPDSP0 (LC823450_IRQ_INTERRUPTS+8) /* 24: LPDSP0 interrupt */
arch/arm/include/rp2040/irq.h
+2 -2
View File
@@ -75,8 +75,8 @@
#define RP2040_DMA_IRQ_1 (RP2040_IRQ_EXTINT+12)
#define RP2040_IO_IRQ_BANK0 (RP2040_IRQ_EXTINT+13)
#define RP2040_IO_IRQ_QSPI (RP2040_IRQ_EXTINT+14)
#define RP2040_SIO_IRQ_PROC0 (RP2040_IRQ_EXTINT+15)
#define RP2040_SIO_IRQ_PROC1 (RP2040_IRQ_EXTINT+16)
#define RP2040_SMP_CALL_PROC0 (RP2040_IRQ_EXTINT+15)
#define RP2040_SMP_CALL_PROC1 (RP2040_IRQ_EXTINT+16)
#define RP2040_CLOCKS_IRQ (RP2040_IRQ_EXTINT+17)
#define RP2040_SPI0_IRQ (RP2040_IRQ_EXTINT+18)
#define RP2040_SPI1_IRQ (RP2040_IRQ_EXTINT+19)
arch/arm/include/sam34/sam4cm_irq.h
+2 -2
View File
@@ -114,7 +114,7 @@
#define SAM_IRQ_TC5 (SAM_IRQ_EXTINT+SAM_PID_TC5) /* PID 28: Timer Counter 5 */
#define SAM_IRQ_ADC (SAM_IRQ_EXTINT+SAM_PID_ADC) /* PID 29: Analog To Digital Converter */
#define SAM_IRQ_ARM (SAM_IRQ_EXTINT+SAM_PID_ARM) /* PID 30: FPU signals (only on CM4P1 core): FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */
#define SAM_IRQ_IPC0 (SAM_IRQ_EXTINT+SAM_PID_IPC0) /* PID 31: Interprocessor communication 0 */
#define SAM_IRQ_SMP_CALL0 (SAM_IRQ_EXTINT+SAM_PID_IPC0) /* PID 31: Interprocessor communication 0 */
#define SAM_IRQ_SLCDC (SAM_IRQ_EXTINT+SAM_PID_SLCDC) /* PID 32: Segment LCD Controller */
#define SAM_IRQ_TRNG (SAM_IRQ_EXTINT+SAM_PID_TRNG) /* PID 33: True Random Generator */
#define SAM_IRQ_ICM (SAM_IRQ_EXTINT+SAM_PID_ICM) /* PID 34: Integrity Check Module */
@@ -122,7 +122,7 @@
#define SAM_IRQ_AES (SAM_IRQ_EXTINT+SAM_PID_AES) /* PID 36: Advanced Enhanced Standard */
#define SAM_IRQ_PIOC (SAM_IRQ_EXTINT+SAM_PID_PIOC) /* PID 37: Parallel I/O Controller C */
#define SAM_IRQ_UART1 (SAM_IRQ_EXTINT+SAM_PID_UART1) /* PID 38: Universal Asynchronous Receiver Transmitter 1 */
#define SAM_IRQ_IPC1 (SAM_IRQ_EXTINT+SAM_PID_IPC1) /* PID 39: Interprocessor communication 1 */
#define SAM_IRQ_SMP_CALL1 (SAM_IRQ_EXTINT+SAM_PID_IPC1) /* PID 39: Interprocessor communication 1 */
#define SAM_IRQ_RESERVED_40 (SAM_IRQ_EXTINT+SAM_PID_RESERVED_40) /* PID 40: Reserved */
#define SAM_IRQ_PWM (SAM_IRQ_EXTINT+SAM_PID_PWM) /* PID 41: Pulse Width Modulation */
#define SAM_IRQ_SRAM (SAM_IRQ_EXTINT+SAM_PID_SRAM) /* PID 42: SRAM1 (I/D Code bus of CM4P1), SRAM2 (Systembus of CM4P1) */
arch/arm/src/armv7-a/CMakeLists.txt
+1 -1
View File
@@ -109,7 +109,7 @@ if(CONFIG_ARCH_FPU)
endif()
if(CONFIG_SMP)
list(APPEND SRCS arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c arm_scu.c)
list(APPEND SRCS arm_cpustart.c arm_smpcall.c arm_cpuidlestack.c arm_scu.c)
endif()
if(CONFIG_ARM_PSCI)
arch/arm/src/armv7-a/Make.defs
+1 -1
View File
@@ -94,7 +94,7 @@ ifeq ($(CONFIG_ARCH_FPU),y)
endif
ifeq ($(CONFIG_SMP),y)
CMN_CSRCS += arm_cpustart.c arm_cpupause.c arm_cpuidlestack.c
CMN_CSRCS += arm_cpustart.c arm_smpcall.c arm_cpuidlestack.c
CMN_CSRCS += arm_scu.c
endif
arch/arm/src/armv7-a/arm_gicv2.c
+2 -24
View File
@@ -219,9 +219,8 @@ void arm_gic0_initialize(void)
/* Attach SGI interrupt handlers. This attaches the handler to all CPUs. */
DEBUGVERIFY(irq_attach(GIC_SMP_CPUSTART, arm_start_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_CPUPAUSE_ASYNC,
arm_pause_async_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_CPUCALL, nxsched_smp_call_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_SCHED, arm_smp_sched_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_CALL, nxsched_smp_call_handler, NULL));
#endif
arm_gic_dump("Exit arm_gic0_initialize", true, 0);
@@ -754,27 +753,6 @@ void arm_cpu_sgi(int sgi, unsigned int cpuset)
putreg32(regval, GIC_ICDSGIR);
}
#ifdef CONFIG_SMP
/****************************************************************************
* Name: up_send_smp_call
*
* Description:
* Send smp call to target cpu.
*
* Input Parameters:
* cpuset - The set of CPUs to receive the SGI.
*
* Returned Value:
* None.
*
****************************************************************************/
void up_send_smp_call(cpu_set_t cpuset)
{
up_trigger_irq(GIC_SMP_CPUCALL, cpuset);
}
#endif
/****************************************************************************
* Name: up_get_legacy_irq
*
arch/arm/src/armv7-a/arm_cpupause.c → arch/arm/src/armv7-a/arm_smpcall.c
+26 -7
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_cpupause.c
* arch/arm/src/armv7-a/arm_smpcall.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -47,10 +47,10 @@
****************************************************************************/
/****************************************************************************
* Name: arm_pause_async_handler
* Name: arm_smp_sched_handler
*
* Description:
* This is the handler for async pause.
* This is the handler for sched.
*
* 1. It saves the current task state at the head of the current assigned
* task list.
@@ -66,7 +66,7 @@
*
****************************************************************************/
int arm_pause_async_handler(int irq, void *context, void *arg)
int arm_smp_sched_handler(int irq, void *context, void *arg)
{
int cpu = this_cpu();
@@ -75,7 +75,7 @@ int arm_pause_async_handler(int irq, void *context, void *arg)
}
/****************************************************************************
* Name: up_cpu_pause_async
* Name: up_send_smp_sched
*
* Description:
* pause task execution on the CPU
@@ -93,11 +93,30 @@ int arm_pause_async_handler(int irq, void *context, void *arg)
*
****************************************************************************/
inline_function int up_cpu_pause_async(int cpu)
int up_send_smp_sched(int cpu)
{
arm_cpu_sgi(GIC_SMP_CPUPAUSE_ASYNC, (1 << cpu));
arm_cpu_sgi(GIC_SMP_SCHED, (1 << cpu));
return OK;
}
/****************************************************************************
* Name: up_send_smp_call
*
* Description:
* Send smp call to target cpu.
*
* Input Parameters:
* cpuset - The set of CPUs to receive the SGI.
*
* Returned Value:
* None.
*
****************************************************************************/
void up_send_smp_call(cpu_set_t cpuset)
{
up_trigger_irq(GIC_SMP_CALL, cpuset);
}
#endif /* CONFIG_SMP */
arch/arm/src/armv7-a/gic.h
+7 -9
View File
@@ -635,14 +635,12 @@
#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
# define GIC_SMP_CPUSTART GIC_IRQ_SGI9
# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI10
# define GIC_SMP_CPUCALL GIC_IRQ_SGI11
# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI12
# define GIC_SMP_CALL GIC_IRQ_SGI10
# define GIC_SMP_SCHED GIC_IRQ_SGI11
#else
# define GIC_SMP_CPUSTART GIC_IRQ_SGI1
# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI2
# define GIC_SMP_CPUCALL GIC_IRQ_SGI3
# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI4
# define GIC_SMP_CALL GIC_IRQ_SGI2
# define GIC_SMP_SCHED GIC_IRQ_SGI3
#endif
/****************************************************************************
@@ -836,10 +834,10 @@ int arm_start_handler(int irq, void *context, void *arg);
#endif
/****************************************************************************
* Name: arm_pause_async_handler
* Name: arm_smp_sched_handler
*
* Description:
* This is the handler for async pause.
* This is the handler for sched.
*
* 1. It saves the current task state at the head of the current assigned
* task list.
@@ -856,7 +854,7 @@ int arm_start_handler(int irq, void *context, void *arg);
****************************************************************************/
#ifdef CONFIG_SMP
int arm_pause_async_handler(int irq, void *context, void *arg);
int arm_smp_sched_handler(int irq, void *context, void *arg);
#endif
/****************************************************************************
* Name: arm_gic_dump
arch/arm/src/armv7-r/CMakeLists.txt
+1 -1
View File
@@ -71,7 +71,7 @@ if(CONFIG_SMP)
SRCS
arm_cpuhead.S
arm_cpustart.c
arm_cpupause.c
arm_smpcall.c
arm_cpuidlestack.c
arm_scu.c)
endif()
arch/arm/src/armv7-r/Make.defs
+1 -1
View File
@@ -59,6 +59,6 @@ endif
ifeq ($(CONFIG_SMP),y)
CMN_ASRCS += arm_cpuhead.S
CMN_CSRCS += arm_cpustart.c arm_cpupause.c
CMN_CSRCS += arm_cpustart.c arm_smpcall.c
CMN_CSRCS += arm_cpuidlestack.c arm_scu.c
endif
arch/arm/src/armv7-r/arm_gicv2.c
+2 -23
View File
@@ -160,9 +160,8 @@ void arm_gic0_initialize(void)
/* Attach SGI interrupt handlers. This attaches the handler to all CPUs. */
DEBUGVERIFY(irq_attach(GIC_SMP_CPUSTART, arm_start_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_CPUPAUSE_ASYNC,
arm_pause_async_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_CPUCALL, nxsched_smp_call_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_SCHED, arm_smp_sched_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_CALL, nxsched_smp_call_handler, NULL));
#endif
arm_gic_dump("Exit arm_gic0_initialize", true, 0);
@@ -659,24 +658,4 @@ int arm_gic_irq_trigger(int irq, bool edge)
return -EINVAL;
}
# ifdef CONFIG_SMP
/****************************************************************************
* Name: up_send_smp_call
*
* Description:
* Send smp call to target cpu.
*
* Input Parameters:
* cpuset - The set of CPUs to receive the SGI.
*
* Returned Value:
* None.
*
****************************************************************************/
void up_send_smp_call(cpu_set_t cpuset)
{
up_trigger_irq(GIC_SMP_CPUCALL, cpuset);
}
# endif
#endif /* CONFIG_ARMV7R_HAVE_GICv2 */
arch/arm/src/armv7-r/arm_cpupause.c → arch/arm/src/armv7-r/arm_smpcall.c
+26 -7
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_cpupause.c
* arch/arm/src/armv7-r/arm_smpcall.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -47,10 +47,10 @@
****************************************************************************/
/****************************************************************************
* Name: arm_pause_async_handler
* Name: arm_smp_sched_handler
*
* Description:
* This is the handler for async pause.
* This is the handler for sched.
*
* 1. It saves the current task state at the head of the current assigned
* task list.
@@ -66,7 +66,7 @@
*
****************************************************************************/
int arm_pause_async_handler(int irq, void *context, void *arg)
int arm_smp_sched_handler(int irq, void *context, void *arg)
{
int cpu = this_cpu();
@@ -75,7 +75,7 @@ int arm_pause_async_handler(int irq, void *context, void *arg)
}
/****************************************************************************
* Name: up_cpu_pause_async
* Name: up_send_smp_sched
*
* Description:
* pause task execution on the CPU
@@ -93,11 +93,30 @@ int arm_pause_async_handler(int irq, void *context, void *arg)
*
****************************************************************************/
inline_function int up_cpu_pause_async(int cpu)
int up_send_smp_sched(int cpu)
{
arm_cpu_sgi(GIC_SMP_CPUPAUSE_ASYNC, (1 << cpu));
arm_cpu_sgi(GIC_SMP_SCHED, (1 << cpu));
return OK;
}
/****************************************************************************
* Name: up_send_smp_call
*
* Description:
* Send smp call to target cpu.
*
* Input Parameters:
* cpuset - The set of CPUs to receive the SGI.
*
* Returned Value:
* None.
*
****************************************************************************/
void up_send_smp_call(cpu_set_t cpuset)
{
up_trigger_irq(GIC_SMP_CALL, cpuset);
}
#endif /* CONFIG_SMP */
arch/arm/src/armv7-r/gic.h
+7 -9
View File
@@ -608,14 +608,12 @@
#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
# define GIC_SMP_CPUSTART GIC_IRQ_SGI9
# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI10
# define GIC_SMP_CPUCALL GIC_IRQ_SGI11
# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI12
# define GIC_SMP_CALL GIC_IRQ_SGI10
# define GIC_SMP_SCHED GIC_IRQ_SGI11
#else
# define GIC_SMP_CPUSTART GIC_IRQ_SGI1
# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI2
# define GIC_SMP_CPUCALL GIC_IRQ_SGI3
# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI4
# define GIC_SMP_CALL GIC_IRQ_SGI2
# define GIC_SMP_SCHED GIC_IRQ_SGI3
#endif
/****************************************************************************
@@ -806,10 +804,10 @@ int arm_start_handler(int irq, void *context, void *arg);
#endif
/****************************************************************************
* Name: arm_pause_async_handler
* Name: arm_smp_sched_handler
*
* Description:
* This is the handler for async pause.
* This is the handler for sched.
*
* 1. It saves the current task state at the head of the current assigned
* task list.
@@ -826,7 +824,7 @@ int arm_start_handler(int irq, void *context, void *arg);
****************************************************************************/
#ifdef CONFIG_SMP
int arm_pause_async_handler(int irq, void *context, void *arg);
int arm_smp_sched_handler(int irq, void *context, void *arg);
#endif
/****************************************************************************
arch/arm/src/armv8-r/arm_gic.h
+5 -7
View File
@@ -311,14 +311,12 @@
#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
# define GIC_SMP_CPUSTART GIC_IRQ_SGI9
# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI10
# define GIC_SMP_CPUCALL GIC_IRQ_SGI11
# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI12
# define GIC_SMP_CALL GIC_IRQ_SGI10
# define GIC_SMP_SCHED GIC_IRQ_SGI11
#else
# define GIC_SMP_CPUSTART GIC_IRQ_SGI1
# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI2
# define GIC_SMP_CPUCALL GIC_IRQ_SGI3
# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI4
# define GIC_SMP_CALL GIC_IRQ_SGI2
# define GIC_SMP_SCHED GIC_IRQ_SGI3
#endif
/****************************************************************************
@@ -335,7 +333,7 @@ int arm_gic_raise_sgi(unsigned int sgi_id, uint16_t target_list);
#ifdef CONFIG_SMP
int arm_pause_async_handler(int irq, void *context, void *arg);
int arm_smp_sched_handler(int irq, void *context, void *arg);
void arm_gic_secondary_init(void);
#endif
arch/arm/src/armv8-r/arm_gicv3.c
+4 -26
View File
@@ -567,10 +567,8 @@ static void gicv3_dist_init(void)
#ifdef CONFIG_SMP
/* Attach SGI interrupt handlers. This attaches the handler to all CPUs. */
DEBUGVERIFY(irq_attach(GIC_SMP_CPUPAUSE_ASYNC,
arm64_pause_async_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_CPUCALL,
nxsched_smp_call_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_SCHED, arm64_smp_sched_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_CALL, nxsched_smp_call_handler, NULL));
#endif
}
@@ -814,8 +812,8 @@ static void arm_gic_init(void)
gicv3_cpuif_init();
#ifdef CONFIG_SMP
up_enable_irq(GIC_SMP_CPUCALL);
up_enable_irq(GIC_SMP_CPUPAUSE_ASYNC);
up_enable_irq(GIC_SMP_CALL);
up_enable_irq(GIC_SMP_SCHED);
#endif
}
@@ -843,24 +841,4 @@ void arm_gic_secondary_init(void)
arm_gic_init();
}
# ifdef CONFIG_SMP
/***************************************************************************
* Name: up_send_smp_call
*
* Description:
* Send smp call to target cpu.
*
* Input Parameters:
* cpuset - The set of CPUs to receive the SGI.
*
* Returned Value:
* None.
*
***************************************************************************/
void up_send_smp_call(cpu_set_t cpuset)
{
up_trigger_irq(GIC_SMP_CPUCALL, cpuset);
}
# endif
#endif
arch/arm/src/cxd56xx/CMakeLists.txt
+1 -1
View File
@@ -42,7 +42,7 @@ set(SRCS
if(CONFIG_SMP)
list(APPEND SRCS cxd56_cpuidlestack.c)
list(APPEND SRCS cxd56_cpuindex.c)
list(APPEND SRCS cxd56_cpupause.c)
list(APPEND SRCS cxd56_smpcall.c)
list(APPEND SRCS cxd56_cpustart.c)
if(CONFIG_CXD56_TESTSET)
list(APPEND SRCS cxd56_testset.c)
arch/arm/src/cxd56xx/Make.defs
+1 -1
View File
@@ -41,7 +41,7 @@ CHIP_CSRCS += cxd56_sysctl.c
ifeq ($(CONFIG_SMP), y)
CHIP_CSRCS += cxd56_cpuidlestack.c
CHIP_CSRCS += cxd56_cpuindex.c
CHIP_CSRCS += cxd56_cpupause.c
CHIP_CSRCS += cxd56_smpcall.c
CHIP_CSRCS += cxd56_cpustart.c
ifeq ($(CONFIG_CXD56_TESTSET),y)
CHIP_CSRCS += cxd56_testset.c
arch/arm/src/cxd56xx/cxd56_cpustart.c
+5 -5
View File
@@ -72,7 +72,7 @@
volatile static spinlock_t g_appdsp_boot;
extern int arm_pause_handler(int irq, void *c, void *arg);
extern int cxd56_smp_call_handler(int irq, void *c, void *arg);
/****************************************************************************
* Private Functions
@@ -117,8 +117,8 @@ static void appdsp_boot(void)
/* Enable SW_INT */
irq_attach(CXD56_IRQ_SW_INT, arm_pause_handler, NULL);
up_enable_irq(CXD56_IRQ_SW_INT);
irq_attach(CXD56_IRQ_SMP_CALL, cxd56_smp_call_handler, NULL);
up_enable_irq(CXD56_IRQ_SMP_CALL);
spin_unlock(&g_appdsp_boot);
@@ -232,8 +232,8 @@ int up_cpu_start(int cpu)
/* Setup SW_INT for this APP_DSP0 */
irq_attach(CXD56_IRQ_SW_INT, arm_pause_handler, NULL);
up_enable_irq(CXD56_IRQ_SW_INT);
irq_attach(CXD56_IRQ_SMP_CALL, cxd56_smp_call_handler, NULL);
up_enable_irq(CXD56_IRQ_SMP_CALL);
}
spin_lock(&g_appdsp_boot);
arch/arm/src/cxd56xx/cxd56_irq.c
+1 -1
View File
@@ -470,7 +470,7 @@ void up_enable_irq(int irq)
/* EXTINT needs to be handled on CPU0 to avoid deadlock */
if (irq > CXD56_IRQ_EXTINT && irq != CXD56_IRQ_SW_INT && 0 != cpu)
if (irq > CXD56_IRQ_EXTINT && irq != CXD56_IRQ_SMP_CALL && 0 != cpu)
{
up_send_irqreq(0, irq, 0);
return;
arch/arm/src/cxd56xx/cxd56_cpupause.c → arch/arm/src/cxd56xx/cxd56_smpcall.c
+7 -13
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cxd56xx/cxd56_cpupause.c
* arch/arm/src/cxd56xx/cxd56_smpcall.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -118,20 +118,14 @@ static bool handle_irqreq(int cpu)
****************************************************************************/
/****************************************************************************
* Name: arm_pause_handler
* Name: cxd56_smp_call_handler
*
* Description:
* Inter-CPU interrupt handler
*
* Input Parameters:
* Standard interrupt handler inputs
*
* Returned Value:
* Should always return OK
* This is the handler for SMP_CALL.
*
****************************************************************************/
int arm_pause_handler(int irq, void *c, void *arg)
int cxd56_smp_call_handler(int irq, void *c, void *arg)
{
int cpu = this_cpu();
int ret = OK;
@@ -152,7 +146,7 @@ int arm_pause_handler(int irq, void *c, void *arg)
}
/****************************************************************************
* Name: up_cpu_pause_async
* Name: up_send_smp_sched
*
* Description:
* pause task execution on the CPU
@@ -170,7 +164,7 @@ int arm_pause_handler(int irq, void *c, void *arg)
*
****************************************************************************/
inline_function int up_cpu_pause_async(int cpu)
int up_send_smp_sched(int cpu)
{
/* Generate IRQ for CPU(cpu) */
@@ -200,7 +194,7 @@ void up_send_smp_call(cpu_set_t cpuset)
for (; cpuset != 0; cpuset &= ~(1 << cpu))
{
cpu = ffs(cpuset) - 1;
up_cpu_pause_async(cpu);
up_send_smp_sched(cpu);
}
}
arch/arm/src/lc823450/Make.defs
+1 -1
View File
@@ -92,7 +92,7 @@ endif
ifeq ($(CONFIG_SMP), y)
CHIP_CSRCS += lc823450_cpuidlestack.c
CHIP_CSRCS += lc823450_cpuindex.c
CHIP_CSRCS += lc823450_cpupause.c
CHIP_CSRCS += lc823450_smpcall.c
CHIP_CSRCS += lc823450_cpustart.c
CHIP_CSRCS += lc823450_testset.c
CMN_ASRCS := $(filter-out arm_testset.S,$(CMN_ASRCS))
arch/arm/src/lc823450/lc823450_cpustart.c
+5 -5
View File
@@ -69,7 +69,7 @@ static volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS];
* Private Functions
****************************************************************************/
extern int lc823450_pause_handler(int irq, void *c, void *arg);
extern int lc823450_smp_call_handler(int irq, void *c, void *arg);
/****************************************************************************
* Name: cpu1_boot
@@ -106,8 +106,8 @@ static void cpu1_boot(void)
up_enable_irq(LC823450_IRQ_MEMFAULT);
#endif
irq_attach(LC823450_IRQ_CTXM3_01, lc823450_pause_handler, NULL);
up_enable_irq(LC823450_IRQ_CTXM3_01);
irq_attach(LC823450_IRQ_SMP_CALL_01, lc823450_smp_call_handler, NULL);
up_enable_irq(LC823450_IRQ_SMP_CALL_01);
}
spin_unlock(&g_cpu_wait[0]);
@@ -193,8 +193,8 @@ int up_cpu_start(int cpu)
/* IRQ setup CPU1->CPU0 */
irq_attach(LC823450_IRQ_CTXM3_11, lc823450_pause_handler, NULL);
up_enable_irq(LC823450_IRQ_CTXM3_11);
irq_attach(LC823450_IRQ_SMP_CALL_11, lc823450_smp_call_handler, NULL);
up_enable_irq(LC823450_IRQ_SMP_CALL_11);
spin_lock(&g_cpu_wait[0]);
arch/arm/src/lc823450/lc823450_cpupause.c → arch/arm/src/lc823450/lc823450_smpcall.c
+8 -14
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/lc823450/lc823450_cpupause.c
* arch/arm/src/lc823450/lc823450_smpcall.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -57,20 +57,14 @@
****************************************************************************/
/****************************************************************************
* Name: lc823450_pause_handler
* Name: lc823450_smp_call_handler
*
* Description:
* Inter-CPU interrupt handler
*
* Input Parameters:
* Standard interrupt handler inputs
*
* Returned Value:
* Should always return OK
* This is the handler for SMP_CALL.
*
****************************************************************************/
int lc823450_pause_handler(int irq, void *c, void *arg)
int lc823450_smp_call_handler(int irq, void *c, void *arg)
{
int cpu = this_cpu();
@@ -78,7 +72,7 @@ int lc823450_pause_handler(int irq, void *c, void *arg)
/* Clear : Pause IRQ */
if (irq == LC823450_IRQ_CTXM3_01)
if (irq == LC823450_IRQ_SMP_CALL_01)
{
DPRINTF("CPU0 -> CPU1\n");
putreg32(IPICLR_INTISR0_CLR_1, IPICLR);
@@ -95,7 +89,7 @@ int lc823450_pause_handler(int irq, void *c, void *arg)
}
/****************************************************************************
* Name: up_cpu_pause_async
* Name: up_send_smp_sched
*
* Description:
* pause task execution on the CPU
@@ -113,7 +107,7 @@ int lc823450_pause_handler(int irq, void *c, void *arg)
*
****************************************************************************/
inline_function int up_cpu_pause_async(int cpu)
int up_send_smp_sched(int cpu)
{
/* Execute Pause IRQ to CPU(cpu) */
@@ -150,6 +144,6 @@ void up_send_smp_call(cpu_set_t cpuset)
for (; cpuset != 0; cpuset &= ~(1 << cpu))
{
cpu = ffs(cpuset) - 1;
up_cpu_pause_async(cpu);
up_send_smp_sched(cpu);
}
}
arch/arm/src/rp2040/Make.defs
+1 -1
View File
@@ -37,7 +37,7 @@ CHIP_CSRCS += rp2040_pll.c
ifeq ($(CONFIG_SMP),y)
CHIP_CSRCS += rp2040_cpuindex.c
CHIP_CSRCS += rp2040_cpustart.c
CHIP_CSRCS += rp2040_cpupause.c
CHIP_CSRCS += rp2040_smpcall.c
CHIP_CSRCS += rp2040_cpuidlestack.c
CHIP_CSRCS += rp2040_testset.c
CMN_ASRCS := $(filter-out arm_testset.S,$(CMN_ASRCS))
arch/arm/src/rp2040/rp2040_cpustart.c
+5 -5
View File
@@ -67,7 +67,7 @@
volatile static spinlock_t g_core1_boot;
extern int arm_pause_handler(int irq, void *c, void *arg);
extern int rp2040_smp_call_handler(int irq, void *c, void *arg);
/****************************************************************************
* Private Functions
@@ -151,8 +151,8 @@ static void core1_boot(void)
/* Enable inter-processor FIFO interrupt */
irq_attach(RP2040_SIO_IRQ_PROC1, arm_pause_handler, NULL);
up_enable_irq(RP2040_SIO_IRQ_PROC1);
irq_attach(RP2040_SMP_CALL_PROC1, rp2040_smp_call_handler, NULL);
up_enable_irq(RP2040_SMP_CALL_PROC1);
spin_unlock(&g_core1_boot);
@@ -247,8 +247,8 @@ int up_cpu_start(int cpu)
/* Enable inter-processor FIFO interrupt */
irq_attach(RP2040_SIO_IRQ_PROC0, arm_pause_handler, NULL);
up_enable_irq(RP2040_SIO_IRQ_PROC0);
irq_attach(RP2040_SMP_CALL_PROC0, rp2040_smp_call_handler, NULL);
up_enable_irq(RP2040_SMP_CALL_PROC0);
spin_lock(&g_core1_boot);
arch/arm/src/rp2040/rp2040_irq.c
+2 -2
View File
@@ -276,7 +276,7 @@ void up_disable_irq(int irq)
DEBUGASSERT((unsigned)irq < NR_IRQS);
#ifdef CONFIG_SMP
if (irq >= RP2040_IRQ_EXTINT && irq != RP2040_SIO_IRQ_PROC1 &&
if (irq >= RP2040_IRQ_EXTINT && irq != RP2040_SMP_CALL_PROC1 &&
this_cpu() != 0)
{
/* Must be handled by Core 0 */
@@ -324,7 +324,7 @@ void up_enable_irq(int irq)
DEBUGASSERT((unsigned)irq < NR_IRQS);
#ifdef CONFIG_SMP
if (irq >= RP2040_IRQ_EXTINT && irq != RP2040_SIO_IRQ_PROC1 &&
if (irq >= RP2040_IRQ_EXTINT && irq != RP2040_SMP_CALL_PROC1 &&
this_cpu() != 0)
{
/* Must be handled by Core 0 */
arch/arm/src/rp2040/rp2040_cpupause.c → arch/arm/src/rp2040/rp2040_smpcall.c
+7 -13
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/rp2040/rp2040_cpupause.c
* arch/arm/src/rp2040/rp2040_smpcall.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -81,20 +81,14 @@ static void rp2040_handle_irqreq(int irqreq)
****************************************************************************/
/****************************************************************************
* Name: arm_pause_handler
* Name: rp2040_smp_call_handler
*
* Description:
* Inter-CPU interrupt handler
*
* Input Parameters:
* Standard interrupt handler inputs
*
* Returned Value:
* Should always return OK
* This is the handler for SMP_CALL.
*
****************************************************************************/
int arm_pause_handler(int irq, void *c, void *arg)
int rp2040_smp_call_handler(int irq, void *c, void *arg)
{
int cpu = this_cpu();
int irqreq;
@@ -135,7 +129,7 @@ int arm_pause_handler(int irq, void *c, void *arg)
}
/****************************************************************************
* Name: up_cpu_pause_async
* Name: up_send_smp_sched
*
* Description:
* pause task execution on the CPU
@@ -153,7 +147,7 @@ int arm_pause_handler(int irq, void *c, void *arg)
*
****************************************************************************/
inline_function int up_cpu_pause_async(int cpu)
int up_send_smp_sched(int cpu)
{
/* Generate IRQ for CPU(cpu) */
@@ -185,7 +179,7 @@ void up_send_smp_call(cpu_set_t cpuset)
for (; cpuset != 0; cpuset &= ~(1 << cpu))
{
cpu = ffs(cpuset) - 1;
up_cpu_pause_async(cpu);
up_send_smp_sched(cpu);
}
}
arch/arm/src/sam34/Make.defs
+1 -1
View File
@@ -138,7 +138,7 @@ endif # CONFIG_SAM34_TC
ifeq ($(CONFIG_SMP),y)
CHIP_CSRCS += sam4cm_cpuindex.c sam4cm_cpuidlestack.c
CHIP_CSRCS += sam4cm_cpupause.c sam4cm_cpustart.c
CHIP_CSRCS += sam4cm_smpcall.c sam4cm_cpustart.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += sam4cm_idle.c
endif
arch/arm/src/sam34/sam4cm_cpustart.c
+5 -5
View File
@@ -64,7 +64,7 @@
****************************************************************************/
volatile static spinlock_t g_cpu1_boot;
extern int arm_pause_handler(int irq, void *c, void *arg);
extern int sam4cm_smp_call_handler(int irq, void *c, void *arg);
/****************************************************************************
* Public Functions
@@ -108,8 +108,8 @@ static void cpu1_boot(void)
/* Enable : write-only */
putreg32(0x1, SAM_IPC1_IECR);
irq_attach(SAM_IRQ_IPC1, arm_pause_handler, NULL);
up_enable_irq(SAM_IRQ_IPC1);
irq_attach(SAM_IRQ_SMP_CALL1, sam4cm_smp_call_handler, NULL);
up_enable_irq(SAM_IRQ_SMP_CALL1);
}
spin_unlock(&g_cpu1_boot);
@@ -218,8 +218,8 @@ int up_cpu_start(int cpu)
sam_ipc0_enableclk();
putreg32(0x1, SAM_IPC0_ICCR); /* clear : write-only */
putreg32(0x1, SAM_IPC0_IECR); /* enable : write-only */
irq_attach(SAM_IRQ_IPC0, arm_pause_handler, NULL);
up_enable_irq(SAM_IRQ_IPC0);
irq_attach(SAM_IRQ_SMP_CALL0, sam4cm_smp_call_handler, NULL);
up_enable_irq(SAM_IRQ_SMP_CALL0);
spin_lock(&g_cpu1_boot);
arch/arm/src/sam34/sam4cm_cpupause.c → arch/arm/src/sam34/sam4cm_smpcall.c
+7 -13
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/sam34/sam4cm_cpupause.c
* arch/arm/src/sam34/sam4cm_smpcall.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -59,20 +59,14 @@
****************************************************************************/
/****************************************************************************
* Name: arm_pause_handler
* Name: sam4cm_smp_call_handler
*
* Description:
* Inter-CPU interrupt handler
*
* Input Parameters:
* Standard interrupt handler inputs
*
* Returned Value:
* Should always return OK
* This is the handler for SMP_CALL.
*
****************************************************************************/
int arm_pause_handler(int irq, void *c, void *arg)
int sam4cm_smp_call_handler(int irq, void *c, void *arg)
{
int cpu = this_cpu();
@@ -99,7 +93,7 @@ int arm_pause_handler(int irq, void *c, void *arg)
}
/****************************************************************************
* Name: up_cpu_pause_async
* Name: up_send_smp_sched
*
* Description:
* pause task execution on the CPU
@@ -117,7 +111,7 @@ int arm_pause_handler(int irq, void *c, void *arg)
*
****************************************************************************/
inline_function int up_cpu_pause_async(int cpu)
int up_send_smp_sched(int cpu)
{
/* Execute Pause IRQ to CPU(cpu) */
@@ -156,7 +150,7 @@ void up_send_smp_call(cpu_set_t cpuset)
for (; cpuset != 0; cpuset &= ~(1 << cpu))
{
cpu = ffs(cpuset) - 1;
up_cpu_pause_async(cpu);
up_send_smp_sched(cpu);
}
}
arch/arm64/src/common/CMakeLists.txt
+1 -1
View File
@@ -71,7 +71,7 @@ endif()
if(CONFIG_SMP)
list(APPEND SRCS arm64_cpuidlestack.c arm64_cpustart.c)
list(APPEND SRCS arm64_cpupause.c)
list(APPEND SRCS arm64_smpcall.c)
endif()
if(CONFIG_BUILD_KERNEL)
arch/arm64/src/common/Make.defs
+1 -1
View File
@@ -84,7 +84,7 @@ endif
ifeq ($(CONFIG_SMP),y)
CMN_CSRCS += arm64_cpuidlestack.c arm64_cpustart.c
CMN_CSRCS += arm64_cpupause.c
CMN_CSRCS += arm64_smpcall.c
endif
ifeq ($(CONFIG_BUILD_KERNEL),y)
arch/arm64/src/common/arm64_gic.h
+9 -11
View File
@@ -281,15 +281,13 @@
#define GIC_IRQ_SGI15 15
#ifdef CONFIG_ARCH_TRUSTZONE_SECURE
# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI8
# define GIC_SMP_CPUSTART GIC_IRQ_SGI9
# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI10
# define GIC_SMP_CPUCALL GIC_IRQ_SGI11
# define GIC_SMP_SCHED GIC_IRQ_SGI9
# define GIC_SMP_CPUSTART GIC_IRQ_SGI10
# define GIC_SMP_CALL GIC_IRQ_SGI11
#else
# define GIC_SMP_CPUPAUSE_ASYNC GIC_IRQ_SGI0
# define GIC_SMP_CPUSTART GIC_IRQ_SGI1
# define GIC_SMP_CPUPAUSE GIC_IRQ_SGI2
# define GIC_SMP_CPUCALL GIC_IRQ_SGI3
# define GIC_SMP_SCHED GIC_IRQ_SGI1
# define GIC_SMP_CPUSTART GIC_IRQ_SGI2
# define GIC_SMP_CALL GIC_IRQ_SGI3
#endif
/****************************************************************************
@@ -329,10 +327,10 @@ int arm64_gic_v2m_initialize(void);
#ifdef CONFIG_SMP
/****************************************************************************
* Name: arm64_pause_async_handler
* Name: arm64_smp_sched_handler
*
* Description:
* This is the handler for async pause.
* This is the handler for sched.
*
* 1. It saves the current task state at the head of the current assigned
* task list.
@@ -348,7 +346,7 @@ int arm64_gic_v2m_initialize(void);
*
****************************************************************************/
int arm64_pause_async_handler(int irq, void *context, void *arg);
int arm64_smp_sched_handler(int irq, void *context, void *arg);
void arm64_gic_secondary_init(void);
arch/arm64/src/common/arm64_gicv2.c
+2 -24
View File
@@ -864,10 +864,8 @@ static void arm_gic0_initialize(void)
#ifdef CONFIG_SMP
/* Attach SGI interrupt handlers. This attaches the handler to all CPUs. */
DEBUGVERIFY(irq_attach(GIC_SMP_CPUPAUSE_ASYNC,
arm64_pause_async_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_CPUCALL,
nxsched_smp_call_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_SCHED, arm64_smp_sched_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_CALL, nxsched_smp_call_handler, NULL));
#endif
}
@@ -1489,26 +1487,6 @@ void arm64_gic_raise_sgi(unsigned int sgi, uint16_t cpuset)
arm_cpu_sgi(sgi, cpuset);
}
# ifdef CONFIG_SMP
/****************************************************************************
* Name: up_send_smp_call
*
* Description:
* Send smp call to target cpu.
*
* Input Parameters:
* cpuset - The set of CPUs to receive the SGI.
*
* Returned Value:
* None.
*
****************************************************************************/
void up_send_smp_call(cpu_set_t cpuset)
{
up_trigger_irq(GIC_SMP_CPUCALL, cpuset);
}
# endif
#endif /* CONFIG_SMP */
/****************************************************************************
arch/arm64/src/common/arm64_gicv3.c
+4 -27
View File
@@ -649,10 +649,8 @@ static void gicv3_dist_init(void)
#ifdef CONFIG_SMP
/* Attach SGI interrupt handlers. This attaches the handler to all CPUs. */
DEBUGVERIFY(irq_attach(GIC_SMP_CPUPAUSE_ASYNC,
arm64_pause_async_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_CPUCALL,
nxsched_smp_call_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_SCHED, arm64_smp_sched_handler, NULL));
DEBUGVERIFY(irq_attach(GIC_SMP_CALL, nxsched_smp_call_handler, NULL));
#endif
}
@@ -948,8 +946,8 @@ static void arm64_gic_init(void)
gicv3_cpuif_init();
#ifdef CONFIG_SMP
up_enable_irq(GIC_SMP_CPUPAUSE_ASYNC);
up_enable_irq(GIC_SMP_CPUCALL);
up_enable_irq(GIC_SMP_SCHED);
up_enable_irq(GIC_SMP_CALL);
#endif
}
@@ -976,27 +974,6 @@ void arm64_gic_secondary_init(void)
{
arm64_gic_init();
}
# ifdef CONFIG_SMP
/***************************************************************************
* Name: up_send_smp_call
*
* Description:
* Send smp call to target cpu.
*
* Input Parameters:
* cpuset - The set of CPUs to receive the SGI.
*
* Returned Value:
* None.
*
***************************************************************************/
void up_send_smp_call(cpu_set_t cpuset)
{
up_trigger_irq(GIC_SMP_CPUCALL, cpuset);
}
# endif
#endif
/***************************************************************************
arch/arm64/src/common/arm64_cpupause.c → arch/arm64/src/common/arm64_smpcall.c
+26 -7
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm64/src/common/arm64_cpupause.c
* arch/arm64/src/common/arm64_smpcall.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -46,10 +46,10 @@
****************************************************************************/
/****************************************************************************
* Name: arm64_pause_async_handler
* Name: arm64_smp_sched_handler
*
* Description:
* This is the handler for async pause.
* This is the handler for sched.
*
* 1. It saves the current task state at the head of the current assigned
* task list.
@@ -65,7 +65,7 @@
*
****************************************************************************/
int arm64_pause_async_handler(int irq, void *context, void *arg)
int arm64_smp_sched_handler(int irq, void *context, void *arg)
{
int cpu = this_cpu();
@@ -75,7 +75,7 @@ int arm64_pause_async_handler(int irq, void *context, void *arg)
}
/****************************************************************************
* Name: up_cpu_pause_async
* Name: up_send_smp_sched
*
* Description:
* pause task execution on the CPU
@@ -93,11 +93,30 @@ int arm64_pause_async_handler(int irq, void *context, void *arg)
*
****************************************************************************/
inline_function int up_cpu_pause_async(int cpu)
int up_send_smp_sched(int cpu)
{
/* Execute SGI2 */
arm64_gic_raise_sgi(GIC_SMP_CPUPAUSE_ASYNC, (1 << cpu));
arm64_gic_raise_sgi(GIC_SMP_SCHED, (1 << cpu));
return OK;
}
/****************************************************************************
* Name: up_send_smp_call
*
* Description:
* Send smp call to target cpu.
*
* Input Parameters:
* cpuset - The set of CPUs to receive the SGI.
*
* Returned Value:
* None.
*
****************************************************************************/
void up_send_smp_call(cpu_set_t cpuset)
{
up_trigger_irq(GIC_SMP_CALL, cpuset);
}
arch/risc-v/src/common/CMakeLists.txt
+1 -1
View File
@@ -44,7 +44,7 @@ if(NOT CONFIG_ALARM_ARCH)
endif()
if(CONFIG_SMP)
list(APPEND SRCS riscv_cpuindex.c riscv_cpupause.c riscv_cpustart.c)
list(APPEND SRCS riscv_cpuindex.c riscv_smpcall.c riscv_cpustart.c)
endif()
if(CONFIG_RISCV_MISALIGNED_HANDLER)
arch/risc-v/src/common/Make.defs
+1 -1
View File
@@ -47,7 +47,7 @@ ifneq ($(CONFIG_ALARM_ARCH),y)
endif
ifeq ($(CONFIG_SMP),y)
CMN_CSRCS += riscv_cpuindex.c riscv_cpupause.c riscv_cpustart.c
CMN_CSRCS += riscv_cpuindex.c riscv_smpcall.c riscv_cpustart.c
endif
ifeq ($(CONFIG_RISCV_MISALIGNED_HANDLER),y)
arch/risc-v/src/common/riscv_exception.c
+1 -1
View File
@@ -298,7 +298,7 @@ void riscv_exception_attach(void)
irq_attach(RISCV_IRQ_RESERVED14, riscv_exception, NULL);
#ifdef CONFIG_SMP
irq_attach(RISCV_IRQ_SOFT, riscv_pause_handler, NULL);
irq_attach(RISCV_IRQ_SOFT, riscv_smp_call_handler, NULL);
#else
irq_attach(RISCV_IRQ_SOFT, riscv_exception, NULL);
#endif
arch/risc-v/src/common/riscv_internal.h
+1 -1
View File
@@ -412,7 +412,7 @@ void riscv_stack_color(void *stackbase, size_t nbytes);
#ifdef CONFIG_SMP
void riscv_cpu_boot(int cpu);
int riscv_pause_handler(int irq, void *c, void *arg);
int riscv_smp_call_handler(int irq, void *c, void *arg);
#endif
/****************************************************************************
arch/risc-v/src/common/riscv_cpupause.c → arch/risc-v/src/common/riscv_smpcall.c
+7 -14
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/risc-v/src/common/riscv_cpupause.c
* arch/risc-v/src/common/riscv_smpcall.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -48,20 +48,14 @@
****************************************************************************/
/****************************************************************************
* Name: riscv_pause_handler
* Name: riscv_smp_call_handler
*
* Description:
* Inter-CPU interrupt handler
*
* Input Parameters:
* Standard interrupt handler inputs
*
* Returned Value:
* Should always return OK
* This is the handler for SMP_CALL.
*
****************************************************************************/
int riscv_pause_handler(int irq, void *c, void *arg)
int riscv_smp_call_handler(int irq, void *c, void *arg)
{
struct tcb_s *tcb;
int cpu = this_cpu();
@@ -82,7 +76,7 @@ int riscv_pause_handler(int irq, void *c, void *arg)
}
/****************************************************************************
* Name: up_cpu_pause_async
* Name: up_send_smp_sched
*
* Description:
* pause task execution on the CPU
@@ -100,7 +94,7 @@ int riscv_pause_handler(int irq, void *c, void *arg)
*
****************************************************************************/
inline_function int up_cpu_pause_async(int cpu)
int up_send_smp_sched(int cpu)
{
/* Execute Pause IRQ to CPU(cpu) */
@@ -130,7 +124,6 @@ void up_send_smp_call(cpu_set_t cpuset)
for (; cpuset != 0; cpuset &= ~(1 << cpu))
{
cpu = ffs(cpuset) - 1;
riscv_ipi_send(cpu);
up_send_smp_sched(cpu);
}
}
arch/risc-v/src/jh7110/jh7110_timerisr.c
+1 -1
View File
@@ -79,7 +79,7 @@ static int jh7110_ssoft_interrupt(int irq, void *context, void *arg)
{
/* We assume IPI has been issued */
riscv_pause_handler(irq, context, arg);
riscv_smp_call_handler(irq, context, arg);
}
#endif
arch/sim/src/sim/sim_smpsignal.c
+6 -15
View File
@@ -60,23 +60,14 @@ static int sim_smp_call_handler(int irq, void *context, void *arg)
}
/****************************************************************************
* Name: sim_cpupause_handler
* Name: sim_smp_sched_handler
*
* Description:
* This is the SIGUSR signal handler. It implements the core logic of
* up_cpu_pause() on the thread of execution the simulated CPU.
*
* Input Parameters:
* irq - the interrupt number
* context - not used
* arg - not used
*
* Returned Value:
* In case of success OK (0) is returned otherwise a negative value.
* This is the handler for smp.
*
****************************************************************************/
static int sim_cpupause_handler(int irq, void *context, void *arg)
static int sim_smp_sched_handler(int irq, void *context, void *arg)
{
struct tcb_s *tcb;
int cpu = this_cpu();
@@ -173,11 +164,11 @@ int up_cpu_start(int cpu)
int sim_init_ipi(int irq)
{
up_enable_irq(irq);
return irq_attach(irq, sim_cpupause_handler, NULL);
return irq_attach(irq, sim_smp_sched_handler, NULL);
}
/****************************************************************************
* Name: up_cpu_pause_async
* Name: up_send_smp_sched
*
* Description:
* pause task execution on the CPU
@@ -195,7 +186,7 @@ int sim_init_ipi(int irq)
*
****************************************************************************/
inline_function int up_cpu_pause_async(int cpu)
int up_send_smp_sched(int cpu)
{
/* Generate IRQ for CPU(cpu) */
arch/sparc/src/s698pm/Make.defs
+1 -1
View File
@@ -54,5 +54,5 @@ endif
# Configuration-dependent files
ifeq ($(CONFIG_SMP),y)
CHIP_CSRCS += s698pm_cpuindex.c s698pm_cpustart.c s698pm_cpupause.c s698pm_cpuidlestack.c
CHIP_CSRCS += s698pm_cpuindex.c s698pm_cpustart.c s698pm_smpcall.c s698pm_cpuidlestack.c
endif
arch/sparc/src/s698pm/s698pm-irq.c
+1 -1
View File
@@ -185,7 +185,7 @@ int s698pm_cpuint_initialize(void)
#if defined CONFIG_SMP
/* Attach IPI interrupts */
irq_attach(S698PM_IPI_IRQ, s698pm_pause_handler, NULL);
irq_attach(S698PM_IPI_IRQ, s698pm_smp_call_handler, NULL);
(void)s698pm_setup_irq(cpu, S698PM_IPI_IRQ, 0);
arch/sparc/src/s698pm/s698pm.h
+3 -9
View File
@@ -416,21 +416,15 @@ void gpio_irqdisable(int irq);
#endif
/****************************************************************************
* Name: s698pm_pause_handler
* Name: s698pm_smp_call_handler
*
* Description:
* Inter-CPU interrupt handler
*
* Input Parameters:
* Standard interrupt handler inputs
*
* Returned Value:
* Should always return OK
* This is the handler for SMP_CALL.
*
****************************************************************************/
#ifdef CONFIG_SMP
int s698pm_pause_handler(int irq, void *c, void *arg);
int s698pm_smp_call_handler(int irq, void *c, void *arg);
#endif
#undef EXTERN
arch/sparc/src/s698pm/s698pm_cpupause.c → arch/sparc/src/s698pm/s698pm_smpcall.c
+7 -13
View File
@@ -1,5 +1,5 @@
/****************************************************************************
* arch/sparc/src/s698pm/s698pm_cpupause.c
* arch/sparc/src/s698pm/s698pm_smpcall.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -47,20 +47,14 @@
****************************************************************************/
/****************************************************************************
* Name: s698pm_pause_handler
* Name: s698pm_smp_call_handler
*
* Description:
* Inter-CPU interrupt handler
*
* Input Parameters:
* Standard interrupt handler inputs
*
* Returned Value:
* Should always return OK
* This is the handler for SMP_CALL.
*
****************************************************************************/
int s698pm_pause_handler(int irq, void *c, void *arg)
int s698pm_smp_call_handler(int irq, void *c, void *arg)
{
struct tcb_s *tcb;
int cpu = this_cpu();
@@ -80,7 +74,7 @@ int s698pm_pause_handler(int irq, void *c, void *arg)
}
/****************************************************************************
* Name: up_cpu_pause_async
* Name: up_send_smp_sched
*
* Description:
* pause task execution on the CPU
@@ -98,7 +92,7 @@ int s698pm_pause_handler(int irq, void *c, void *arg)
*
****************************************************************************/
inline_function int up_cpu_pause_async(int cpu)
int up_send_smp_sched(int cpu)
{
uintptr_t regaddr;
@@ -131,6 +125,6 @@ void up_send_smp_call(cpu_set_t cpuset)
for (; cpuset != 0; cpuset &= ~(1 << cpu))
{
cpu = ffs(cpuset) - 1;
up_cpu_pause_async(cpu);
up_send_smp_sched(cpu);
}
}
arch/x86_64/include/intel64/irq.h
+2 -2
View File
@@ -352,8 +352,8 @@
/* Use IRQ24 IRQ25 for SMP */
#define SMP_IPI_IRQ IRQ24
#define SMP_IPI_ASYNC_IRQ IRQ25
#define SMP_IPI_CALL_IRQ IRQ24
#define SMP_IPI_SCHED_IRQ IRQ25
/* Use IRQ32 and above for MSI */
arch/x86_64/src/intel64/CMakeLists.txt
+1 -1
View File
@@ -61,7 +61,7 @@ if(CONFIG_ARCH_HAVE_TESTSET)
endif()
if(CONFIG_SMP)
list(APPEND SRCS intel64_cpuidlestack.c intel64_cpupause.c intel64_cpustart.c)
list(APPEND SRCS intel64_cpuidlestack.c intel64_smpcall.c intel64_cpustart.c)
endif()
if(CONFIG_MULTBOOT2_FB_TERM)

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