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arm: Support hardware debug
Support hardware debugging of ARM architecture, and support smp mode.We can use "up_debugpoint_add" or "up_debugpoint_remove" to add breakpoints, and the hardware will jump into the interrupt after detecting it. Signed-off-by: wangmingrong1 <wangmingrong1@xiaomi.com>
This commit is contained in:
wangmingrong1
committed by
Xiang Xiao
Xiang Xiao
parent
35071467bb
commit
3149fd453c
@@ -952,6 +952,7 @@ config ARCH_ARMV7A
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bool
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default n
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select ARCH_HAVE_CPUINFO
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select ARCH_HAVE_DEBUG
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select ARCH_HAVE_PERF_EVENTS
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select ARM_HAVE_WFE_SEV
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@@ -55,6 +55,10 @@ if(CONFIG_ARMV7A_GICv2M)
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list(APPEND SRCS arm_gicv2m.c)
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endif()
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if(CONFIG_ARCH_HAVE_DEBUG)
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list(APPEND SRCS arm_hwdebug.c)
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endif()
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if(CONFIG_ARMV7A_HAVE_PTM)
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list(APPEND SRCS arm_timer.c)
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endif()
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@@ -46,6 +46,10 @@ ifeq ($(CONFIG_ARMV7A_GICv2M),y)
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CMN_CSRCS += arm_gicv2m.c
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endif
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ifeq ($(CONFIG_ARCH_HAVE_DEBUG),y)
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CMN_CSRCS += arm_hwdebug.c
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endif
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ifeq ($(CONFIG_ARMV7A_HAVE_PTM),y)
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CMN_CSRCS += arm_timer.c
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endif
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@@ -0,0 +1,497 @@
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/****************************************************************************
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* arch/arm/src/armv7-a/arm_hwdebug.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <stdint.h>
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#include <string.h>
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#include <assert.h>
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#include <debug.h>
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#include <arch/armv7-a/cp14.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Watchpoint and breakpoint control register share bits */
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#define CP14_DBGBWCR_E CP14_DBGBCR_E
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#define CP14_DBGBWCR_PAC_USER CP14_DBGBCR_PAC_USER
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#define CP14_DBGBWCR_LSC_OFFSET CP14_DBGBCR_LSC_OFFSET
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#define CP14_DBGBWCR_LSC_EXECUTE CP14_DBGBCR_LSC_EXECUTE
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#define CP14_DBGBWCR_LSC_LOAD CP14_DBGBCR_LSC_LOAD
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#define CP14_DBGBWCR_LSC_STORE CP14_DBGBCR_LSC_STORE
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#define CP14_DBGBWCR_BAS_OFFSET CP14_DBGBCR_BAS_OFFSET
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#define CP14_DBGBWCR_BAS_LEN_1 CP14_DBGBCR_BAS_LEN_1
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#define CP14_DBGBWCR_BAS_LEN_2 CP14_DBGBCR_BAS_LEN_2
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#define CP14_DBGBWCR_BAS_LEN_4 CP14_DBGBCR_BAS_LEN_4
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#define CP14_DBGBWCR_BAS_LEN_8 CP14_DBGBCR_BAS_LEN_8
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/* Encode the bp control register field as a 32-bit value */
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#define CP14_DBGBWCR_VAL(type, len) \
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(arm_convert_type(type) | arm_convert_size(len) | \
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CP14_DBGBCR_PAC_ALL | CP14_DBGBWCR_E)
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/****************************************************************************
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* Private Type
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****************************************************************************/
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struct arm_debugpoint_s
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{
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int type;
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void *addr;
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size_t size;
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debug_callback_t callback;
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void *arg;
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};
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struct arm_debug_s
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{
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/* Breakpoint currently in use for each BRP, WRP */
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struct arm_debugpoint_s brps[CP14_DBGDIDR_MAX_BRP];
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struct arm_debugpoint_s wrps[CP14_DBGDIDR_MAX_WRP];
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};
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static struct arm_debug_s g_arm_debug[CONFIG_SMP_NCPUS];
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/****************************************************************************
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* Private Function
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****************************************************************************/
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static uint32_t arm_convert_type(int type)
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{
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switch (type)
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{
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case DEBUGPOINT_WATCHPOINT_RO:
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return CP14_DBGBWCR_LSC_LOAD << CP14_DBGBWCR_LSC_OFFSET;
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case DEBUGPOINT_WATCHPOINT_WO:
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return CP14_DBGBWCR_LSC_STORE << CP14_DBGBWCR_LSC_OFFSET;
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case DEBUGPOINT_WATCHPOINT_RW:
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return (CP14_DBGBWCR_LSC_LOAD | CP14_DBGBWCR_LSC_STORE)
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<< CP14_DBGBWCR_LSC_OFFSET;
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case DEBUGPOINT_BREAKPOINT:
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case DEBUGPOINT_STEPPOINT:
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default:
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return CP14_DBGBWCR_LSC_EXECUTE << CP14_DBGBWCR_LSC_OFFSET;
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}
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}
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static uint32_t arm_convert_size(size_t len)
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{
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switch (len)
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{
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case 1:
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return CP14_DBGBWCR_BAS_LEN_1 << CP14_DBGBWCR_BAS_OFFSET;
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case 2:
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return CP14_DBGBWCR_BAS_LEN_2 << CP14_DBGBWCR_BAS_OFFSET;
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case 4:
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return CP14_DBGBWCR_BAS_LEN_4 << CP14_DBGBWCR_BAS_OFFSET;
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case 8:
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default:
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return CP14_DBGBWCR_BAS_LEN_8 << CP14_DBGBWCR_BAS_OFFSET;
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}
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}
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/* Determine number of usable WRPs available. */
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static int arm_get_num_wrps(void)
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{
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return ((CP14_GET(DBGDIDR) >> CP14_DBGDIDR_WRPS_OFFSET)
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& CP14_DBGDIDR_WRPS_MASK) + 1;
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}
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/* Determine number of usable BRPs available. */
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static int arm_get_num_brps(void)
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{
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return ((CP14_GET(DBGDIDR) >> CP14_DBGDIDR_BRPS_OFFSET)
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& CP14_DBGDIDR_BRPS_MASK) + 1;
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}
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/****************************************************************************
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* Name: up_watchpoint_add
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*
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* Description:
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* Add a watchpoint on the address.
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*
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* Input Parameters:
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* type - The type of the watchpoint
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* addr - The address to be watched
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* size - The size of the address to be watched
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*
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* Returned Value:
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* Index in wprs array on success; a negated errno value on failure
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*
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* Notes:
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* The size of the watchpoint is determined by the hardware.
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*
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****************************************************************************/
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static int arm_watchpoint_add(int type, uint32_t addr, size_t size)
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{
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int num = arm_get_num_wrps();
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int i;
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for (i = 0; i < num; i++)
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{
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if (!(CP14_GETN(DBGWCR, i) & CP14_DBGBWCR_E))
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{
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CP14_SETN(DBGWVR, i, CP14_MASK_ADDR(addr));
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CP14_SETN(DBGWCR, i, CP14_DBGBWCR_VAL(type, size));
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return i;
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}
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}
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return -ENOSPC;
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}
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/****************************************************************************
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* Name: arm_watchpoint_remove
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*
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* Description:
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* Remove a watchpoint on the address.
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*
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* Input Parameters:
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* addr - The address to be watched.
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*
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* Returned Value:
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* Index in wprs array on success; a negated errno value on failure
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*
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****************************************************************************/
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static int arm_watchpoint_remove(uint32_t addr)
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{
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int num = arm_get_num_wrps();
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int i;
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for (i = 0; i < num; i++)
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{
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if (CP14_GETN(DBGWVR, i) == CP14_MASK_ADDR(addr))
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{
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CP14_SETN(DBGWCR, i, 0);
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return i;
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}
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}
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return -ENOENT;
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}
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/****************************************************************************
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* Name: arm_breakpoint_add
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*
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* Description:
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* Add a breakpoint on addr.
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*
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* Input Parameters:
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* addr - The address to break.
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*
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* Returned Value:
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* Index in bprs array on success; a negated errno value on failure
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*
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* Notes:
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* 1. If breakpoint is already set, it will do nothing.
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* 2. If all comparators are in use, it will return -1.
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* 3. When the breakpoint trigger, if enable monitor exception already ,
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* will cause a debug monitor exception, oaddr=0x4020392ctherwise will
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* cause a hard fault.
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*
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****************************************************************************/
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static int arm_breakpoint_add(uintptr_t addr)
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{
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int num = arm_get_num_brps();
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int i;
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for (i = 0; i < num; i++)
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{
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if (!(CP14_GETN(DBGBCR, i) & CP14_DBGBWCR_E))
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{
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CP14_SETN(DBGBVR, i, CP14_MASK_ADDR(addr));
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CP14_SETN(DBGBCR, i, CP14_DBGBWCR_VAL(DEBUGPOINT_BREAKPOINT, 8));
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return i;
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}
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}
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return -ENOSPC;
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}
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/****************************************************************************
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* Name: arm_breakpoint_remove
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*
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* Description:
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* Remove a breakpoint on addr.
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*
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* Input Parameters:
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* addr - The address to remove.
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*
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* Returned Value:
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* Index in bprs array on success; a negated errno value on failure
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*
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****************************************************************************/
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static int arm_breakpoint_remove(uintptr_t addr)
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{
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int num = arm_get_num_brps();
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int i;
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for (i = 0; i < num; i++)
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{
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if (CP14_GETN(DBGBVR, i) == CP14_MASK_ADDR(addr))
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{
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CP14_SETN(DBGBCR, i, 0);
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return i;
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}
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}
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return -ENOENT;
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}
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static void arm_watchpoint_match(uint32_t addr)
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{
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struct arm_debugpoint_s *dp = g_arm_debug[this_cpu()].wrps;
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int num = arm_get_num_wrps();
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int i;
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for (i = 0; i < num; i++)
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{
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if (CP14_MASK_ADDR(dp[i].addr) == CP14_MASK_ADDR(addr))
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{
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dp[i].callback(dp[i].type, dp[i].addr,
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dp[i].size, dp[i].arg);
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break;
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}
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}
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}
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static void arm_breakpoint_match(uint32_t addr)
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{
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struct arm_debugpoint_s *dp = g_arm_debug[this_cpu()].brps;
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int num = arm_get_num_brps();
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int i;
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for (i = 0; i < num; i++)
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{
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if (CP14_MASK_ADDR(dp[i].addr) == CP14_MASK_ADDR(addr))
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{
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dp[i].callback(dp[i].type, dp[i].addr,
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dp[i].size, dp[i].arg);
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break;
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}
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}
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: arm_enable_dbgmonitor
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*
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* Description:
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* This function enables the debug monitor exception.
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*
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****************************************************************************/
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int arm_enable_dbgmonitor(void)
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{
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/* Determine how many BRPs/WRPs are available.
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* And work out the maximum supported watchpoint length.
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*/
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binfo("found %d breakpoint and %d watchpoint registers.\n",
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arm_get_num_brps(), arm_get_num_wrps());
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/* If monitor mode is already enabled, just return. */
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if (CP14_GET(DBGDSCRINT) & CP14_DBGDSCRINT_MDBGEN)
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{
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return OK;
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}
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CP14_MOD(DBGDSCREXT, CP14_DBGDSCRINT_MDBGEN, CP14_DBGDSCRINT_MDBGEN);
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/* Check that the write made it through. */
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if (!(CP14_GET(DBGDSCRINT) & CP14_DBGDSCRINT_MDBGEN))
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{
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return -EPERM;
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}
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return OK;
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}
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/****************************************************************************
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* Name: arm_dbgmonitor
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*
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* Description:
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* This is Debug Monitor exception handler. This function is entered when
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* the processor enters debug mode. The debug monitor handler will handle
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* debug events, and resume execution.
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*
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****************************************************************************/
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int arm_dbgmonitor(int irq, void *context, void *arg)
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{
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switch (((CP14_GET(DBGDSCRINT)) >> CP14_DBGDSCRINT_MOE_OFFSET)
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& CP14_DBGDSCRINT_MOE_MASK)
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{
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case CP14_DBGDSCRINT_MOE_BREAKPOINT:
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case CP14_DBGDSCRINT_MOE_CFI_BREAKPOINT:
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arm_breakpoint_match((uintptr_t)context);
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break;
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case CP14_DBGDSCRINT_MOE_ASYNC_WATCHPOINT:
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case CP14_DBGDSCRINT_MOE_SYNC_WATCHPOINT:
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arm_watchpoint_match((uintptr_t)context);
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break;
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}
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return OK;
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}
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/****************************************************************************
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* Name: up_debugpoint_add
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*
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* Description:
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* Add a debugpoint.
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*
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* Input Parameters:
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* type - The debugpoint type. optional value:
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* DEBUGPOINT_WATCHPOINT_RO - Read only watchpoint.
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* DEBUGPOINT_WATCHPOINT_WO - Write only watchpoint.
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* DEBUGPOINT_WATCHPOINT_RW - Read and write watchpoint.
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* DEBUGPOINT_BREAKPOINT - Breakpoint.
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* DEBUGPOINT_STEPPOINT - Single step.
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* addr - The address to be debugged.
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* size - The watchpoint size. only for watchpoint.
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* callback - The callback function when debugpoint triggered.
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* if NULL, the debugpoint will be removed.
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* arg - The argument of callback function.
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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****************************************************************************/
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int up_debugpoint_add(int type, void *addr, size_t size,
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debug_callback_t callback, void *arg)
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{
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struct arm_debugpoint_s *dp;
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int cpu = this_cpu();
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int ret = -EINVAL;
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if (type == DEBUGPOINT_BREAKPOINT)
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{
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ret = arm_breakpoint_add((uintptr_t)addr);
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dp = g_arm_debug[cpu].brps;
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}
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else if (type == DEBUGPOINT_WATCHPOINT_RO ||
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type == DEBUGPOINT_WATCHPOINT_WO ||
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type == DEBUGPOINT_WATCHPOINT_RW)
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{
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ret = arm_watchpoint_add(type, (uintptr_t)addr, size);
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dp = g_arm_debug[cpu].wrps;
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}
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if (ret < 0)
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{
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return ret;
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}
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dp[ret].type = type;
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dp[ret].addr = addr;
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dp[ret].size = size;
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dp[ret].callback = callback;
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dp[ret].arg = arg;
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return OK;
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}
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/****************************************************************************
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* Name: up_debugpoint_remove
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*
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* Description:
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* Remove a debugpoint.
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*
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* Input Parameters:
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* type - The debugpoint type. optional value:
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* DEBUGPOINT_WATCHPOINT_RO - Read only watchpoint.
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* DEBUGPOINT_WATCHPOINT_WO - Write only watchpoint.
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* DEBUGPOINT_WATCHPOINT_RW - Read and write watchpoint.
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* DEBUGPOINT_BREAKPOINT - Breakpoint.
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* DEBUGPOINT_STEPPOINT - Single step.
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* addr - The address to be debugged.
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* size - The watchpoint size. only for watchpoint.
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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****************************************************************************/
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int up_debugpoint_remove(int type, void *addr, size_t size)
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{
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struct arm_debugpoint_s *dp;
|
||||
int cpu = this_cpu();
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (type == DEBUGPOINT_BREAKPOINT)
|
||||
{
|
||||
ret = arm_breakpoint_remove((uintptr_t)addr);
|
||||
dp = g_arm_debug[cpu].brps;
|
||||
}
|
||||
else if (type == DEBUGPOINT_WATCHPOINT_RO ||
|
||||
type == DEBUGPOINT_WATCHPOINT_WO ||
|
||||
type == DEBUGPOINT_WATCHPOINT_RW)
|
||||
{
|
||||
ret = arm_watchpoint_remove((uintptr_t)addr);
|
||||
dp = g_arm_debug[cpu].wrps;
|
||||
}
|
||||
|
||||
if (ret < 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
dp[ret].type = 0;
|
||||
dp[ret].addr = 0;
|
||||
dp[ret].size = 0;
|
||||
dp[ret].callback = NULL;
|
||||
dp[ret].arg = NULL;
|
||||
|
||||
return OK;
|
||||
}
|
||||
@@ -332,8 +332,6 @@ EXTERN const void * const _vectors[];
|
||||
|
||||
int arm_svcall(int irq, void *context, void *arg);
|
||||
int arm_hardfault(int irq, void *context, void *arg);
|
||||
int arm_enable_dbgmonitor(void);
|
||||
int arm_dbgmonitor(int irq, void *context, void *arg);
|
||||
|
||||
# if defined(CONFIG_ARCH_ARMV7M) || defined(CONFIG_ARCH_ARMV8M)
|
||||
|
||||
@@ -495,6 +493,11 @@ void arm_stack_check_init(void) noinstrument_function;
|
||||
void arm_coredump_add_region(void);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_HAVE_DEBUG
|
||||
int arm_enable_dbgmonitor(void);
|
||||
int arm_dbgmonitor(int irq, void *context, void *arg);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user