Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-05-20 20:44:39 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

SAMA5 NAND: Add block erase logic

Browse Source
This commit is contained in:
Gregory Nutt
2013-11-20 13:55:23 -06:00
parent 9e804749e9
commit 31004d1cf7
6 changed files with 945 additions and 64 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/sama5/chip/sam_hsmc.h
+49
View File
@@ -53,6 +53,9 @@
#define HSMC_CS2 2
#define HSMC_CS3 3
#define NFCSRAM_BASE SAM_NFCSRAM_VSECTION
#define NFCCMD_BASE SAM_NFCCR_VSECTION
/* SMC Register Offsets *************************************************************/
#define SAM_HSMC_CFG_OFFSET 0x0000 /* HSMC NFC Configuration Register */
@@ -572,4 +575,50 @@
#define HSMC_WPSR_WPVSRC_SHIFT (8) /* Bit 8-23: Write Protection Violation Source */
#define HSMC_WPSR_WPVSRC_MASK (0xffff << HSMC_WPSR_WPVSRC_SHIFT)
/* NFC Command/Data Registers *******************************************************/
#define NFCADDR_CMD_CMD1_SHIFT (2) /* Bits 2-9: Command Register Value for Cycle 1 */
#define NFCADDR_CMD_CMD1_MASK (0xff << NFCADDR_CMD_CMD1_SHIFT)
# define NFCADDR_CMD_CMD1(n) ((uint32_t)(n) << NFCADDR_CMD_CMD1_SHIFT)
#define NFCADDR_CMD_CMD2_SHIFT (10) /* Bits 10-17: Command Register Value for Cycle 1 */
#define NFCADDR_CMD_CMD2_MASK (0xff << NFCADDR_CMD_CMD2_SHIFT)
# define NFCADDR_CMD_CMD2(n) ((uint32_t)(n) << NFCADDR_CMD_CMD2_SHIFT)
#define NFCADDR_CMD_VCMD2 (1 << 18) /* Bit 18:Valid Cycle 2 Command */
#define NFCADDR_CMD_ACYCLE_SHIFT (19) /* Bits 19-21: Number of Address required for command */
#define NFCADDR_CMD_ACYCLE_MASK (7 << NFCADDR_CMD_ACYCLE_SHIFT)
# define NFCADDR_CMD_ACYCLE_NONE (0 << NFCADDR_CMD_ACYCLE_SHIFT) /* No address cycle */
# define NFCADDR_CMD_ACYCLE_ONE (1 << NFCADDR_CMD_ACYCLE_SHIFT) /* One address cycle */
# define NFCADDR_CMD_ACYCLE_TWO (2 << NFCADDR_CMD_ACYCLE_SHIFT) /* Two address cycles */
# define NFCADDR_CMD_ACYCLE_THREE (3 << NFCADDR_CMD_ACYCLE_SHIFT) /* Three address cycles */
# define NFCADDR_CMD_ACYCLE_FOUR (4 << NFCADDR_CMD_ACYCLE_SHIFT) /* Four address cycles */
# define NFCADDR_CMD_ACYCLE_FIVE (5 << NFCADDR_CMD_ACYCLE_SHIFT) /* Five address cycles */
#define NFCADDR_CMD_CSID_SHIFT (22) /* Bits 22-24: Chip Select Identifier */
#define NFCADDR_CMD_CSID_MASK (7 << NFCADDR_CMD_CSID_SHIFT) /* Bits 22-24: Chip Select Identifier */
# define NFCADDR_CMD_CSID_0 (0 << NFCADDR_CMD_CSID_SHIFT) /* CS0 */
# define NFCADDR_CMD_CSID_1 (1 << NFCADDR_CMD_CSID_SHIFT) /* CS1 */
# define NFCADDR_CMD_CSID_2 (2 << NFCADDR_CMD_CSID_SHIFT) /* CS2 */
# define NFCADDR_CMD_CSID_3 (3 << NFCADDR_CMD_CSID_SHIFT) /* CS3 */
# define NFCADDR_CMD_CSID_4 (4 << NFCADDR_CMD_CSID_SHIFT) /* CS4 */
# define NFCADDR_CMD_CSID_5 (5 << NFCADDR_CMD_CSID_SHIFT) /* CS5 */
# define NFCADDR_CMD_CSID_6 (6 << NFCADDR_CMD_CSID_SHIFT) /* CS6 */
# define NFCADDR_CMD_CSID_7 (7 << NFCADDR_CMD_CSID_SHIFT) /* CS7 */
#define NFCADDR_CMD_DATAEN (1 << 25) /* Bit 25: 1=NFC Data Enable */
#define NFCADDR_CMD_DATADIS (0 << 25) /* Bit 25: 0=NFC Data disable */
#define NFCADDR_CMD_NFCRD (0 << 26) /* Bit 26: 0=NFC Read Enable */
#define NFCADDR_CMD_NFCWR (1 << 26) /* Bit 26: 1=NFC Write Enable */
#define NFCADDR_CMD_NFCCMD (1 << 27) /* Bit 27: 1=NFC Command Enable */
#define NFCDATA_ADDT_CYCLE1_SHIFT (0) /* Bits 0-7: NAND Flash Array Address Cycle 1 */
#define NFCDATA_ADDT_CYCLE1_MASK (0xff << NFCDATA_ADDT_CYCLE1_SHIFT)
# define NFCDATA_ADDT_CYCLE1(n) ((uint32_t)(n) << NFCDATA_ADDT_CYCLE1_SHIFT)
#define NFCDATA_ADDT_CYCLE2_SHIFT (8) /* Bits 8-15: NAND Flash Array Address Cycle 2 */
#define NFCDATA_ADDT_CYCLE2_MASK (0xff << NFCDATA_ADDT_CYCLE2_SHIFT)
# define NFCDATA_ADDT_CYCLE2(n) ((uint32_t)(n) << NFCDATA_ADDT_CYCLE2_SHIFT)
#define NFCDATA_ADDT_CYCLE3_SHIFT (nn) /* Bits 16-23: NAND Flash Array Address Cycle 3 */
#define NFCDATA_ADDT_CYCLE3_MASK (16 << NFCDATA_ADDT_CYCLE3_SHIFT)
# define NFCDATA_ADDT_CYCLE3(n) ((uint32_t)(n) << NFCDATA_ADDT_CYCLE3_SHIFT)
#define NFCDATA_ADDT_CYCLE4_SHIFT (24) /* Bits 24-31: NAND Flash Array Address Cycle 4 */
#define NFCDATA_ADDT_CYCLE4_MASK (0xff << NFCDATA_ADDT_CYCLE4_SHIFT)
# define NFCDATA_ADDT_CYCLE4(n) ((uint32_t)(n) << NFCDATA_ADDT_CYCLE4_SHIFT)
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_HSMC_H */
arch/arm/src/sama5/sam_hsmci.c
+2 -2
View File
@@ -681,7 +681,7 @@ static bool sam_checkreg(struct sam_dev_s *priv, bool wr, uint32_t value,
* Name: sam_getreg
*
* Description:
* Read an SPI register
* Read an HSMCI register
*
****************************************************************************/
@@ -704,7 +704,7 @@ static inline uint32_t sam_getreg(struct sam_dev_s *priv, unsigned int offset)
* Name: sam_putreg
*
* Description:
* Write a value to an SPI register
* Write a value to an HSMCI register
*
****************************************************************************/
arch/arm/src/sama5/sam_nand.c
+610 -53
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/sama5/sam_nand.h
+275
View File
@@ -42,6 +42,10 @@
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <debug.h>
#include <nuttx/mtd/nand_raw.h>
#include "chip.h"
@@ -96,6 +100,36 @@
#define NANDECC_PMECC (NANDECC_HWECC + 1)
#define NANDECC_HSIAO (NANDECC_HWECC + 2)
/****************************************************************************
* Public Types
****************************************************************************/
/* This type represents the state of a raw NAND MTD device on a single chip
* select. The struct nand_raw_s must appear at the beginning of the
* definition so that you can freely cast between pointers to struct
* nand_raw_s and struct sam_nandcs_s.
*/
struct sam_nandcs_s
{
struct nand_raw_s raw; /* Externally visible part of the driver */
uint8_t cs :2; /* Chip select number (0..3) */
uint8_t nfcen :1; /* True: NFC is enabled */
uint8_t nfcsram :1; /* True: Use NFC SRAM */
uint8_t dmaxfr :1; /* True: Use DMA transfers */
};
/* Register debug state */
#ifdef CONFIG_SAMA5_NAND_REGDEBUG
struct sam_nanddbg_s
{
bool wr; /* Last was a write */
uint32_t regadddr; /* Last address */
uint32_t regval; /* Last value */
int ntimes; /* Number of times */
};
#endif
/****************************************************************************
* Public Data
****************************************************************************/
@@ -110,6 +144,12 @@ extern "C" {
#define EXTERN extern
#endif
/* NAND regiser debug state */
#ifdef CONFIG_SAMA5_NAND_REGDEBUG
EXTERN struct sam_nanddbg_s g_nanddbg;
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -203,6 +243,241 @@ bool board_nand_busy(int cs);
void board_nand_ce(int cs, bool enable);
#endif
/****************************************************************************
* Name: nand_checkreg
*
* Description:
* Check if the current HSMC register access is a duplicate of the preceding.
*
* Input Parameters:
* regval - The value to be written
* regaddr - The address of the register to write to
*
* Returned Value:
* true: This is the first register access of this type.
* flase: This is the same as the preceding register access.
*
****************************************************************************/
#ifdef CONFIG_SAMA5_NAND_REGDEBUG
bool nand_checkreg(bool wr, uintptr_t regaddr, uint32_t regval);
#endif
/****************************************************************************
* Name: nand_getreg
*
* Description:
* Read an HSMC register
*
****************************************************************************/
static inline uint32_t nand_getreg(uintptr_t regaddr)
{
uint32_t regval = getreg32(regaddr);
#ifdef CONFIG_SAMA5_NAND_REGDEBUG
if (nand_checkreg(false, regaddr, regval))
{
lldbg("%08x->%08x\n", regaddr, regval);
}
#endif
return regval;
}
/****************************************************************************
* Name: nand_putreg
*
* Description:
* Write a value to an HSMC register
*
****************************************************************************/
static inline void nand_putreg(uintptr_t regaddr, uint32_t regval)
{
#ifdef CONFIG_SAMA5_NAND_REGDEBUG
if (nand_checkreg(true, regaddr, regval))
{
lldbg("%08x<-%08x\n", regaddr, regval);
}
#endif
putreg32(regval, regaddr);
}
/****************************************************************************
* Name: nand_nfc_enable
*
* Description:
* Enable the NAND FLASH controller
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline void nand_nfc_enable(struct sam_nandcs_s *priv)
{
priv->nfcen = true;
nand_putreg(SAM_HSMC_CTRL, HSMC_CTRL_NFCEN);
}
/****************************************************************************
* Name: nand_nfc_enable
*
* Description:
* Enable the NAND FLASH controller
*
* Input Parameters:
* priv - A reference to the NAND chip select data structure
*
* Returned Value:
* None
*
****************************************************************************/
static inline void nand_nfc_disable(struct sam_nandcs_s *priv)
{
priv->nfcen = false;
nand_putreg(SAM_HSMC_CTRL, HSMC_CTRL_NFCDIS);
}
/****************************************************************************
* Name: nand_nfc_enabled
*
* Description:
* Return the state of the NAND FLASH controller
*
* Input Parameters:
* priv - A reference to the NAND chip select data structure
*
* Returned Value:
* True if the NAND FLASH controller is enabled
*
****************************************************************************/
static inline uint8_t nand_nfc_enabled(struct sam_nandcs_s *priv)
{
return (bool)priv->nfcen;
}
/****************************************************************************
* Name: nand_nfcsram_enable
*
* Description:
* Enable use of NFC Host SRAM
*
* Input Parameters:
* priv - A reference to the NAND chip select data structure
*
* Returned Value:
* None
*
****************************************************************************/
static inline void nand_nfcsram_enable(struct sam_nandcs_s *priv)
{
priv->nfcsram = true;
}
/****************************************************************************
* Name: nand_nfcsram_disable
*
* Description:
* Disable use of NFC Host SRAM
*
* Input Parameters:
* priv - A reference to the NAND chip select data structure
*
* Returned Value:
* None
*
****************************************************************************/
static inline void nand_nfcsram_disable(struct sam_nandcs_s *priv)
{
priv->nfcsram = false;
}
/****************************************************************************
* Name: nand_nfcsram_enabled
*
* Description:
* Returrn the state of the NFS Host SRAM
*
* Input Parameters:
* priv - A reference to the NAND chip select data structure
*
* Returned Value:
* True if the NFC Host SRAM is used
*
****************************************************************************/
static inline bool nand_nfcsram_enabled(struct sam_nandcs_s *priv)
{
return (bool)priv->nfcsram;
}
/****************************************************************************
* Name: nand_nanddma_enable
*
* Description:
* Enable use of DMA to perform transfers
*
* Input Parameters:
* priv - A reference to the NAND chip select data structure
*
* Returned Value:
* None
*
****************************************************************************/
static inline void nand_nanddma_enable(struct sam_nandcs_s *priv)
{
priv->dmaxfr = true;
}
/****************************************************************************
* Name: nand_nanddma_disable
*
* Description:
* Disable use of DMA to perform transfers
*
* Input Parameters:
* priv - A reference to the NAND chip select data structure
*
* Returned Value:
* None
*
****************************************************************************/
void nand_nanddma_disable(struct sam_nandcs_s *priv)
{
priv->dmaxfr = false;
}
/****************************************************************************
* Name: nand_nanddma_enabled
*
* Description:
* Returrn the state of the DMA usage
*
* Input Parameters:
* priv - A reference to the NAND chip select data structure
*
* Returned Value:
* True if transfers are performed using DMA
*
****************************************************************************/
bool nand_nanddma_enabled(struct sam_nandcs_s *priv)
{
return priv->dmaxfr;
}
#undef EXTERN
#if defined(__cplusplus)
}
include/nuttx/mtd/nand_model.h
+1 -1
View File
@@ -259,7 +259,7 @@ int nandmodel_translate(FAR const struct nand_model_s *model, off_t address,
****************************************************************************/
#define nandmodel_pagesperblock(m) \
((uint32_t)((m)->blocksize << 10) / model->pagesize)
((uint32_t)((m)->blocksize << 10) / (m)->pagesize)
/****************************************************************************
* Name: nandmodel_getdevpagesize
include/nuttx/mtd/nand_raw.h
+8 -8
View File
@@ -104,21 +104,21 @@
/* NAND access macros */
#define WRITE_COMMAND8(raw, command) \
{*((volatile uint8_t *)raw->cmdaddr) = (uint8_t)command;}
{*((volatile uint8_t *)(raw)->cmdaddr) = (uint8_t)command;}
#define WRITE_COMMAND16(raw, command) \
{*((volatile uint16_t *)raw->cmdaddr) = (uint16_t)command;}
{*((volatile uint16_t *)(raw)->cmdaddr) = (uint16_t)command;}
#define WRITE_ADDRESS8(raw, address) \
{*((volatile uint8_t *)raw->addraddr) = (uint8_t)address;}
{*((volatile uint8_t *)(raw)->addraddr) = (uint8_t)address;}
#define WRITE_ADDRESS16(raw, address) \
{*((volatile uint16_t *)raw->addraddr) = (uint16_t)address;}
{*((volatile uint16_t *)(raw)->addraddr) = (uint16_t)address;}
#define WRITE_DATA8(raw, data) \
{*((volatile uint8_t *)raw->dataaddr) = (uint8_t)data;}
{*((volatile uint8_t *)(raw)->dataaddr) = (uint8_t)data;}
#define READ_DATA8(raw) \
(*((volatile uint8_t *)raw->dataaddr))
(*((volatile uint8_t *)(raw)->dataaddr))
#define WRITE_DATA16(raw, data) \
{*((volatile uint16_t *) raw->dataaddr) = (uint16_t)data;}
{*((volatile uint16_t *)(raw)->dataaddr) = (uint16_t)data;}
#define READ_DATA16(raw) \
(*((volatile uint16_t *)raw->dataaddr))
(*((volatile uint16_t *)(raw)->dataaddr))
/* struct nand_raw_s operations */