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Merged in raiden00/nuttx (pull request #236)
STM32F33XX DAC, OPAMP, COMP and ADC headers Approved-by: Gregory Nutt
This commit is contained in:
Mateusz Szafoni
Gregory Nutt
@@ -177,7 +177,7 @@
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# define DAC_CR_TSEL1_TIM4 (5 << DAC_CR_TSEL1_SHIFT) /* Timer 4 TRGO event */
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# define DAC_CR_TSEL1_EXT9 (6 << DAC_CR_TSEL1_SHIFT) /* External line9 */
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# define DAC_CR_TSEL1_SW (7 << DAC_CR_TSEL1_SHIFT) /* Software trigger */
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#define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel 1 noise/triangle wave generation */enable
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#define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel 1 noise/triangle wave generation */
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#define DAC_CR_WAVE1_MASK (3 << DAC_CR_WAVE1_SHIFT)
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# define DAC_CR_WAVE1_DISABLED (0 << DAC_CR_WAVE1_SHIFT) /* Wave generation disabled */
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# define DAC_CR_WAVE1_NOISE (1 << DAC_CR_WAVE1_SHIFT) /* Noise wave generation enabled */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,124 @@
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/****************************************************************************************************
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* arch/arm/src/stm32/chip/stm32f33xxx_comp.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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||||
* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_COMP_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32_COMP_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* Register Offsets *********************************************************************************/
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#define STM32_COMP2_CSR_OFFSET 0x0020 /* COMP2 Control register */
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#define STM32_COMP4_CSR_OFFSET 0x0028 /* COMP4 Control register */
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#define STM32_COMP6_CSR_OFFSET 0x0030 /* COMP6 Control register */
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/* Register Addresses *******************************************************************************/
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#define STM32_COMP2_CSR (STM32_COMP_BASE+STM32_COMP2_CSR_OFFSET)
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#define STM32_COMP4_CSR (STM32_COMP_BASE+STM32_COMP4_CSR_OFFSET)
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#define STM32_COMP6_CSR (STM32_COMP_BASE+STM32_COMP6_CSR_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* COMP control and status register */
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#define COMP_CSR_COMPEN (1 << 0) /* Bit 0: Comparator enable */
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/* Bits 1-3: Reserved */
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#define COMP_CSR_INMSEL_SHIFT (4) /* Bits 4-6: Comparator inverting input selection */
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#define COMP_CSR_INMSEL_MASK (15 << COMP_CSR_INMSEL_SHIFT)
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# define COMP_CSR_INMSEL_1P4VREF (0 << COMP_CSR_INMSEL_SHIFT) /* 0000: 1/4 of Vrefint */
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# define COMP_CSR_INMSEL_1P2VREF (1 << COMP_CSR_INMSEL_SHIFT) /* 0001: 1/2 of Vrefint */
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# define COMP_CSR_INMSEL_3P4VREF (2 << COMP_CSR_INMSEL_SHIFT) /* 0010: 3/4 of Vrefint */
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# define COMP_CSR_INMSEL_VREF (3 << COMP_CSR_INMSEL_SHIFT) /* 0011: Vrefint */
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# define COMP_CSR_INMSEL_PA4 (4 << COMP_CSR_INMSEL_SHIFT) /* 0100: PA4 or DAC1_CH output if enabled */
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# define COMP_CSR_INMSEL_DAC1CH2 (5 << COMP_CSR_INMSEL_SHIFT) /* 0101: DAC1_CH2 output */
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# define COMP_CSR_INMSEL_PA2 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PA2 (COMP2 only) */
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# define COMP_CSR_INMSEL_PB2 (7 << COMP4_CSR_INMSEL_SHIFT) /* 0111: PB2 (COMP4 only) */
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# define COMP_CSR_INMSEL_PB15 (7 << COMP6_CSR_INMSEL_SHIFT) /* 0110: PB15 (COMP6 only) */
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/* 1000: DAC2_CH1 output, look at bit 22 */
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/* Bits 7-9: Reserved */
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#define COMP_CSR_OUTSEL_SHIFT (4) /* Bits 10-13: Comparator output selection */
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#define COMP_CSR_OUTSEL_MASK (15 << COMP_CSR_INMSEL_SHIFT)
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# define COMP_CSR_OUTSEL_NOSEL (0 << COMP_CSR_INMSEL_SHIFT) /* 0000: No selection */
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# define COMP_CSR_OUTSEL_BRKACTH (1 << COMP_CSR_INMSEL_SHIFT) /* 0001: Timer 1 break input */
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# define COMP_CSR_OUTSEL_BRK2 (2 << COMP_CSR_INMSEL_SHIFT) /* 0010: Timer 1 break input 2 */
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/* 0011: Reserved */
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/* 0100: Reserved */
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# define COMP_CSR_OUTSEL_BRK2_ (5 << COMP_CSR_INMSEL_SHIFT) /* 0101: Timer 1 break input2 */
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# define COMP_CSR_OUTSEL_T1OCCC (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: Timer 1 OCREF_CLR input (COMP2 only) */
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# define COMP_CSR_OUTSEL_T3CAP3 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: Timer 3 input apture 3 (COMP4 only) */
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# define COMP_CSR_OUTSEL_T2CAP2 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: Timer 2 input apture 2 (COMP6 only) */
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# define COMP_CSR_OUTSEL_T1CAP1 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: Timer 1 input capture 1 (COMP2 only) */
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# define COMP_CSR_OUTSEL_T2CAP4 (8 << COMP_CSR_INMSEL_SHIFT) /* 1000: Timer 2 input capture 4 (COMP2 only) */
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# define COMP_CSR_OUTSEL_T15CAP2 (8 << COMP_CSR_INMSEL_SHIFT) /* 1000: Timer 15 input capture 2 (COMP4 only) */
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# define COMP_CSR_OUTSEL_T2OCC (8 << COMP_CSR_INMSEL_SHIFT) /* 1000: Timer 2 OCREF CLR input (COMP6 only) */
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# define COMP_CSR_OUTSEL_T2OCC (9 << COMP_CSR_INMSEL_SHIFT) /* 1001: Timer 2 OCREF_CLR input (COMP2 only) */
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# define COMP_CSR_OUTSEL_T16OCC (9 << COMP_CSR_INMSEL_SHIFT) /* 1001: Timer 16 OCREF_CLR input (COMP6 only) */
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# define COMP_CSR_OUTSEL_T3CAP1 (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 3 input capture 1 (COMP2 only) */
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# define COMP_CSR_OUTSEL_T3CAP1 (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 15 OCREF_CLR input (COMP4 only) */
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# define COMP_CSR_OUTSEL_T3CAP1 (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 16 input capture 1 (COMP6 only) */
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# define COMP_CSR_OUTSEL_T3OCC (11 << COMP_CSR_INMSEL_SHIFT) /* 1011: Timer 3 OCREF_CLR input (COMP2,COMP4 only) */
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/* Bit 14: Reserved */
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#define COMP_CSR_POL (1 << 15) /* Bit 15: comparator output polarity */
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/* Bits 16-17: Reserved */
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#define COMP_CSR_BLANCKING_SHIFT (18) /* Bit 18-20: comparator output blanking source */
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#define COMP_CSR_BLANCKING_MASK (7 << COMP_CSR_BLANCKING_SHIFT)
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# define COMP_CSR_BLANCKING_DIS (0 << COMP_CSR_BLANCKING_SHIFT) /* 000: No blanking */
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# define COMP_CSR_BLANCKING_T1OC5 (1 << COMP_CSR_BLANCKING_SHIFT) /* 001: TIM1 OC5 as blanking source (COMP2 only) */
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# define COMP_CSR_BLANCKING_T3OC4 (1 << COMP_CSR_BLANCKING_SHIFT) /* 001: TIM3 OC4 as blanking source (COMP4 only) */
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# define COMP_CSR_BLANCKING_T2OC3 (2 << COMP_CSR_BLANCKING_SHIFT) /* 010: TIM2 OC3 as blanking source (COMP2 only) */
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# define COMP_CSR_BLANCKING_T3OC3 (3 << COMP_CSR_BLANCKING_SHIFT) /* 011: TIM3 OC3 as blanking source (COMP2 only) */
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# define COMP_CSR_BLANCKING_T15OC1 (3 << COMP_CSR_BLANCKING_SHIFT) /* 011: TIM15 OC1 as blanking source (COMP4 only) */
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# define COMP_CSR_BLANCKING_T2OC4 (3 << COMP_CSR_BLANCKING_SHIFT) /* 011: TIM2 OC4 as blanking source (COMP6 only) */
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# define COMP_CSR_BLANCKING_T15OC2 (4 << COMP_CSR_BLANCKING_SHIFT) /* 011: TIM15 OC2 as blanking source (COMP6 only) */
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/* Bit 21: Reserved */
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#define COMP_CSR_INMSEL_DAC2CH1 (1 << 22) /* Bit 22: used with bits 4-6, DAC2_CH1 output */
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/* Bits 23-29: Reserved */
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#define COMP_CSR_OUT (1 << 30) /* Bit 30: comparator output */
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#define COMP_CSR_LOCK (1 << 31) /* Bit 31: comparator lock */
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_COMP_H */
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@@ -1 +1,238 @@
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/* todo */
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32f33xxx_dac.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Modified for STM32F334 by Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DAC_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DAC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */
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#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */
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#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */
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#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */
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#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */
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#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */
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#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */
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#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */
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#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */
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#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */
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#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */
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#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */
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#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */
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/* Register Addresses ***************************************************************/
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/* DAC1 */
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# define STM32_DAC1_CR (STM32_DAC1_BASE+STM32_DAC_CR_OFFSET)
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# define STM32_DAC1_SWTRIGR (STM32_DAC1_BASE+STM32_DAC_SWTRIGR_OFFSET)
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# define STM32_DAC1_DHR12R1 (STM32_DAC1_BASE+STM32_DAC_DHR12R1_OFFSET)
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# define STM32_DAC1_DHR12L1 (STM32_DAC1_BASE+STM32_DAC_DHR12L1_OFFSET)
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# define STM32_DAC1_DHR8R1 (STM32_DAC1_BASE+STM32_DAC_DHR8R1_OFFSET)
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# define STM32_DAC1_DHR12R2 (STM32_DAC1_BASE+STM32_DAC_DHR12R2_OFFSET)
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# define STM32_DAC1_DHR12L2 (STM32_DAC1_BASE+STM32_DAC_DHR12L2_OFFSET)
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# define STM32_DAC1_DHR8R2 (STM32_DAC1_BASE+STM32_DAC_DHR8R2_OFFSET)
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# define STM32_DAC1_DHR12RD (STM32_DAC1_BASE+STM32_DAC_DHR12RD_OFFSET)
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# define STM32_DAC1_DHR12LD (STM32_DAC1_BASE+STM32_DAC_DHR12LD_OFFSET)
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# define STM32_DAC1_DHR8RD (STM32_DAC1_BASE+STM32_DAC_DHR8RD_OFFSET)
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# define STM32_DAC1_DOR1 (STM32_DAC1_BASE+STM32_DAC_DOR1_OFFSET)
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# define STM32_DAC1_DOR2 (STM32_DAC1_BASE+STM32_DAC_DOR2_OFFSET)
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# define STM32_DAC1_SR (STM32_DAC1_BASE+STM32_DAC_SR_OFFSET)
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/* DAC2 */
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# define STM32_DAC2_CR (STM32_DAC2_BASE+STM32_DAC_CR_OFFSET)
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# define STM32_DAC2_SWTRIGR (STM32_DAC2_BASE+STM32_DAC_SWTRIGR_OFFSET)
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# define STM32_DAC2_DHR12R1 (STM32_DAC2_BASE+STM32_DAC_DHR12R1_OFFSET)
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# define STM32_DAC2_DHR12L1 (STM32_DAC2_BASE+STM32_DAC_DHR12L1_OFFSET)
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# define STM32_DAC2_DHR8R1 (STM32_DAC2_BASE+STM32_DAC_DHR8R1_OFFSET)
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# define STM32_DAC2_DHR12R2 (STM32_DAC2_BASE+STM32_DAC_DHR12R2_OFFSET)
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# define STM32_DAC2_DHR12L2 (STM32_DAC2_BASE+STM32_DAC_DHR12L2_OFFSET)
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# define STM32_DAC2_DHR8R2 (STM32_DAC2_BASE+STM32_DAC_DHR8R2_OFFSET)
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# define STM32_DAC2_DHR12RD (STM32_DAC2_BASE+STM32_DAC_DHR12RD_OFFSET)
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# define STM32_DAC2_DHR12LD (STM32_DAC2_BASE+STM32_DAC_DHR12LD_OFFSET)
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# define STM32_DAC2_DHR8RD (STM32_DAC2_BASE+STM32_DAC_DHR8RD_OFFSET)
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# define STM32_DAC2_DOR1 (STM32_DAC2_BASE+STM32_DAC_DOR1_OFFSET)
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# define STM32_DAC2_DOR2 (STM32_DAC2_BASE+STM32_DAC_DOR2_OFFSET)
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# define STM32_DAC2_SR (STM32_DAC2_BASE+STM32_DAC_SR_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* DAC control register */
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/* These definitions may be used with the full, 32-bit register */
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#define DAC_CR_EN1 (1 << 0) /* Bit 0: DAC channel 1 enable */
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#define DAC_CR_BOFF1 (1 << 1) /* Bit 1: DAC channel 1 output buffer disable */
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#define DAC_CR_TEN1 (1 << 2) /* Bit 2: DAC channel 1 trigger enable */
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#define DAC_CR_TSEL1_SHIFT (3) /* Bits 3-5: DAC channel 1 trigger selection */
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#define DAC_CR_TSEL1_MASK (7 << DAC_CR_TSEL1_SHIFT)
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# define DAC_CR_TSEL1_TIM6 (0 << DAC_CR_TSEL1_SHIFT) /* Timer 6 TRGO event */
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# define DAC_CR_TSEL1_TIM3 (1 << DAC_CR_TSEL1_SHIFT) /* Timer 3 TRGO event */
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# define DAC_CR_TSEL1_TIM7 (2 << DAC_CR_TSEL1_SHIFT) /* Timer 7 TRGO event */
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# define DAC_CR_TSEL1_TIM15 (3 << DAC_CR_TSEL1_SHIFT) /* Timer 15 TRGO event, or */
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# define DAC_CR_TSEL_HRT1TRG1 (3 << DAC_CR_TSEL_SHIFT) /* HRTIM1 DACTRG1 event (DAC1 only) */
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# define DAC_CR_TSEL1_TIM2 (4 << DAC_CR_TSEL1_SHIFT) /* Timer 2 TRGO event */
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# define DAC_CR_TSEL_HRT1TRG2 (5 << DAC_CR_TSEL_SHIFT) /* HRTIM1 DACTRG2 event (DAC1), or */
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# define DAC_CR_TSEL_HRT1TRG3 (5 << DAC_CR_TSEL_SHIFT) /* HRTIM1 DACTRG3 event (DAC2) */
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# define DAC_CR_TSEL1_EXT9 (6 << DAC_CR_TSEL1_SHIFT) /* External line9 */
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# define DAC_CR_TSEL1_SW (7 << DAC_CR_TSEL1_SHIFT) /* Software trigger */
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#define DAC_CR_WAVE1_SHIFT (6) /* Bits 6-7: DAC channel 1 noise/triangle wave generation */
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#define DAC_CR_WAVE1_MASK (3 << DAC_CR_WAVE1_SHIFT)
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# define DAC_CR_WAVE1_DISABLED (0 << DAC_CR_WAVE1_SHIFT) /* Wave generation disabled */
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# define DAC_CR_WAVE1_NOISE (1 << DAC_CR_WAVE1_SHIFT) /* Noise wave generation enabled */
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# define DAC_CR_WAVE1_TRIANGLE (2 << DAC_CR_WAVE1_SHIFT) /* Triangle wave generation enabled */
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#define DAC_CR_MAMP1_SHIFT (8) /* Bits 8-11: DAC channel 1 mask/amplitude selector */
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#define DAC_CR_MAMP1_MASK (15 << DAC_CR_MAMP1_SHIFT)
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# define DAC_CR_MAMP1_AMP1 (0 << DAC_CR_MAMP1_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */
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# define DAC_CR_MAMP1_AMP3 (1 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */
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# define DAC_CR_MAMP1_AMP7 (2 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[2:0] of LFSR/triangle amplitude=7 */
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# define DAC_CR_MAMP1_AMP15 (3 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[3:0] of LFSR/triangle amplitude=15 */
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# define DAC_CR_MAMP1_AMP31 (4 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[4:0] of LFSR/triangle amplitude=31 */
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# define DAC_CR_MAMP1_AMP63 (5 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[5:0] of LFSR/triangle amplitude=63 */
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# define DAC_CR_MAMP1_AMP127 (6 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[6:0] of LFSR/triangle amplitude=127 */
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# define DAC_CR_MAMP1_AMP255 (7 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[7:0] of LFSR/triangle amplitude=255 */
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# define DAC_CR_MAMP1_AMP511 (8 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[8:0] of LFSR/triangle amplitude=511 */
|
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# define DAC_CR_MAMP1_AMP1023 (9 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */
|
||||
# define DAC_CR_MAMP1_AMP2047 (10 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */
|
||||
# define DAC_CR_MAMP1_AMP4095 (11 << DAC_CR_MAMP1_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */
|
||||
#define DAC_CR_DMAEN1 (1 << 12) /* Bit 12: DAC channel 1 DMA enable */
|
||||
#define DAC_CR_DMAUDRIE1 (1 << 13) /* Bit 13: DAC channel 1 DMA Underrun Interrupt enable */
|
||||
|
||||
#define DAC_CR_EN2 (1 << 16) /* Bit 16: DAC channel 2 enable */
|
||||
#define DAC_CR_BOFF2 (1 << 17) /* Bit 17: DAC channel 2 output buffer disable */
|
||||
#define DAC_CR_TEN2 (1 << 18) /* Bit 18: DAC channel 2 trigger enable */
|
||||
#define DAC_CR_TSEL2_SHIFT (19) /* Bits 19-21: DAC channel 2 trigger selection */
|
||||
#define DAC_CR_TSEL2_MASK (7 << DAC_CR_TSEL2_SHIFT)
|
||||
# define DAC_CR_TSEL2_TIM6 (0 << DAC_CR_TSEL2_SHIFT) /* Timer 6 TRGO event */
|
||||
# define DAC_CR_TSEL2_TIM8 (1 << DAC_CR_TSEL2_SHIFT) /* Timer 8 TRGO event */
|
||||
# define DAC_CR_TSEL2_TIM7 (2 << DAC_CR_TSEL2_SHIFT) /* Timer 7 TRGO event */
|
||||
# define DAC_CR_TSEL2_TIM5 (3 << DAC_CR_TSEL2_SHIFT) /* Timer 5 TRGO event */
|
||||
# define DAC_CR_TSEL2_TIM2 (4 << DAC_CR_TSEL2_SHIFT) /* Timer 2 TRGO event */
|
||||
# define DAC_CR_TSEL2_TIM4 (5 << DAC_CR_TSEL2_SHIFT) /* Timer 4 TRGO event */
|
||||
# define DAC_CR_TSEL2_EXT9 (6 << DAC_CR_TSEL2_SHIFT) /* External line9 */
|
||||
# define DAC_CR_TSEL2_SW (7 << DAC_CR_TSEL2_SHIFT) /* Software trigger */
|
||||
#define DAC_CR_WAVE2_SHIFT (22) /* Bit 22-23: DAC channel 2 noise/triangle wave generation enable */
|
||||
#define DAC_CR_WAVE2_MASK (3 << DAC_CR_WAVE2_SHIFT)
|
||||
# define DAC_CR_WAVE2_DISABLED (0 << DAC_CR_WAVE2_SHIFT) /* Wave generation disabled */
|
||||
# define DAC_CR_WAVE2_NOISE (1 << DAC_CR_WAVE2_SHIFT) /* Noise wave generation enabled */
|
||||
# define DAC_CR_WAVE2_TRIANGLE (2 << DAC_CR_WAVE2_SHIFT) /* Triangle wave generation enabled */
|
||||
#define DAC_CR_MAMP2_SHIFT (24) /* Bit 24-27: DAC channel 2 mask/amplitude selector */
|
||||
#define DAC_CR_MAMP2_MASK (15 << DAC_CR_MAMP2_SHIFT)
|
||||
# define DAC_CR_MAMP2_AMP1 (0 << DAC_CR_MAMP2_SHIFT) /* Unmask bit0 of LFSR/triangle amplitude=1 */
|
||||
# define DAC_CR_MAMP2_AMP3 (1 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[1:0] of LFSR/triangle amplitude=3 */
|
||||
# define DAC_CR_MAMP2_AMP7 (2 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[2:0] of LFSR/triangle amplitude=7 */
|
||||
# define DAC_CR_MAMP2_AMP15 (3 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[3:0] of LFSR/triangle amplitude=15 */
|
||||
# define DAC_CR_MAMP2_AMP31 (4 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[4:0] of LFSR/triangle amplitude=31 */
|
||||
# define DAC_CR_MAMP2_AMP63 (5 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[5:0] of LFSR/triangle amplitude=63 */
|
||||
# define DAC_CR_MAMP2_AMP127 (6 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[6:0] of LFSR/triangle amplitude=127 */
|
||||
# define DAC_CR_MAMP2_AMP255 (7 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[7:0] of LFSR/triangle amplitude=255 */
|
||||
# define DAC_CR_MAMP2_AMP511 (8 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[8:0] of LFSR/triangle amplitude=511 */
|
||||
# define DAC_CR_MAMP2_AMP1023 (9 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[9:0] of LFSR/triangle amplitude=1023 */
|
||||
# define DAC_CR_MAMP2_AMP2047 (10 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[10:0] of LFSR/triangle amplitude=2047 */
|
||||
# define DAC_CR_MAMP2_AMP4095 (11 << DAC_CR_MAMP2_SHIFT) /* Unmask bits[11:0] of LFSR/triangle amplitude=4095 */
|
||||
#define DAC_CR_DMAEN2 (1 << 28) /* Bit 28: DAC channel 2 DMA enable */
|
||||
#define DAC_CR_DMAUDRIE2 (1 << 29) /* Bits 29: DAC channel 2 DMA underrun interrupt enable */
|
||||
|
||||
/* DAC software trigger register */
|
||||
|
||||
#define DAC_SWTRIGR_SWTRIG(n) (1 << ((n)-1))
|
||||
#define DAC_SWTRIGR_SWTRIG1 (1 << 0) /* Bit 0: DAC channel 1 software trigger */
|
||||
#define DAC_SWTRIGR_SWTRIG2 (1 << 1) /* Bit 1: DAC channel 2 software trigger */
|
||||
|
||||
/* DAC channel 1/2 12-bit right-aligned data holding register */
|
||||
|
||||
#define DAC_DHR12R_MASK (0x0fff)
|
||||
|
||||
/* DAC channel 1/2 12-bit left aligned data holding register */
|
||||
|
||||
#define DAC_DHR12L_MASK (0xfff0)
|
||||
|
||||
/* DAC channel 1/2 8-bit right aligned data holding register */
|
||||
|
||||
#define DAC_DHR8R_MASK (0x00ff)
|
||||
|
||||
/* Dual DAC 12-bit right-aligned data holding register */
|
||||
|
||||
#define DAC_DHR12RD_DACC_SHIFT(n) (1 << (((n)-1) << 4))
|
||||
#define DAC_DHR12RD_DACC_MASK(n) (0xfff << DAC_DHR12RD_DACC_SHIFT(n))
|
||||
|
||||
#define DAC_DHR12RD_DACC1_SHIFT (0) /* Bits 0-11: DAC channel 1 12-bit right-aligned data */
|
||||
#define DAC_DHR12RD_DACC1_MASK (0xfff << DAC_DHR12RD_DACC2_SHIFT)
|
||||
#define DAC_DHR12RD_DACC2_SHIFT (16) /* Bits 16-27: DAC channel 2 12-bit right-aligned data */
|
||||
#define DAC_DHR12RD_DACC2_MASK (0xfff << DAC_DHR12RD_DACC2_SHIFT)
|
||||
|
||||
/* Dual DAC 12-bit left-aligned data holding register */
|
||||
|
||||
#define DAC_DHR12LD_DACC_SHIFT(n) ((1 << (((n)-1) << 4)) + 4)
|
||||
#define DAC_DHR12LD_DACC_MASK(n) (0xfff << DAC_DHR12LD_DACC_SHIFT(n))
|
||||
|
||||
#define DAC_DHR12LD_DACC1_SHIFT (4) /* Bits 4-15: DAC channel 1 12-bit left-aligned data */
|
||||
#define DAC_DHR12LD_DACC1_MASK (0xfff << DAC_DHR12LD_DACC1_SHIFT)
|
||||
#define DAC_DHR12LD_DACC2_SHIFT (20) /* Bits 20-31: DAC channel 2 12-bit left-aligned data */
|
||||
#define DAC_DHR12LD_DACC2_MASK (0xfff << DAC_DHR12LD_DACC2_SHIFT)
|
||||
|
||||
/* DUAL DAC 8-bit right aligned data holding register */
|
||||
|
||||
#define DAC_DHR8RD_DACC_SHIFT(n) (1 << (((n)-1) << 3))
|
||||
#define DAC_DHR8RD_DACC_MASK(n) (0xff << DAC_DHR8RD_DACC_SHIFT(n))
|
||||
|
||||
#define DAC_DHR8RD_DACC1_SHIFT (0) /* Bits 0-7: DAC channel 1 8-bit right-aligned data */
|
||||
#define DAC_DHR8RD_DACC1_MASK (0xff << DAC_DHR8RD_DACC1_SHIFT)
|
||||
#define DAC_DHR8RD_DACC2_SHIFT (8) /* Bits 8-15: DAC channel 2 8-bit right-aligned data */
|
||||
#define DAC_DHR8RD_DACC2_MASK (0xff << DAC_DHR8RD_DACC2_SHIFT)
|
||||
|
||||
/* DAC channel 1/2 data output register */
|
||||
|
||||
#define DAC_DOR_MASK (0x0fff)
|
||||
|
||||
/* DAC status register */
|
||||
|
||||
#define DAC_SR_DMAUDR(n) ((1 << (((n)-1) << 4)) + 13)
|
||||
#define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */
|
||||
#define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DAC_H */
|
||||
|
||||
@@ -107,7 +107,9 @@
|
||||
|
||||
/* APB2 Base Addresses **************************************************************/
|
||||
|
||||
#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103FF SYSCFG + COMP + OPAMP */
|
||||
#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103FF SYSCFG, and */
|
||||
#define STM32_COMP_BASE 0x40010000 /* COMP, and */
|
||||
#define STM32_OPAMP_BASE 0x40010000 /* OPAMP */
|
||||
#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107FF EXTI */
|
||||
#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */
|
||||
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
|
||||
@@ -115,7 +117,7 @@
|
||||
#define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */
|
||||
#define STM32_TIM16_BASE 0x40014400 /* 0x40014400-0x400147ff TIM16 */
|
||||
#define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */
|
||||
#define STM32_HRTIM1_BASE 0x40017400 /* 0x40017400-0x400177ff TIM19 */
|
||||
#define STM32_HRTIM1_BASE 0x40017400 /* 0x40017400-0x400177ff HRTIM1 */
|
||||
|
||||
/* AHB1 Base Addresses **************************************************************/
|
||||
|
||||
|
||||
@@ -0,0 +1,117 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/chip/stm32f33xxx_opamp.h
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_OPAMP_H
|
||||
#define __ARCH_ARM_SRC_STM32_CHIP_STM32_OPAMP_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
#define STM32_OPAMP2_CSR_OFFSET 0x003C /* OPAMP2 Control register */
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define STM32_OPAMP2_CSR (STM32_OPAMP2_BASE+STM32_OPAMP2_CSR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
/* OPAMP control and status register */
|
||||
|
||||
#define OPAMP_CSR_OPAMPEN (1 << 0) /* Bit 0: OPAMP enable */
|
||||
#define OPAMP_CSR_FORCE_VP (1 << 1) /* Bit 1: Force a calibration reference voltage on non-nverting */
|
||||
/* input and disables external connections */
|
||||
#define OPAMP_CSR_VPSEL_SHIFT (3) /* Bits 2-3: OPAMP non inverting input selection */
|
||||
#define OPAMP_CSR_VPSEL_MASK (3 << OPAMP_CSR_VPSEL_SHIFT)
|
||||
/* 00: Reserved */
|
||||
# define OPAMP_CSR_VPSEL_PB13 (1 << OPAMP_CSR_VPSEL_SHIFT) /* 01: PB14 */
|
||||
# define OPAMP_CSR_VPSEL_PB0 (2 << OPAMP_CSR_VPSEL_SHIFT) /* 10: PB0 */
|
||||
# define OPAMP_CSR_VPSEL_PA7 (3 << OPAMP_CSR_VPSEL_SHIFT) /* 11: PA7 */
|
||||
/* Bit 4: Reserved */
|
||||
#define OPAMP_CSR_VMSEL_SHIFT (5) /* Bits 5-6: OPAMP inverting input selection */
|
||||
#define OPAMP_CSR_VMSEL_MASK (3 << OPAMP_CSR_VMSEL_SHIFT)
|
||||
# define OPAMP_CSR_VMSEL_PC5 (0 << OPAMP_CSR_VMSEL_SHIFT) /* 00: PC5 */
|
||||
# define OPAMP_CSR_VMSEL_PA5 (1 << OPAMP_CSR_VMSEL_SHIFT) /* 01: PA5 */
|
||||
# define OPAMP_CSR_VMSEL_RESISTOR (2 << OPAMP_CSR_VMSEL_SHIFT) /* 10: Resistor feedback output */
|
||||
# define OPAMP_CSR_VMSEL_FOLLOWER (3 << OPAMP_CSR_VMSEL_SHIFT) /* 11: Follower mode */
|
||||
#define OPAMP_CSR_TCMEN (1 << 7) /* Bit 7: Timer controlled Mux mode enable */
|
||||
#define OPAMP_CSR_VMSSEL (1 << 8) /* Bit 8: OPAMP inverting input secondary selection */
|
||||
#define OPAMP_CSR_VPSSEL_SHIFT (1 << 9) /* Bits 9-10: OPAMP Non inverting input secondary selection */
|
||||
#define OPAMP_CSR_VPSSEL_MASK (3 << OPAMP_CSR_VPSSEL_SHIFT)
|
||||
/* 00: Reserved */
|
||||
# define OPAMP_CSR_VPSSEL_PB14 (1 << OPAMP_CSR_VPSSEL_SHIFT) /* 01: PB14 */
|
||||
# define OPAMP_CSR_VPSSEL_PB0 (2 << OPAMP_CSR_VPSSEL_SHIFT) /* 10: PB0 */
|
||||
# define OPAMP_CSR_VPSSEL_PA7 (3 << OPAMP_CSR_VPSSEL_SHIFT) /* 11: PA7 */
|
||||
#define OPAMP_CSR_CALON (1 << 11) /* Bit 11: Calibration mode enable */
|
||||
#define OPAMP_CSR_CALSEL_SHIFT (12) /* Bits 12-13: Calibration selection */
|
||||
#define OPAMP_CSR_CALSEL_MASK (3 << OPAMP_CSR_CALSEL_SHIFT)
|
||||
# define OPAMP_CSR_CALSEL_3P3 (0 << OPAMP_CSR_CALSEL_SHIFT) /* 00 V_REFOPAMP = 3.3% V_DDA */
|
||||
# define OPAMP_CSR_CALSEL_10 (1 << OPAMP_CSR_CALSEL_SHIFT) /* 01 V_REFOPAMP = 10% V_DDA */
|
||||
# define OPAMP_CSR_CALSEL_50 (2 << OPAMP_CSR_CALSEL_SHIFT) /* 10 V_REFOPAMP = 50% V_DDA */
|
||||
# define OPAMP_CSR_CALSEL_90 (3 << OPAMP_CSR_CALSEL_SHIFT) /* 11 V_REFOPAMP = 90% V_DDA */
|
||||
#define OPAMP_CSR_PGAGAIN_SHIFT (14) /* Bits 14-17: Gain in PGA mode */
|
||||
#define OPAMP_CSR_PGAGAIN_MASK (15 << OPAMP_CSR_PGAGAIN_SHIFT)
|
||||
# define OPAMP_CSR_PGAGAIN_2 (0 << OPAMP_CSR_PGAGAIN_SHIFT) /* 0X00: Non-inverting gain = 2 */
|
||||
# define OPAMP_CSR_PGAGAIN_4 (1 << OPAMP_CSR_PGAGAIN_SHIFT) /* 0X01: Non-inverting gain = 4 */
|
||||
# define OPAMP_CSR_PGAGAIN_8 (2 << OPAMP_CSR_PGAGAIN_SHIFT) /* 0X1-: Non-inverting gain = 8 */
|
||||
# define OPAMP_CSR_PGAGAIN_16 (3 << OPAMP_CSR_PGAGAIN_SHIFT) /* 0X11: Non-inverting gain = 16 */
|
||||
# define OPAMP_CSR_PGAGAIN_2VM0 (8 << OPAMP_CSR_PGAGAIN_SHIFT) /* 1000: Non-inverting gain = 2 - VM0*/
|
||||
# define OPAMP_CSR_PGAGAIN_4VM0 (9 << OPAMP_CSR_PGAGAIN_SHIFT) /* 1001: Non-inverting gain = 4 - VM0*/
|
||||
# define OPAMP_CSR_PGAGAIN_8VM0 (10 << OPAMP_CSR_PGAGAIN_SHIFT) /* 1010: Non-inverting gain = 8 - VM0*/
|
||||
# define OPAMP_CSR_PGAGAIN_16VM0 (11 << OPAMP_CSR_PGAGAIN_SHIFT) /* 1011: Non-inverting gain = 16 - VM0*/
|
||||
# define OPAMP_CSR_PGAGAIN_2VM1 (12 << OPAMP_CSR_PGAGAIN_SHIFT) /* 1100: Non-inverting gain = 2 - VM1*/
|
||||
# define OPAMP_CSR_PGAGAIN_4VM1 (13 << OPAMP_CSR_PGAGAIN_SHIFT) /* 1101: Non-inverting gain = 4 - VM1*/
|
||||
# define OPAMP_CSR_PGAGAIN_8VM1 (14 << OPAMP_CSR_PGAGAIN_SHIFT) /* 1110: Non-inverting gain = 8 - VM1*/
|
||||
# define OPAMP_CSR_PGAGAIN_16VM1 (15 << OPAMP_CSR_PGAGAIN_SHIFT) /* 1111: Non-inverting gain = 16 - VM1*/
|
||||
#define OPAMP_CSR_USERTRIM (1 << 18) /* Bit 18: User trimming enable */
|
||||
#define OPAMP_CSR_TRIMOFFSETP_SHIFT (19) /* Bits 19-23: Offset trimming value (PMOS)*/
|
||||
#define OPAMP_CSR_TRIMOFFSETP_MASK (31 << OPAMP_CSR_TRIMOFFSETP_SHIFT)
|
||||
#define OPAMP_CSR_TRIMOFFSETN_SHIFT (24) /* Bits 24-28: Offset trimming value (NMOS) */
|
||||
#define OPAMP_CSR_TRIMOFFSETN_MASK (31 << OPAMP_CSR_TRIMOFFSETN_SHIFT)
|
||||
#define OPAMP_CSR_TSTREF (1 << 29) /* Bit 29: Output the internal reference voltage */
|
||||
#define OPAMP_CSR_OUTCAL (1 << 30) /* Bit 30: OPAMP output status flag */
|
||||
#define OPAMP_CSR_LOCK (1 << 31) /* Bit 31: OPAMP 2 lock */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_OPAMP_H */
|
||||
|
||||
@@ -48,6 +48,8 @@
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
# include "chip/stm32f30xxx_adc.h"
|
||||
#elif defined(CONFIG_STM32_STM32F33XX)
|
||||
# include "chip/stm32f33xxx_adc.h"
|
||||
#elif defined(CONFIG_STM32_STM32F37XX)
|
||||
# include "chip/stm32f37xxx_adc.h"
|
||||
#else
|
||||
|
||||
@@ -43,7 +43,11 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#ifdef CONFIG_STM32_STM32F33XX
|
||||
#include "chip/stm32f33xxx_dac.h"
|
||||
#else
|
||||
#include "chip/stm32_dac.h"
|
||||
#endif
|
||||
|
||||
#include <nuttx/analog/dac.h>
|
||||
|
||||
|
||||
Reference in New Issue
Block a user