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Merged in raiden00/nuttx (pull request #529)

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* cosmetics

* stm32_hrtim: add helper macros

* smps: cosmetics

* stm32f33xxx_adc: injected channels support, fix some definitions, add interface to disable interrupts

* stm32f334-dsico: beginning of lower-half driver for SMPS (buck-boost onboard converter)

* nucleo-f334r8/highpri: missing ADC trigger configuration

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Mateusz Szafoni
2017-11-05 14:15:04 +00:00
committed by Gregory Nutt
parent 4d6c17246f
commit 2fc5237854
16 changed files with 1211 additions and 357 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/stm32/chip/stm32f33xxx_adc.h
+4 -4
View File
@@ -84,7 +84,7 @@
#define STM32_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */
#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */
#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */
#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */
#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register */
#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */
/* Master and Slave ADC Common Registers */
@@ -384,7 +384,7 @@
/* ADC injected sequence register */
#define ADC_JSQR_JL_SHIFT (0) /* Bits 0-1: Injected Sequence length */
#define ADC_JSQR_JL_MASK (3 << ADC_JSQR_JL_SHIFT)
#define ADC_JSQR_JL_MASK (2 << ADC_JSQR_JL_SHIFT)
# define ADC_JSQR_JL(n) (((n)-1) << ADC_JSQR_JL_SHIFT) /* n=1..4 */
#define ADC_JSQR_JEXTSEL_SHIFT (2) /* Bits 2-5: External Trigger Selection for injected group */
#define ADC_JSQR_JEXTSEL_MASK (15 << ADC_JSQR_JEXTSEL_SHIFT)
@@ -414,8 +414,8 @@
#define ADC_JSQR_JSQ1_MASK (0x1f << ADC_JSQR_JSQ1_SHIFT)
# define ADC_JSQR_JSQ1(ch) ((ch) << ADC_JSQR_JSQ1_SHIFT) /* Channel number 1..18 */
#define ADC_JSQR_JSQ2_SHIFT (14) /* Bits 14-18: 2nd conversion in injected sequence */
#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_MASK)
# define ADC_JSQR_JSQ2(ch) ((ch) << ADC_JSQR_JSQ2_MASK) /* Channel number 1..18 */
#define ADC_JSQR_JSQ2_MASK (0x1f << ADC_JSQR_JSQ2_SHIFT)
# define ADC_JSQR_JSQ2(ch) ((ch) << ADC_JSQR_JSQ2_SHIFT) /* Channel number 1..18 */
#define ADC_JSQR_JSQ3_SHIFT (20) /* Bits 20-24: 3rd conversion in injected sequence */
#define ADC_JSQR_JSQ3_MASK (0x1f << ADC_JSQR_JSQ3_SHIFT)
# define ADC_JSQR_JSQ3(ch) ((ch) << ADC_JSQR_JSQ3_SHIFT) /* Channel number 1..18 */
arch/arm/src/stm32/gnu/stm32_vectors.S
+1 -1
View File
@@ -106,7 +106,7 @@
.thumb
.file "stm32_vectors.S"
/* Check if common ARMv7 interrupt vectoring is used (see arch/arm/src/armv7-m/up_vectors.S) */
/* Check if common ARMv7 interrupt vectoring is used (see arch/arm/src/armv7-m/up_vectors.c) */
#ifndef CONFIG_ARMV7M_CMNVECTOR
arch/arm/src/stm32/stm32_adc.h
+248 -244
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/stm32/stm32_hrtim.c
-4
View File
@@ -181,10 +181,6 @@
# endif
#endif
#ifdef CONFIG_STM32_HRTIM_ADC
# error HRTIM ADC Triggering not supported yet
#endif
#if defined(CONFIG_STM32_HRTIM_ADC1_TRG1) || defined(CONFIG_STM32_HRTIM_ADC1_TRG2) || \
defined(CONFIG_STM32_HRTIM_ADC1_TRG3) || defined(CONFIG_STM32_HRTIM_ADC1_TRG4) || \
defined(CONFIG_STM32_HRTIM_ADC2_TRG1) || defined(CONFIG_STM32_HRTIM_ADC2_TRG2) || \
arch/arm/src/stm32/stm32_hrtim.h
+19
View File
@@ -202,6 +202,25 @@
# endif
#endif
/* Helpers **************************************************************************/
#define HRTIM_CMP_SET(hrtim, tim, index, cmp) \
(hrtim)->hd_ops->cmp_update(hrtim, tim, index, cmp)
#define HRTIM_PER_SET(hrtim, tim, per) \
(hrtim)->hd_ops->per_update(hrtim, tim, per)
#define HRTIM_OUTPUTS_ENABLE(hrtim, tim, state) \
(hrtim)->hd_ops->outputs_enable(hrtim, tim, state)
#define HRTIM_OUTPUTS_ENABLE(hrtim, tim, state) \
(hrtim)->hd_ops->outputs_enable(hrtim, tim, state)
#define HRTIM_BURST_CMP_SET(hrtim, cmp) \
(hrtim)->hd_ops->burst_cmp_set(hrtim, cmp)
#define HRTIM_BURST_PER_SET(hrtim, per) \
(hrtim)->hd_ops->burst_per_set(hrtim, per)
#define HRTIM_BURST_PRE_SET(hrtim, pre) \
(hrtim)->hd_ops->burst_pre_set(hrtim, pre)
#define HRTIM_BURST_ENABLE(hrtim, state) \
(hrtim)->hd_ops->burst_enable(hrtim, state)
/************************************************************************************
* Public Types
************************************************************************************/
arch/arm/src/stm32/stm32f33xxx_adc.c
+168 -58
View File
@@ -93,18 +93,26 @@
#warning "ADC support for STM32F33XX under development !"
/* HRTIM triggering needs DMA support */
#if defined(ADC_HAVE_HRTIM) && !defined(ADC_HAVE_DMA)
# error "ADC HRTIM Triggering support only with DMA"
#if defined(ADC1_INJECTED_CHAN) && !defined(CONFIG_STM32_ADC1_INJECTED)
# warning
#endif
#if defined(ADC2_INJECTED_CHAN) && !defined(CONFIG_STM32_ADC2_INJECTED)
# warning
#endif
#if defined(CONFIG_STM32_ADC1_INJECTED) || defined(CONFIG_STM32_ADC2_INJECTED)
# define ADC_HAVE_INJECTED 1
#endif
#ifdef ADC_HAVE_INJECTED
# error "ADC injected trigger not implemented yet"
#ifndef CONFIG_STM32_ADC1_INJECTED
# define ADC1_INJECTED_CHAN 0
#else
# define ADC1_HAVE_JEXTSEL
#endif
#ifndef CONFIG_STM32_ADC2_INJECTED
# define ADC2_INJECTED_CHAN 0
#else
# define ADC2_HAVE_JEXTSEL
#endif
/****************************************************************************
@@ -135,13 +143,15 @@
#define ADC_IER_AWD ADC_INT_AWD1
#define ADC_ISR_JEOC ADC_INT_JEOC
#define ADC_IER_JEOC ADC_INT_JEOC
#define ADC_ISR_JEOS ADC_INT_JEOS
#define ADC_IER_JEOS ADC_INT_JEOS
#define ADC_ISR_OVR ADC_INT_OVR
#define ADC_IER_OVR ADC_INT_OVR
#define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_AWD | ADC_ISR_JEOC | \
ADC_ISR_OVR)
ADC_ISR_JEOS | ADC_ISR_OVR)
#define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_AWD | ADC_IER_JEOC | \
ADC_IER_OVR)
ADC_IER_JEOS| ADC_IER_OVR)
/* ADC Channels/DMA ********************************************************/
/* The maximum number of channels that can be sampled. If DMA support is
@@ -375,7 +385,7 @@ struct stm32_dev_s
FAR const struct adc_callback_s *cb;
uint8_t irq; /* Interrupt generated by this ADC block */
#endif
uint8_t nchannels; /* Number of channels */
uint8_t rnchannels; /* Number of regular channels */
uint8_t cr_channels; /* Number of configured regular channels */
uint8_t cj_channels; /* Number of configured injected channels */
uint8_t intf; /* ADC interface number */
@@ -487,11 +497,13 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr,
static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable);
#ifdef ADC_HAVE_INJECTED
static void adc_inj_startconv(FAR struct stm32_dev_s *priv, bool enable);
static int adc_inj_set_ch(FAR struct adc_dev_s *dev, uint8_t ch);
#endif
#ifdef CONFIG_STM32_ADC_NOIRQ
static void adc_intack(FAR struct stm32_adc_dev_s *dev, uint32_t source);
static void adc_inten(FAR struct stm32_adc_dev_s *dev, uint32_t source);
static void adc_intdis(FAR struct stm32_adc_dev_s *dev, uint32_t source);
static uint32_t adc_intget(FAR struct stm32_adc_dev_s *dev);
static uint32_t adc_regget(FAR struct stm32_adc_dev_s *dev);
# ifdef ADC_HAVE_DMA
@@ -526,6 +538,7 @@ static const struct stm32_adc_ops_s g_adc_lowerops =
.int_ack = adc_intack,
.int_get = adc_intget,
.int_en = adc_inten,
.int_dis = adc_intdis,
.val_get = adc_regget,
#ifdef ADC_HAVE_DMA
.regbuf_reg = adc_regbufregister,
@@ -1367,10 +1380,16 @@ static void adc_enable(FAR struct stm32_dev_s *priv, bool enable)
}
else if ((regval & ADC_CR_ADEN) != 0 && (regval & ADC_CR_ADDIS) == 0)
{
/* Stop ongoing conversions */
/* Stop ongoing regular conversions */
adc_startconv(priv, false);
#ifdef ADC_HAVE_INJECTED
/* Stop ongoing injected conversion */
adc_inj_startconv(priv, false);
#endif
/* Disable the ADC */
adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADDIS);
@@ -1387,6 +1406,7 @@ static void adc_enable(FAR struct stm32_dev_s *priv, bool enable)
* Description:
* Callback for DMA. Called from the DMA transfer complete interrupt after
* all channels have been converted and transferred with DMA.
* Only for regular conversion.
*
* Input Parameters:
*
@@ -1411,12 +1431,12 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
{
DEBUGASSERT(priv->cb->au_receive != NULL);
for (i = 0; i < priv->nchannels; i++)
for (i = 0; i < priv->rnchannels; i++)
{
priv->cb->au_receive(dev, priv->r_chanlist[priv->current],
priv->r_dmabuffer[priv->current]);
priv->current++;
if (priv->current >= priv->nchannels)
if (priv->current >= priv->rnchannels)
{
/* Restart the conversion sequence from the beginning */
@@ -1579,9 +1599,12 @@ static void adc_reset(FAR struct adc_dev_s *dev)
adc_modifyreg(priv, STM32_ADC_IER_OFFSET, clrbits, setbits);
#endif
/* Configuration of the channel conversions */
/* Configuration of the regular channel conversions */
adc_set_ch(dev, 0);
if (priv->cr_channels > 0)
{
adc_set_ch(dev, 0);
}
/* ADC CCR configuration */
@@ -1618,7 +1641,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
stm32_dmasetup(priv->dma,
priv->base + STM32_ADC_DR_OFFSET,
(uint32_t)priv->r_dmabuffer,
priv->nchannels,
priv->rnchannels,
ADC_DMA_CONTROL_WORD);
stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false);
@@ -1631,8 +1654,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
adc_enable(priv, true);
/* EXTSEL and JEXTSEL selection: These bits select the external event used
/* EXTSEL selection: These bits select the external event used
* to trigger the start of conversion of a regular group. NOTE:
*
* - The position with of the EXTSEL field varies from one STM32 MCU
@@ -1653,14 +1675,12 @@ static void adc_reset(FAR struct adc_dev_s *dev)
}
#endif
#ifdef ADC_HAVE_JEXTSEL
if (priv->jextsel & HAVE_EXTSEL_MASK)
{
ainfo("Initializing jextsel = 0x%08x\n", (priv->jextsel & ~HAVE_EXTSEL_MASK));
#ifdef ADC_HAVE_INJECTED
/* Configuration of the injected channel conversions after adc enabled */
adc_modifyreg(priv, STM32_ADC_JEXTREG_OFFSET,
ADC_JEXTREG_JEXTEN_MASK | ADC_JEXTREG_JEXTSEL_MASK,
ADC_JEXTREG_JEXTEN_DEFAULT | (priv->jextsel & ~HAVE_EXTSEL_MASK));
if (priv->cj_channels > 0)
{
adc_inj_set_ch(dev, 0);
}
#endif
@@ -1680,6 +1700,10 @@ static void adc_reset(FAR struct adc_dev_s *dev)
#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV
{
adc_startconv(priv, true);
#ifdef ADC_HAVE_INJECTED
adc_inj_startconv(priv, true);
#endif
}
#endif
@@ -1701,6 +1725,15 @@ static void adc_reset(FAR struct adc_dev_s *dev)
{
ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC12_CCR));
}
ainfo("SMPR1: 0x%08x SMPR2: 0x%08x\n",
adc_getreg(priv, STM32_ADC_SMPR1_OFFSET),
adc_getreg(priv, STM32_ADC_SMPR2_OFFSET));
ainfo("JSQR: 0x%08x DIFSEL: 0x%08x IER: 0x%08x\n",
adc_getreg(priv, STM32_ADC_JSQR_OFFSET),
adc_getreg(priv, STM32_ADC_DIFSEL_OFFSET),
adc_getreg(priv, STM32_ADC_IER_OFFSET));
}
/****************************************************************************
@@ -1835,7 +1868,7 @@ static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, int last,
int i;
for (i = first - 1;
i < priv->nchannels && i < last;
i < priv->rnchannels && i < last;
i++, offset += ADC_SQ_OFFSET)
{
bits |= (uint32_t)priv->r_chanlist[i] << offset;
@@ -1868,7 +1901,7 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch)
if (ch == 0)
{
priv->current = 0;
priv->nchannels = priv->cr_channels;
priv->rnchannels = priv->cr_channels;
}
else
{
@@ -1880,7 +1913,7 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch)
}
priv->current = i;
priv->nchannels = 1;
priv->rnchannels = 1;
}
bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET);
@@ -1892,13 +1925,46 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch)
bits = adc_sqrbits(priv, ADC_SQR2_FIRST, ADC_SQR2_LAST, ADC_SQR2_SQ_OFFSET);
adc_modifyreg(priv, STM32_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits);
bits = ((uint32_t)priv->nchannels - 1) << ADC_SQR1_L_SHIFT |
bits = ((uint32_t)priv->rnchannels - 1) << ADC_SQR1_L_SHIFT |
adc_sqrbits(priv, ADC_SQR1_FIRST, ADC_SQR1_LAST, ADC_SQR1_SQ_OFFSET);
adc_modifyreg(priv, STM32_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits);
return OK;
}
#ifdef ADC_HAVE_INJECTED
static int adc_inj_set_ch(FAR struct adc_dev_s *dev, uint8_t ch)
{
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
uint32_t regval;
int i;
/* Configure JEXTSEL */
if (priv->jextsel & HAVE_EXTSEL_MASK)
{
ainfo("Initializing jextsel = 0x%08x\n", (priv->jextsel & ~HAVE_EXTSEL_MASK));
regval = ADC_JEXTREG_JEXTEN_DEFAULT | (priv->jextsel & ~HAVE_EXTSEL_MASK);
}
/* Configure injected sequence length */
regval |= ADC_JSQR_JL(priv->cj_channels);
/* Configure injected channels */
for (i = 0 ; i < priv->cj_channels; i += 1)
{
regval |= priv->j_chanlist[i] << (ADC_JSQR_JSQ1_SHIFT + 6 * i);
}
adc_putreg(priv, STM32_ADC_JSQR_OFFSET, regval);
return OK;
}
#endif
/****************************************************************************
* Name: adc_ioctl
*
@@ -1922,13 +1988,31 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
switch (cmd)
{
case ANIOC_TRIGGER:
adc_startconv(priv, true);
break;
{
/* Start regular conversion if regular channels configured */
if (priv->cr_channels > 0)
{
adc_startconv(priv, true);
}
#ifdef ADC_HAVE_INJECTED
/* Start injected conversion if injected channels configured */
if (priv->cj_channels > 0)
{
adc_inj_startconv(priv, true);
}
#endif
break;
}
default:
aerr("ERROR: Unknown cmd: %d\n", cmd);
ret = -ENOTTY;
break;
{
aerr("ERROR: Unknown cmd: %d\n", cmd);
ret = -ENOTTY;
break;
}
}
return ret;
@@ -2005,7 +2089,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
priv->current++;
if (priv->current >= priv->nchannels)
if (priv->current >= priv->rnchannels)
{
/* Restart the conversion sequence from the beginning */
@@ -2076,6 +2160,19 @@ static void adc_inten(FAR struct stm32_adc_dev_s *dev, uint32_t source)
adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, source);
}
/****************************************************************************
* Name: adc_intdis
****************************************************************************/
static void adc_intdis(FAR struct stm32_adc_dev_s *dev, uint32_t source)
{
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
/* Disable interrupts */
adc_modifyreg(priv, STM32_ADC_IER_OFFSET, source, 0);
}
/****************************************************************************
* Name: adc_ackget
****************************************************************************/
@@ -2134,13 +2231,17 @@ static int adc_regbufregister(FAR struct stm32_adc_dev_s *dev, uint16_t *buffer,
static uint32_t adc_injget(FAR struct stm32_adc_dev_s *dev, uint8_t chan)
{
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
uint32_t regval = 0;
if (chan > priv->cj_channels)
if (chan > priv->cj_channels-1)
{
return 0;
goto errout;
}
return adc_getreg(priv, STM32_ADC_JDR1_OFFSET+4*(chan-1)) & ADC_JDR_JDATA_MASK;
regval = adc_getreg(priv, STM32_ADC_JDR1_OFFSET+4*(chan)) & ADC_JDR_JDATA_MASK;
errout:
return regval;
}
#endif
#endif
@@ -2155,7 +2256,7 @@ static uint32_t adc_injget(FAR struct stm32_adc_dev_s *dev, uint8_t chan)
* Description:
* Initialize the ADC.
*
* The logic is, save nchannels : # of channels (conversions) in ADC_SQR1_L
* The logic is, save rnchannels : # of channels (conversions) in ADC_SQR1_L
* Then, take the chanlist array and store it in the SQR Regs,
* chanlist[0] -> ADC_SQR3_SQ1
* chanlist[1] -> ADC_SQR3_SQ2
@@ -2163,7 +2264,7 @@ static uint32_t adc_injget(FAR struct stm32_adc_dev_s *dev, uint8_t chan)
* chanlist[15]-> ADC_SQR1_SQ16
*
* up to
* chanlist[nchannels]
* chanlist[rnchannels]
*
* Input Parameters:
* intf - Could be {1,2,3} for ADC1, ADC2, or ADC3
@@ -2175,35 +2276,44 @@ static uint32_t adc_injget(FAR struct stm32_adc_dev_s *dev, uint8_t chan)
*
****************************************************************************/
#ifndef ADC_HAVE_INJECTED
struct adc_dev_s *stm32_adcinitialize(int intf,
FAR const uint8_t *r_chanlist, int cr_channels)
#else
struct adc_dev_s *stm32_adcinitialize(int intf,
FAR const uint8_t *r_chanlist, int cr_channels,
FAR const uint8_t *j_chanlist, int cj_channels)
#endif
struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
int channels)
{
FAR struct adc_dev_s *dev;
FAR struct stm32_dev_s *priv;
uint8_t cr_channels = 0;
uint8_t cj_channels = 0;
FAR uint8_t *j_chanlist = NULL;
switch (intf)
{
#ifdef CONFIG_STM32_ADC1
case 1:
ainfo("ADC1 selected\n");
dev = &g_adcdev1;
break;
{
ainfo("ADC1 selected\n");
dev = &g_adcdev1;
cr_channels = channels - ADC1_INJECTED_CHAN;
cj_channels = ADC1_INJECTED_CHAN;
j_chanlist = (FAR uint8_t *)chanlist + cr_channels;
break;
}
#endif
#ifdef CONFIG_STM32_ADC2
case 2:
ainfo("ADC2 selected\n");
dev = &g_adcdev2;
break;
{
ainfo("ADC2 selected\n");
dev = &g_adcdev2;
cr_channels = channels - ADC2_INJECTED_CHAN;
cj_channels = ADC2_INJECTED_CHAN;
j_chanlist = chanlist + cr_channels;
break;
}
#endif
default:
aerr("ERROR: No ADC interface defined\n");
return NULL;
{
aerr("ERROR: No ADC interface defined\n");
return NULL;
}
}
/* Configure the selected ADC */
@@ -2215,7 +2325,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf,
/* Configure regular channels */
priv->cr_channels = cr_channels;
memcpy(priv->r_chanlist, r_chanlist, cr_channels);
memcpy(priv->r_chanlist, chanlist, cr_channels);
#ifdef ADC_HAVE_INJECTED
/* Configur injected channels */
@@ -2232,9 +2342,9 @@ struct adc_dev_s *stm32_adcinitialize(int intf,
#ifdef ADC_HAVE_INJECTED
ainfo("intf: %d cr_channels: %d, cj_channels: %d\n",
intf, cr_channels, priv->cj_channels);
intf, priv->cr_channels, priv->cj_channels);
#else
ainfo("intf: %d cr_channels: %d\n", intf, cr_channels);
ainfo("intf: %d cr_channels: %d\n", intf, priv->cr_channels);
#endif
return dev;
configs/nucleo-f334r8/highpri/defconfig
+2
View File
@@ -94,6 +94,8 @@ CONFIG_STM32_HRTIM1=y
CONFIG_STM32_HRTIM_CLK_FROM_PLL=y
CONFIG_STM32_HRTIM_DISABLE_CHARDRV=y
CONFIG_STM32_HRTIM_TIMA=y
CONFIG_STM32_HRTIM_ADC=y
CONFIG_STM32_HRTIM_ADC1_TRG1=y
CONFIG_STM32_JTAG_SW_ENABLE=y
CONFIG_STM32_PWR=y
CONFIG_STM32_USART2=y
configs/nucleo-f334r8/src/stm32_highpri.c
+4 -11
View File
@@ -53,7 +53,6 @@
#include "up_internal.h"
#include "ram_vectors.h"
#include "stm32_tim.h"
#include <nuttx/analog/adc.h>
#include <nuttx/analog/ioctl.h>
@@ -106,11 +105,6 @@
#define ADC_REF_VOLTAGE 3.3
#define ADC_VAL_MAX 4095
#define HRTIM_CMP_SET(hrtim, tim, index, cmp) \
hrtim->hd_ops->cmp_update(hrtim, tim, index, cmp)
#define HRTIM_PER_SET(hrtim, tim, per) \
hrtim->hd_ops->per_update(hrtim, tim, per)
/****************************************************************************
* Private Types
****************************************************************************/
@@ -129,6 +123,10 @@ struct highpri_s
float volt[DEV1_NCHANNELS];
};
/****************************************************************************
* Private Data
****************************************************************************/
/* ADC channel list */
static const uint8_t g_chanlist1[DEV1_NCHANNELS] =
@@ -152,10 +150,6 @@ static const uint32_t g_pinlist1[DEV1_NCHANNELS] =
#endif
};
/****************************************************************************
* Private Data
****************************************************************************/
static struct highpri_s g_highpri;
/****************************************************************************
@@ -201,7 +195,6 @@ void adc12_handler(void)
}
adc->ops->int_ack(adc, pending);
}
#endif
configs/stm32f334-disco/include/board.h
+41 -9
View File
@@ -211,15 +211,15 @@
#define GPIO_USART2_RX GPIO_USART2_RX_3 /* PB4 */
#define GPIO_USART2_TX GPIO_USART2_TX_3 /* PB3 */
/* Board configuration for powerled example */
/* - Set HRTIM TIMC output 1 on PERIOD
* - Reset HRTIM TIMC output 1 on HRTIM EEV2.
* - HRTIM EEV2 is connected to COMP4 output which works as current limit.
* - COMP4 inverting input is connected to DAC1CH1 output.
* - COMP4 non-inverting input is connceted to current sense resitor (1 Ohm).
* - DAC1CH1 DMA transfer is triggered by HRTIM TIMC events, which is used
* to provide slope compensation
/* Board configuration for powerled example:
* - Set HRTIM TIMC output 1 (PB12) on PERIOD.
* - Reset HRTIM TIMC output 1 on HRTIM EEV2.
* - HRTIM EEV2 is connected to COMP4 output which works as current limit.
* - COMP4 inverting input is connected to DAC1CH1 output.
* - COMP4 non-inverting input (PB1) is connceted to current sense
* resitor (1 Ohm).
* - DAC1CH1 DMA transfer is triggered by HRTIM TIMC events, which is used
* to provide slope compensation.
*/
#if defined(CONFIG_EXAMPLES_POWERLED)
@@ -257,6 +257,38 @@
#endif /* CONFIG_EXAMPLES_POWERLED */
/* Board configuration for SMPS example:
* PA8 - HRTIM_CHA1
* PA9 - HRTIM_CHA2
* PA10 - HRTIM_CHB1
* PA11 - HRTIM_CHB2
* VIN - ADC Channel 2 (PA1)
* VOUT - ADC Channel 4 (PA3)
*/
#if defined(CONFIG_EXAMPLES_SMPS)
/* ADC configuration ******************************************************/
#define ADC1_INJECTED_CHAN 2
#define ADC1_EXTSEL_VALUE 0
#define ADC1_SMP2 ADC_SMPR_61p5
#define ADC1_SMP4 ADC_SMPR_61p5
/* HRTIM configuration ******************************************************/
#define HRTIM_TIMA_PRESCALER HRTIM_PRESCALER_32
#define HRTIM_TIMA_MODE HRTIM_MODE_CONT
#define HRTIM_TIMB_PRESCALER HRTIM_PRESCALER_32
#define HRTIM_TIMB_MODE HRTIM_MODE_CONT
#define HRTIM_ADC_TRG2 HRTIM_ADCTRG24_AC4
/* DMA channels *************************************************************/
#endif /* CONFIG_EXAMPLES_SMPS */
/****************************************************************************
* Public Data
****************************************************************************/
configs/stm32f334-disco/src/Makefile
+4
View File
@@ -72,4 +72,8 @@ ifeq ($(CONFIG_DRIVERS_POWERLED),y)
CSRCS += stm32_powerled.c
endif
ifeq ($(CONFIG_DRIVERS_SMPS),y)
CSRCS += stm32_smps.c
endif
include $(TOPDIR)/configs/Board.mk
configs/stm32f334-disco/src/stm32_appinit.c
+11 -1
View File
@@ -96,7 +96,7 @@ int board_app_initialize(uintptr_t arg)
{
int ret;
#ifndef CONFIG_DRIVERS_POWERLED
#if !defined(CONFIG_DRIVERS_POWERLED) && !defined(CONFIG_DRIVERS_SMPS)
#ifdef HAVE_LEDS
/* Register the LED driver */
@@ -169,6 +169,16 @@ int board_app_initialize(uintptr_t arg)
}
#endif
#ifdef CONFIG_DRIVERS_SMPS
/* Initialize smps and register the smps driver */
ret = stm32_smps_setup();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: stm32_smps_setup failed: %d\n", ret);
}
#endif
UNUSED(ret);
return OK;
}
configs/stm32f334-disco/src/stm32_powerled.c
+2 -19
View File
@@ -84,23 +84,6 @@
* Pre-processor Definitions
****************************************************************************/
/* REVISIT: Move to stm32_hrtim.h ? */
#define HRTIM_CMP_SET(hrtim, tim, index, cmp) \
hrtim->hd_ops->cmp_update(hrtim, tim, index, cmp)
#define HRTIM_PER_SET(hrtim, tim, per) \
hrtim->hd_ops->per_update(hrtim, tim, per)
#define HRTIM_OUTPUTS_ENABLE(hrtim, tim, state) \
hrtim->hd_ops->outputs_enable(hrtim, tim, state)
#define HRTIM_BURST_CMP_SET(hrtim, cmp) \
hrtim->hd_ops->burst_cmp_set(hrtim, cmp)
#define HRTIM_BURST_PER_SET(hrtim, per) \
hrtim->hd_ops->burst_per_set(hrtim, per)
#define HRTIM_BURST_PRE_SET(hrtim, pre) \
hrtim->hd_ops->burst_pre_set(hrtim, pre)
#define HRTIM_BURST_ENABLE(hrtim, state) \
hrtim->hd_ops->burst_enable(hrtim, state)
#define DAC_BUFFER_INIT(dac, buffer) \
dac->ad_ops->ao_ioctl(dac, IO_DMABUFFER_INIT, (unsigned long)buffer)
@@ -507,9 +490,9 @@ static int powerled_limits_set(FAR struct powerled_dev_s *dev,
goto errout;
}
if (limits->current > LED_ABSOLUTE_CURRENT_LIMIT_mA)
if (limits->current * 1000 > LED_ABSOLUTE_CURRENT_LIMIT_mA)
{
limits->current = LED_ABSOLUTE_CURRENT_LIMIT_mA;
limits->current = (float)LED_ABSOLUTE_CURRENT_LIMIT_mA/1000.0;
printf("LED current limiit > LED absoulute current limit."
" Set current limit to %d.\n",
limits->current);
configs/stm32f334-disco/src/stm32_smps.c
+689
View File
File diff suppressed because it is too large Load Diff
configs/stm32f334-disco/src/stm32f334-disco.h
+12
View File
@@ -207,4 +207,16 @@ int stm32_opamp_setup(void);
int stm32_powerled_setup(void);
#endif
/****************************************************************************
* Name: stm32_smps_setup
*
* Description:
* Initialize SMPS peripheral for the board.
*
****************************************************************************/
#ifdef CONFIG_DRIVERS_SMPS
int stm32_smps_setup(void);
#endif
#endif /* __CONFIGS_STM32F334_DISCO_SRC_STM32F334_DISCO_H */
drivers/power/smps.c
+3 -3
View File
@@ -421,7 +421,7 @@ static int smps_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
if (smps->limits.v_out > 0 && params->v_out > smps->limits.v_out)
{
pwrerr("ERROR: params->v_out > limits.v_out: %d > %d\n",
pwrerr("ERROR: params->v_out > limits.v_out: %.2f > %.2f\n",
params->v_out, smps->limits.v_out);
ret = -EPERM;
@@ -432,7 +432,7 @@ static int smps_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
if (smps->limits.i_out > 0 && params->i_out > smps->limits.i_out)
{
pwrerr("ERROR: params->i_out > limits.i_out: %d > %d\n",
pwrerr("ERROR: params->i_out > limits.i_out: %.2f > %.2f\n",
params->i_out, smps->limits.i_out);
ret = -EPERM;
@@ -443,7 +443,7 @@ static int smps_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
if (smps->limits.p_out > 0 && params->p_out > smps->limits.p_out)
{
pwrerr("ERROR: params->p_out > limits.p_out: %d > %d\n",
pwrerr("ERROR: params->p_out > limits.p_out: %.2f > %.2f\n",
params->p_out, smps->limits.p_out);
ret = -EPERM;
include/nuttx/power/smps.h
+3 -3
View File
@@ -121,15 +121,15 @@ struct smps_feedback_s
#ifdef CONFIG_SMPS_HAVE_OUTPUT_VOLTAGE
float v_out; /* Output Voltage */
#endif
#ifdef CONFIG_SMPS_HAVE_INPUT_CURRENT
float i_in; /* Input Current */
#endif
#ifdef CONFIG_SMPS_HAVE_INPUT_VOLTAGE
float v_in; /* Input Voltage */
#endif
#ifdef CONFIG_SMPS_HAVE_OUTPUT_CURRENT
float i_out; /* Output Current */
#endif
#ifdef CONFIG_SMPS_HAVE_INPUT_CURRENT
float i_in; /* Input Current */
#endif
#ifdef CONFIG_SMPS_HAVE_INPUT_POWER
float p_in; /* Input Power */
#endif