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arch/risc-v/rp23xx-riscv: Add rp23xx RISC-V cores support (Hazard3)

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Chip name   : rp23xx-rv
Board name  : raspberrypi-pico-2-rv
Arch        : risc-v

Changes from ARM rp23xx impl

- Linker script update
- ASM head start
- Update chip start
- New Hazard3 registers
- Remove rp23xx chip hw spinlocks/testset
- New irq handling (external IRQ interrupt Hazard3)
- New timerisr based on RISC-V std MTIME and alarm arch
- No SMP yet
- Tickless option
- Double size for idle, irq and main stacks
- Board reset via watchdog trigger

Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
This commit is contained in:
Serg Podtynnyi
2025-05-22 02:38:16 +07:00
committed by Xiang Xiao
parent d218334baa
commit 2e7f75f6e0
154 changed files with 41402 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
.codespellrc
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@@ -62,3 +62,4 @@ ignore-words-list =
tolen,
UE,
WRON,
SIE,

8
Documentation/platforms/arm/rp23xx/boards/raspberrypi-pico-2/index.rst
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@@ -191,7 +191,7 @@ Installation
$ git clone https://github.com/apache/nuttx-apps.git apps
$ cd nuttx
$ make distclean
$ ./tools/configure.sh raspberrypi-pico:nsh
$ ./tools/configure.sh raspberrypi-pico-2:nsh
$ make V=1
5. Connect Raspberry Pi Pico 2 board to USB port while pressing BOOTSEL.
@@ -214,6 +214,12 @@ nsh
Basic NuttShell configuration (console enabled in UART0, at 115200 bps).
usbnsh
---
Basic NuttShell configuration (console enabled via USB CDC/ACM).
smp
---

4
Documentation/platforms/arm/rp23xx/index.rst
View File

@@ -7,7 +7,9 @@ RaspberryPi rp2350
The rp2350 is a dual core chip produced by the RaspberryPi Foundation that
is based on ARM Cortex-M33 or the Hazard3 RISC-V.
For now, only the ARM Cortex-M33 is supported.
ARM Cortex-M33 and Hazard3 RISC-V cores are supported.
This is ARM Cortex-M33 version of the chip configuration.
This port is experimental and still a work in progress. Use with caution.

230
Documentation/platforms/risc-v/rp23xx-rv/boards/raspberrypi-pico-2-rv/index.rst Normal file
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@@ -0,0 +1,230 @@
===============================
Raspberry Pi Pico 2 RISC-V
===============================
.. tags:: chip:rp2350
The `Raspberry Pi Pico 2 <https://www.raspberrypi.com/products/raspberry-pi-pico-2/>`_ is a general purpose board supplied by
the Raspberry Pi Foundation.
.. figure:: pico-2.png
:align: center
Features
========
* RP2350 microcontroller chip
* Dual-core Hazard3 RISC-V processor, flexible clock running up to 150 MHz
* 520kB of SRAM, and 4MB of on-board Flash memory
* Castellated module allows soldering direct to carrier boards
* USB 1.1 Host and Device support
* Low-power sleep and dormant modes
* Drag & drop programming using mass storage over USB
* 26 multi-function GPIO pins
* 2× SPI, 2× I2C, 2× UART, 3× 12-bit ADC, 16× controllable PWM channels
* Accurate clock and timer on-chip
* Temperature sensor
* Accelerated floating point libraries on-chip
* 12 × Programmable IO (PIO) state machines for custom peripheral support
Serial Console
==============
By default a serial console appears on pins 1 (TX GPIO0) and pin 2
(RX GPIO1). This console runs a 115200-8N1.
The board can be configured to use the USB connection as the serial console.
See the `usbnsh` configuration.
Buttons and LEDs
================
User LED controlled by GPIO25 and is configured as autoled by default.
A BOOTSEL button, which if held down when power is first
applied to the board, will cause the Pico 2 to boot into programming
mode and appear as a storage device to the computer connected via USB.
Saving a .UF2 file to this device will replace the Flash ROM contents
on the Pico 2.
Pin Mapping
===========
Pads numbered anticlockwise from USB connector.
===== ========== ==========
Pad Signal Notes
===== ========== ==========
1 GPIO0 Default TX for UART0 serial console
2 GPIO1 Default RX for UART1 serial console
3 Ground
4 GPIO2
5 GPIO3
6 GPIO4 Default SDA for I2C0
7 GPIO5 Default SCL for I2C0
8 Ground
9 GPIO6 Default SDA for I2C1
10 GPIO7 Default SCL for I2C1
11 GPIO8 Default RX for SPI1
12 GPIO9 Default CSn for SPI1
13 Ground
14 GPIO10 Default SCK for SPI1
15 GPIO11 Default TX for SPI1
16 GPIO12
17 GPIO13
18 Ground
19 GPIO14
20 GPIO15
21 GPIO16 Default RX for SPI0
22 GPIO17 Default CSn for SPI0
23 Ground
24 GPIO18 Default SCK for SPI0
25 GPIO19 Default TX for SPI0
26 GPIO20 Default TX for UART1 serial console
27 GPIO21 Default RX for UART1 serial console
28 Ground
29 GPIO22
30 Run
31 GPIO26 ADC0
32 GPIO27 ADC1
33 AGND Analog Ground
34 GPIO28 ADC2
35 ADC_VREF Analog reference voltage
36 3V3 Power output to peripherals
37 3V3_EN Pull to ground to turn off.
38 Ground
39 VSYS +5V Supply to board
40 VBUS Connected to USB +5V
===== ========== ==========
Other Pico 2 Pins
=================
GPIO23 Output - Power supply control.
GPIO24 Input - High if USB port or Pad 40 supplying power.
GPIO25 Output - On board LED.
ADC3 Input - Analog voltage equal to one third of VSys voltage.
Separate pins for the Serial Debug Port (SDB) are available
Power Supply
============
The Raspberry Pi Pico 2 can be powered via the USB connector,
or by supplying +5V to pin 39. The board had a diode that prevents
power from pin 39 from flowing back to the USB socket, although
the socket can be power via pin 30.
The Raspberry Pi Pico chip run on 3.3 volts. This is supplied
by an onboard voltage regulator. This regulator can be disabled
by pulling pin 37 to ground.
The regulator can run in two modes. By default the regulator runs
in PFM mode which provides the best efficiency, but may be
switched to PWM mode for improved ripple by outputting a one
on GPIO23.
Supported Capabilities
======================
NuttX supports the following Pico 2 capabilities:
* UART (console port)
* GPIO 0 (UART0 TX) and GPIO 1 (UART0 RX) are used for the console.
* I2C
* SPI (master only)
* DMAC
* PWM
* ADC
* Watchdog
* USB device
* MSC, CDC/ACM serial and these composite device are supported.
* CDC/ACM serial device can be used for the console.
* PIO (RP2350 Programmable I/O)
* Flash ROM Boot
* SRAM Boot
* If Pico SDK is available, nuttx.uf2 file which can be used in BOOTSEL mode will be created.
* Persistent flash filesystem in unused flash ROM
There is currently no direct user mode access to these RP2350 hardware features:
* SPI Slave Mode
* SSI
* RTC
* Timers
RICS-V toolchain
================
Download and install RISC-V compatible toolchain
with arch `rv32imac` and `ilp32` abi.
https://xpack-dev-tools.github.io/riscv-none-elf-gcc-xpack/
Installation
============
1. Download Raspberry Pi Pico SDK
.. code-block:: console
$ git clone -b 2.1.1 https://github.com/raspberrypi/pico-sdk.git
2. Download and install picotool
Instructions can be found here: https://github.com/raspberrypi/picotool
If you are on Arch Linux, you can install the picotool through the AUR:
.. code-block:: console
$ yay -S picotool
3. Set PICO_SDK_PATH environment variable
.. code-block:: console
$ export PICO_SDK_PATH=<absolute_path_to_pico-sdk_directory>
4. Configure and build NuttX
.. code-block:: console
$ git clone https://github.com/apache/nuttx.git nuttx
$ git clone https://github.com/apache/nuttx-apps.git apps
$ cd nuttx
$ make distclean
$ ./tools/configure.sh raspberrypi-pico-2-rv:nsh
$ make V=1
5. Connect Raspberry Pi Pico 2 board to USB port while pressing BOOTSEL.
The board will be detected as USB Mass Storage Device.
Then copy "nuttx.uf2" into the device.
(Same manner as the standard Pico SDK applications installation.)
6. To access the console, GPIO 0 and 1 pins must be connected to the
device such as USB-serial converter.
`usbnsh` configuration provides the console access by USB CDC/ACM serial
device. The console is available by using a terminal software on the USB
host.
Configurations
==============
nsh
---
Basic NuttShell configuration (console enabled in UART0, at 115200 bps).
usbnsh
---
Basic NuttShell configuration (console enabled via USB CDC/ACM).

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219
Documentation/platforms/risc-v/rp23xx-rv/index.rst Normal file
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@@ -0,0 +1,219 @@
=========================
RaspberryPi rp2350 RISC-V
=========================
.. tags:: chip:rp2350
The rp2350 is a dual core chip produced by the RaspberryPi Foundation that
is based on ARM Cortex-M33 or the Hazard3 RISC-V.
ARM Cortex-M33 and Hazard3 RISC-V cores are supported.
This is RISC-V version of the chip configuration.
This port is experimental and still a work in progress. Use with caution.
SMP (dual core configuration not supported yet)
Peripheral Support
==================
Most drivers were copied from the rp2040 port with some modifications.
The following list indicates peripherals currently supported in NuttX:
============== ============ =====
Peripheral Status Notes
============== ============ =====
GPIO Working See Supported Boards documentation for available pins.
UART Working GPIO 0 (UART0 TX) and GPIO 1 (UART0 RX) are used for the console.
I2C Working
SPI Master Working
SPI Slave Untested
DMAC Working
PWM Working
USB Working
PIO Working
IRQs Working
WDOG Working
DMA Working
FPU/DSP INOP Available in ARM configuration of the chip
Clock Output Untested
Flash ROM Boot Working Does not require boot2 from pico-sdk
If picotool is available a nuttx.uf2 file will be created
SRAM Boot Working Requires external SWD debugger
PSRAM Working Three modes of heap allocation described below
============== ============ =====
Installation
============
1. Download and build picotool, make it available in the PATH::
git clone https://github.com/raspberrypi/picotool.git picotool
cd picotool
mkdir build
cd build
cmake ..
make
cp picotool ~/local/bin # somewhere in your PATH
2. Download NuttX and the companion applications. These must both be
contained in the same directory::
git clone https://github.com/apache/nuttx.git nuttx
git clone https://github.com/apache/nuttx-apps.git apps
3. Download and install RISC-V compatible toolchain
with arch `rv32imac` and `ilp32` abi.
https://xpack-dev-tools.github.io/riscv-none-elf-gcc-xpack/
Building NuttX
==============
1. Change to NuttX directory::
cd nuttx
2. Select a configuration. The available configurations
can be listed with the command::
./tools/configure.sh -L
3. Load the selected configuration.::
make distclean
./tools/configure.sh raspberrypi-pico-2-rv:usbnsh
4. Modify the configuration as needed (optional)::
make menuconfig
5. Build NuttX::
make
Flash boot
==========
By default, the system is built to build and run from the flash
using XIP. By using the default `BOOT_RUNFROMFLASH` configuration,
the full image is run from the flash making most of the internal
SRAM available for the OS and applications, however the execution
is slower. The cache can speed up, but you might want set your
time critical functions to be placed in the SRAM (copied from
the flash on startup).
It is also possible to execute from SRAM, which reduces the
available SRAM to the OS and applications, however it is very
useful when debugging as erasing and rewriting the flash on
every build is tedious and slow. This option is enabled with
`BOOT_RUNFROMISRAM` and requires `openocd`` and/or `gdb`.
There is a third option which is to write the firmware on the
flash and it gets copied to the SRAM. This is enabled with
`CONFIG_BOOT_COPYTORAM` and might be useful for time critical
applications, on the expense of reduced usable internal SRAM
memory.
PSRAM
=====
Some boards like the `pimoroni-pico-2-plus` have a PSRAM
which greatly increases the available memory for applications.
The PSRAM is very slow compared to the internal SRAM,
so depending on the application, different configuration might
be necessary.
To use the PSRAM, enable the `RP23XX_PSRAM` and select the GPIO
pin used as CS1n with `RP23XX_PSRAM_CS1_GPIO`. See the RP2350
datasheet for more information.
The port offers three options for configuring the heaps to use
the external PSRAM, described below. More custom configurations
can be used with custom board initialization functions.
Use PSRAM and SRAM as a single main heap
----------------------------------------
This option is selected with `RP23XX_PSRAM_HEAP_SINGLE` and
requires `MM_REGIONS > 1`, as the PSRAM memory region will
be added to the heap. It is also necessary to disable
`MM_KERNEL_HEAP`, as there will only be a single heap.
This is the simplest configuration because it will unify the
memories into a single main heap. This way you can see the `free`
command output the total amount of usable RAM in the heap.
However, there are some unpredictable performance issues because
there is no control of where the memory is allocated when issuing
`malloc(3)` and `free(3)`. For this reason, you might want to
consider the other options.
Use PSRAM as user heap, SRAM as kernel heap
-------------------------------------------
This option is selected with `RP23XX_PSRAM_HEAP_USER` and
requires `MM_KERNEL_HEAP` to be set.
The external PSRAM is allocated to the default heap, while
the internal SRAM will be used for the kernel heap. This
configuration is useful because it allows drivers to
use the SRAM and behave much faster than if they used
memory on the PSRAM. While user applications can take
the bull benefit of the larger slower heap on the PSRAM.
Use PSRAM as a separate heap
----------------------------
This option is selected with `RP23XX_PSRAM_HEAP_SEPARATE` and
requires `ARCH_HAVE_EXTRA_HEAPS` to be set.
The internal SRAM is used as the main heap for kernel and
applications, as if there was no PSRAM configured. The
external PSRAM is configured as a separate user heap called
`psram` and can be used through the global variable
`g_psramheap` after including `rp23xx_heaps.h`
Programming
============
Programming using BOOTSEL
-------------------------
Connect board to USB port while holding BOOTSEL.
The board will be detected as USB Mass Storage Device.
Then copy "nuttx.uf2" into the device.
(Same manner as the standard Pico SDK applications installation.)
Programming with picotool
-------------------------
You can use picotool to load the elf (or the uf2)::
picotool load nuttx -t elf
Programming using SWD debugger
------------------------------
Most boards provide a serial (SWD) debug port.
The "nuttx" ELF file can be uploaded with an appropriate SDB programmer
module and companion software (openocd and gdb)
Running NuttX
=============
Most builds provide access to the console via UART0. To access this
GPIO 0 and 1 pins must be connected to the device such as USB-serial converter.
The `usbnsh` configuration provides the console access by USB CDC/ACM serial
device. The console is available by using a terminal software on the USB host.
Supported Boards
================
.. toctree::
:glob:
:maxdepth: 1
boards/*/*

23
arch/risc-v/Kconfig
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@@ -369,6 +369,24 @@ config ARCH_CHIP_EIC7700X
---help---
ESWIN EIC7700X SoC.
config ARCH_CHIP_RP23XX_RV
bool "Raspberry Pi RP23XX RISC-V"
select ARCH_RV32
select ARCH_RV_ISA_M
select ARCH_RV_ISA_A
select ARCH_RV_ISA_C
select ARCH_HAVE_PWM_MULTICHAN
select ARCH_HAVE_RESET
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_TICKLESS
select ONESHOT
select ALARM_ARCH
select ARCH_HAVE_I2CRESET
select ARCH_BOARD_COMMON
---help---
Raspberry Pi RP23XX architectures (RISC-V dual Hazard3).
config ARCH_CHIP_RISCV_CUSTOM
bool "Custom RISC-V chip"
select ARCH_CHIP_CUSTOM
@@ -554,6 +572,7 @@ config ARCH_CHIP
default "k230" if ARCH_CHIP_K230
default "sg2000" if ARCH_CHIP_SG2000
default "eic7700x" if ARCH_CHIP_EIC7700X
default "rp23xx-rv" if ARCH_CHIP_RP23XX_RV
config ARCH_RISCV_INTXCPT_EXTENSIONS
bool "RISC-V Integer Context Extensions"
@@ -797,4 +816,8 @@ endif
if ARCH_CHIP_EIC7700X
source "arch/risc-v/src/eic7700x/Kconfig"
endif
if ARCH_CHIP_RP23XX_RV
source "arch/risc-v/src/rp23xx-rv/Kconfig"
endif
endif # ARCH_RISCV

36
arch/risc-v/include/arch.h
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@@ -38,6 +38,42 @@
# include <stddef.h>
#endif
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
#ifdef CONFIG_PIC
#define PIC_REG x29
#define PIC_REG_STRING "x29"
#define up_getpicbase(ppicbase) \
do { \
uintptr_t picbase; \
__asm__ volatile \
( \
"mv %0, " PIC_REG_STRING \
: "=r"(picbase) \
: \
: \
); \
*(uintptr_t *)ppicbase = picbase; \
} while (0)
#define up_setpicbase(picbase) \
do { \
uintptr_t _picbase = (uintptr_t)picbase; \
__asm__ volatile \
( \
"mv " PIC_REG_STRING ", %0" \
: \
: "r"(_picbase) \
: PIC_REG_STRING \
); \
} while (0)
#endif /* CONFIG_PIC */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/

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arch/risc-v/include/rp23xx-rv/chip.h Normal file
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@@ -0,0 +1,26 @@
/****************************************************************************
* arch/risc-v/include/rp23xx-rv/chip.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_INCLUDE_RP23XX_RV_CHIP_H
#define __ARCH_RISCV_INCLUDE_RP23XX_RV_CHIP_H
#endif /* __ARCH_RISCV_INCLUDE_RP23XX_RV_CHIP_H */

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arch/risc-v/include/rp23xx-rv/i2c_slave.h Normal file
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@@ -0,0 +1,116 @@
/****************************************************************************
* arch/risc-v/include/rp23xx-rv/i2c_slave.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_INCLUDE_RP23XX_RV_I2C_SLAVE_H
#define __ARCH_RISCV_INCLUDE_RP23XX_RV_I2C_SLAVE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/i2c/i2c_slave.h>
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* There is no driver for I2C slave operations. To create an I2C slave,
* include this file (as: <arch/chip/i2c_slave.h>) and use either
* rp23xx_i2c0_slave_initialize or rp23xx_i2c1_slave_initialize to
* initialize the I2C for slave operations.
*/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: rp23xx_i2c0_slave_initialize
*
* Description:
* Initialize I2C controller zero for slave operation, and return a pointer
* to the instance of struct i2c_slave_s. This function should only be
* called once of a give controller.
*
* Note: the same port cannot be initialized as both master and slave.
*
* Input Parameters:
* rx_buffer - Buffer for data transmitted to us by an I2C master.
* rx_buffer_len - Length of rx_buffer.
* callback - Callback function called when messages are received.
*
* Returned Value:
* Valid I2C device structure reference on success; a NULL on failure
*
****************************************************************************/
#ifdef CONFIG_RP23XX_RV_I2C0_SLAVE
struct i2c_slave_s *rp23xx_i2c0_slave_initialize
(uint8_t *rx_buffer,
size_t rx_buffer_len,
i2c_slave_callback_t *callback);
#endif
/****************************************************************************
* Name: rp23xx_i2c1_slave_initialize
*
* Description:
* Initialize I2C controller zero for slave operation, and return a pointer
* to the instance of struct i2c_slave_s. This function should only be
* called once of a give controller.
*
* Note: the same port cannot be initialized as both master and slave.
*
* Input Parameters:
* rx_buffer - Buffer for data transmitted to us by an I2C master.
* rx_buffer_len - Length of rx_buffer.
* callback - Callback function called when messages are received.
*
* Returned Value:
* Valid I2C device structure reference on success; a NULL on failure
*
****************************************************************************/
#ifdef CONFIG_RP23XX_RV_I2C1_SLAVE
struct i2c_slave_s *rp23xx_i2c1_slave_initialize
(uint8_t *rx_buffer,
size_t rx_buffer_len,
i2c_slave_callback_t *callback);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_INCLUDE_RP23XX_RV_I2C_SLAVE_H */

134
arch/risc-v/include/rp23xx-rv/irq.h Normal file
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@@ -0,0 +1,134 @@
/****************************************************************************
* arch/risc-v/include/rp23xx-rv/irq.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_RISCV_INCLUDE_RP23XX_IRQ_H
#define __ARCH_RISCV_INCLUDE_RP23XX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ASSEMBLY__
# include <stdint.h>
#endif
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
#define RP23XX_IRQ_EXTINT (RISCV_IRQ_ASYNC + 32) /* Vector 48: Vector number of the first external interrupt */
/* External interrupts (vectors >= 48). These definitions are
* chip-specific
*/
#define RP23XX_TIMER0_IRQ_0 (RP23XX_IRQ_EXTINT+0)
#define RP23XX_TIMER0_IRQ_1 (RP23XX_IRQ_EXTINT+1)
#define RP23XX_TIMER0_IRQ_2 (RP23XX_IRQ_EXTINT+2)
#define RP23XX_TIMER0_IRQ_3 (RP23XX_IRQ_EXTINT+3)
#define RP23XX_TIMER1_IRQ_0 (RP23XX_IRQ_EXTINT+4)
#define RP23XX_TIMER1_IRQ_1 (RP23XX_IRQ_EXTINT+5)
#define RP23XX_TIMER1_IRQ_2 (RP23XX_IRQ_EXTINT+6)
#define RP23XX_TIMER1_IRQ_3 (RP23XX_IRQ_EXTINT+7)
#define RP23XX_RV_PWM_IRQ_WRAP_0 (RP23XX_IRQ_EXTINT+8)
#define RP23XX_RV_PWM_IRQ_WRAP_1 (RP23XX_IRQ_EXTINT+9)
#define RP23XX_DMA_IRQ_0 (RP23XX_IRQ_EXTINT+10)
#define RP23XX_DMA_IRQ_1 (RP23XX_IRQ_EXTINT+11)
#define RP23XX_DMA_IRQ_2 (RP23XX_IRQ_EXTINT+12)
#define RP23XX_DMA_IRQ_3 (RP23XX_IRQ_EXTINT+13)
#define RP23XX_USBCTRL_IRQ (RP23XX_IRQ_EXTINT+14)
#define RP23XX_PIO0_IRQ_0 (RP23XX_IRQ_EXTINT+15)
#define RP23XX_PIO0_IRQ_1 (RP23XX_IRQ_EXTINT+16)
#define RP23XX_PIO1_IRQ_0 (RP23XX_IRQ_EXTINT+17)
#define RP23XX_PIO1_IRQ_1 (RP23XX_IRQ_EXTINT+18)
#define RP23XX_PIO2_IRQ_0 (RP23XX_IRQ_EXTINT+19)
#define RP23XX_PIO2_IRQ_1 (RP23XX_IRQ_EXTINT+20)
#define RP23XX_IO_IRQ_BANK0 (RP23XX_IRQ_EXTINT+21)
#define RP23XX_IO_IRQ_BANK0_NS (RP23XX_IRQ_EXTINT+22)
#define RP23XX_IO_IRQ_QSPI (RP23XX_IRQ_EXTINT+23)
#define RP23XX_IO_IRQ_QSPI_NS (RP23XX_IRQ_EXTINT+24)
#define RP23XX_SIO_IRQ_FIFO (RP23XX_IRQ_EXTINT+25)
#define RP23XX_SIO_IRQ_BELL (RP23XX_IRQ_EXTINT+26)
#define RP23XX_SIO_IRQ_FIFO_NS (RP23XX_IRQ_EXTINT+27)
#define RP23XX_SIO_IRQ_BELL_NS (RP23XX_IRQ_EXTINT+28)
#define RP23XX_SIO_IRQ_MTIMECMP (RP23XX_IRQ_EXTINT+29)
#define RP23XX_CLOCKS_IRQ (RP23XX_IRQ_EXTINT+30)
#define RP23XX_RV_SPI0_IRQ (RP23XX_IRQ_EXTINT+31)
#define RP23XX_RV_SPI1_IRQ (RP23XX_IRQ_EXTINT+32)
#define RP23XX_RV_UART0_IRQ (RP23XX_IRQ_EXTINT+33)
#define RP23XX_RV_UART1_IRQ (RP23XX_IRQ_EXTINT+34)
#define RP23XX_RV_ADC_IRQ_FIFO (RP23XX_IRQ_EXTINT+35)
#define RP23XX_RV_I2C0_IRQ (RP23XX_IRQ_EXTINT+36)
#define RP23XX_RV_I2C1_IRQ (RP23XX_IRQ_EXTINT+37)
#define RP23XX_OTP_IRQ (RP23XX_IRQ_EXTINT+38)
#define RP23XX_TRNG_IRQ (RP23XX_IRQ_EXTINT+39)
#define RP23XX_PROC0_IRQ_CTI (RP23XX_IRQ_EXTINT+40)
#define RP23XX_PROC1_IRQ_CTI (RP23XX_IRQ_EXTINT+41)
#define RP23XX_PLL_SYS_IRQ (RP23XX_IRQ_EXTINT+42)
#define RP23XX_PLL_USB_IRQ (RP23XX_IRQ_EXTINT+43)
#define RP23XX_POWMAN_IRQ_POW (RP23XX_IRQ_EXTINT+44)
#define RP23XX_POWMAN_IRQ_TIMER (RP23XX_IRQ_EXTINT+45)
#define RP23XX_SPAREIRQ_IRQ_0 (RP23XX_IRQ_EXTINT+46)
#define RP23XX_SPAREIRQ_IRQ_1 (RP23XX_IRQ_EXTINT+47)
#define RP23XX_SPAREIRQ_IRQ_2 (RP23XX_IRQ_EXTINT+48)
#define RP23XX_SPAREIRQ_IRQ_3 (RP23XX_IRQ_EXTINT+49)
#define RP23XX_SPAREIRQ_IRQ_4 (RP23XX_IRQ_EXTINT+50)
#define RP23XX_SPAREIRQ_IRQ_5 (RP23XX_IRQ_EXTINT+51)
#define RP23XX_IRQ_NEXTINT (52)
#define RP23XX_IRQ_NIRQS (RP23XX_IRQ_EXTINT+RP23XX_IRQ_NEXTINT)
#define NR_VECTORS RP23XX_IRQ_NIRQS
#define NR_IRQS RP23XX_IRQ_NIRQS
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_INCLUDE_RP23XX_IRQ_H */

97
arch/risc-v/include/rp23xx-rv/watchdog.h Normal file
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@@ -0,0 +1,97 @@
/****************************************************************************
* arch/risc-v/include/rp23xx-rv/watchdog.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_INCLUDE_RP23XX_WATCHDOG_H
#define __ARCH_RISCV_INCLUDE_RP23XX_WATCHDOG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/timers/watchdog.h>
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#ifdef CONFIG_WATCHDOG
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IOCTL Commands ***********************************************************/
/* The watchdog driver uses a standard character driver framework. However,
* since the watchdog driver is a device control interface and not a data
* transfer interface, the majority of the functionality is implemented in
* driver ioctl calls.
*
* See nuttx/timers/watchdog.h for the IOCTLs handled by the upper half.
*
* These are detected and handled by the "lower half" watchdog timer driver.
*
* WDIOC_SET_SCRATCHn - save a 32-bit "arg" value in a scratch register
* that will be preserved over soft resets. A hard
* reset sets all scratch values to zero.
*
* WDIOC_GET_SCRATCHn - fetch a 32-bit value from a scratch register
* into a uint32_t pointed to by "arg".
*/
#define WDIOC_SET_SCRATCH0 _WDIOC(0x180)
#define WDIOC_SET_SCRATCH1 _WDIOC(0x181)
#define WDIOC_SET_SCRATCH2 _WDIOC(0x182)
#define WDIOC_SET_SCRATCH3 _WDIOC(0x183)
#define WDIOC_SET_SCRATCH4 _WDIOC(0x184)
#define WDIOC_SET_SCRATCH5 _WDIOC(0x185)
#define WDIOC_SET_SCRATCH6 _WDIOC(0x186)
#define WDIOC_SET_SCRATCH7 _WDIOC(0x187)
#define WDIOC_SET_SCRATCH(n) _WDIOC(0x180 + (n))
#define WDIOC_GET_SCRATCH0 _WDIOC(0x1f0)
#define WDIOC_GET_SCRATCH1 _WDIOC(0x1f1)
#define WDIOC_GET_SCRATCH2 _WDIOC(0x1f2)
#define WDIOC_GET_SCRATCH3 _WDIOC(0x1f3)
#define WDIOC_GET_SCRATCH4 _WDIOC(0x1f4)
#define WDIOC_GET_SCRATCH5 _WDIOC(0x1f5)
#define WDIOC_GET_SCRATCH6 _WDIOC(0x1f6)
#define WDIOC_GET_SCRATCH7 _WDIOC(0x1f7)
#define WDIOC_GET_SCRATCH(n) _WDIOC(0x1f0 + (n))
#endif /* CONFIG_WATCHDOG */
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_INCLUDE_RP23XX_WATCHDOG_H */

7
arch/risc-v/src/common/riscv_internal.h
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@@ -168,6 +168,13 @@ static inline void putreg64(uint64_t v, const volatile uintreg_t a)
#endif
/* Non-atomic, but more effective modification of registers */
#define modreg8(v,m,a) putreg8((getreg8(a) & ~(m)) | ((v) & (m)), (a))
#define modreg16(v,m,a) putreg16((getreg16(a) & ~(m)) | ((v) & (m)), (a))
#define modreg32(v,m,a) putreg32((getreg32(a) & ~(m)) | ((v) & (m)), (a))
#define modreg64(v,m,a) putreg64((getreg64(a) & ~(m)) | ((v) & (m)), (a))
/****************************************************************************
* Public Types
****************************************************************************/

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arch/risc-v/src/rp23xx-rv/Kconfig Normal file
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89
arch/risc-v/src/rp23xx-rv/Make.defs Normal file
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############################################################################
# arch/risc-v/src/rp23xx-rv/Make.defs
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include common/Make.defs
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
HEAD_ASRC = rp23xx_head.S
CFLAGS += -Wno-array-bounds
CHIP_CSRCS += rp23xx_idle.c
CHIP_CSRCS += rp23xx_irq.c
CHIP_CSRCS += rp23xx_irq_dispatch.c
CHIP_CSRCS += rp23xx_uart.c
CHIP_CSRCS += rp23xx_serial.c
CHIP_CSRCS += rp23xx_start.c
CHIP_CSRCS += rp23xx_timerisr.c
CHIP_CSRCS += rp23xx_gpio.c
CHIP_CSRCS += rp23xx_pio.c
CHIP_CSRCS += rp23xx_clock.c
CHIP_CSRCS += rp23xx_xosc.c
CHIP_CSRCS += rp23xx_pll.c
ifeq ($(CONFIG_SMP),y)
CHIP_CSRCS += rp23xx_cpustart.c
CHIP_CSRCS += rp23xx_smpcall.c
CHIP_CSRCS += rp23xx_cpuidlestack.c
endif
ifeq ($(CONFIG_RP23XX_RV_DMAC),y)
CHIP_CSRCS += rp23xx_dmac.c
endif
ifeq ($(CONFIG_RP23XX_RV_SPI),y)
CHIP_CSRCS += rp23xx_spi.c
endif
ifeq ($(CONFIG_RP23XX_RV_PWM),y)
CHIP_CSRCS += rp23xx_pwm.c
endif
ifeq ($(CONFIG_RP23XX_RV_I2C),y)
CHIP_CSRCS += rp23xx_i2c.c
endif
ifeq ($(CONFIG_RP23XX_RV_I2C_SLAVE),y)
CHIP_CSRCS += rp23xx_i2c_slave.c
endif
ifeq ($(CONFIG_RP23XX_RV_I2S),y)
CHIP_CSRCS += rp23xx_i2s.c
CHIP_CSRCS += rp23xx_i2s_pio.c
endif
ifeq ($(CONFIG_USBDEV),y)
CHIP_CSRCS += rp23xx_usbdev.c
endif
ifeq ($(CONFIG_WS2812),y)
CHIP_CSRCS += rp23xx_ws2812.c
endif
ifeq ($(CONFIG_ADC),y)
CHIP_CSRCS += rp23xx_adc.c
endif
ifeq ($(CONFIG_WATCHDOG),y)
CHIP_CSRCS += rp23xx_wdt.c
endif

47
arch/risc-v/src/rp23xx-rv/chip.h Normal file
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@@ -0,0 +1,47 @@
/****************************************************************************
* arch/risc-v/src/rp23xx-rv/chip.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISCV_SRC_RP23XX_RV_CHIP_H
#define __ARCH_RISCV_SRC_RP23XX_RV_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <nuttx/arch.h>
#endif
/* Include the chip capabilities file */
#include <arch/rp23xx-rv/chip.h>
/****************************************************************************
* Macro Definitions
****************************************************************************/
#ifdef __ASSEMBLY__
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISCV_SRC_RP23XX_RV_CHIP_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_accessctrl.h Normal file
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99
arch/risc-v/src/rp23xx-rv/hardware/rp23xx_adc.h Normal file
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@@ -0,0 +1,99 @@
/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_adc.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_ADC_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_ADC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_RV_ADC_CS_OFFSET 0x00000000
#define RP23XX_RV_ADC_RESULT_OFFSET 0x00000004
#define RP23XX_RV_ADC_FCS_OFFSET 0x00000008
#define RP23XX_RV_ADC_FIFO_OFFSET 0x0000000c
#define RP23XX_RV_ADC_DIV_OFFSET 0x00000010
#define RP23XX_RV_ADC_INTR_OFFSET 0x00000014
#define RP23XX_RV_ADC_INTE_OFFSET 0x00000018
#define RP23XX_RV_ADC_INTF_OFFSET 0x0000001c
#define RP23XX_RV_ADC_INTS_OFFSET 0x00000020
/* Register definitions *****************************************************/
#define RP23XX_RV_ADC_CS (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_CS_OFFSET)
#define RP23XX_RV_ADC_RESULT (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_RESULT_OFFSET)
#define RP23XX_RV_ADC_FCS (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_FCS_OFFSET)
#define RP23XX_RV_ADC_FIFO (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_FIFO_OFFSET)
#define RP23XX_RV_ADC_DIV (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_DIV_OFFSET)
#define RP23XX_RV_ADC_INTR (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_INTR_OFFSET)
#define RP23XX_RV_ADC_INTE (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_INTE_OFFSET)
#define RP23XX_RV_ADC_INTF (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_INTF_OFFSET)
#define RP23XX_RV_ADC_INTS (RP23XX_RV_ADC_BASE + RP23XX_RV_ADC_INTS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_RV_ADC_CS_MASK (0x01fff70f)
#define RP23XX_RV_ADC_CS_RROBIN_SHIFT (16)
#define RP23XX_RV_ADC_CS_RROBIN_MASK (0x01ff << RP23XX_RV_ADC_CS_RROBIN_SHIFT)
#define RP23XX_RV_ADC_CS_AINSEL_SHIFT (12)
#define RP23XX_RV_ADC_CS_AINSEL_MASK (0x000fl << RP23XX_RV_ADC_CS_AINSEL_SHIFT)
#define RP23XX_RV_ADC_CS_ERR_STICKY (1 << 10)
#define RP23XX_RV_ADC_CS_ERR (1 << 9)
#define RP23XX_RV_ADC_CS_READY (1 << 8)
#define RP23XX_RV_ADC_CS_START_MANY (1 << 3)
#define RP23XX_RV_ADC_CS_START_ONCE (1 << 2)
#define RP23XX_RV_ADC_CS_TS_EN (1 << 1)
#define RP23XX_RV_ADC_CS_EN (1 << 0)
#define RP23XX_RV_ADC_RESULT_MASK (0x00000fff)
#define RP23XX_RV_ADC_FCS_MASK (0x0f0f0f0f)
#define RP23XX_RV_ADC_FCS_THRESH_SHIFT (24)
#define RP23XX_RV_ADC_FCS_THRESH_MASK (0x000fl << RP23XX_RV_ADC_FCS_THRESH_SHIFT)
#define RP23XX_RV_ADC_FCS_LEVEL_SHIFT (16)
#define RP23XX_RV_ADC_FCS_LEVEL_MASK (0x000f << RP23XX_RV_ADC_FCS_LEVEL_SHIFT)
#define RP23XX_RV_ADC_FCS_OVER (1 << 11)
#define RP23XX_RV_ADC_FCS_UNDER (1 << 10)
#define RP23XX_RV_ADC_FCS_FULL (1 << 9)
#define RP23XX_RV_ADC_FCS_EMPTY (1 << 8)
#define RP23XX_RV_ADC_FCS_DREQ_EN (1 << 3)
#define RP23XX_RV_ADC_FCS_ERR (1 << 2)
#define RP23XX_RV_ADC_FCS_SHIFT (1 << 1)
#define RP23XX_RV_ADC_FCS_EN (1 << 0)
#define RP23XX_RV_ADC_FIFO_MASK (0x00008fff)
#define RP23XX_RV_ADC_FIFO_ERR (1 << 15)
#define RP23XX_RV_ADC_FIFO_VAL_MASK (0x00000fff)
#define RP23XX_RV_ADC_DIV_MASK (0x00ffffff)
#define RP23XX_RV_ADC_DIV_INT_MASK (0x00ffff00)
#define RP23XX_RV_ADC_DIV_FRAC_MASK (0x000000ff)
#define RP23XX_RV_ADC_INTR_FIFO (1 << 0)
#define RP23XX_RV_ADC_INTE_FIFO (1 << 0)
#define RP23XX_RV_ADC_INTF_FIFO (1 << 0)
#define RP23XX_RV_ADC_INTS_FIFO (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_ADC_H */

54
arch/risc-v/src/rp23xx-rv/hardware/rp23xx_bootram.h Normal file
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@@ -0,0 +1,54 @@
/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_bootram.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_BOOTRAM_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_BOOTRAM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_BOOTRAM_WRITE_ONCE_OFFSET(n) ((n) * 4 + 0x000800)
#define RP23XX_BOOTRAM_BOOTLOCK_STAT_OFFSET 0x00000808
#define RP23XX_BOOTRAM_BOOTLOCK_OFFSET(n) ((n) * 4 + 0x00080c)
/* Register definitions *****************************************************/
#define RP23XX_BOOTRAM_WRITE_ONCE(n) (RP23XX_BOOTRAM_BASE + RP23XX_BOOTRAM_WRITE_ONCE_OFFSET(n))
#define RP23XX_BOOTRAM_BOOTLOCK_STAT (RP23XX_BOOTRAM_BASE + RP23XX_BOOTRAM_BOOTLOCK_STAT_OFFSET)
#define RP23XX_BOOTRAM_BOOTLOCK(n) (RP23XX_BOOTRAM_BASE + RP23XX_BOOTRAM_BOOTLOCK_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_BOOTRAM_WRITE_ONCE_MASK 0xffffffff
#define RP23XX_BOOTRAM_BOOTLOCK_STAT_MASK 0x000000ff
#define RP23XX_BOOTRAM_BOOTLOCK_MASK 0xffffffff
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_BOOTRAM_H */

64
arch/risc-v/src/rp23xx-rv/hardware/rp23xx_busctrl.h Normal file
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@@ -0,0 +1,64 @@
/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_busctrl.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_BUSCTRL_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_BUSCTRL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_BUSCTRL_BUS_PRIORITY_OFFSET 0x00000000
#define RP23XX_BUSCTRL_BUS_PRIORITY_ACK_OFFSET 0x00000004
#define RP23XX_BUSCTRL_PERFCTR_EN_OFFSET 0x00000008
#define RP23XX_BUSCTRL_PERFCTR_OFFSET(n) ((n) * 8 + 0x00000c)
#define RP23XX_BUSCTRL_PERFSEL_OFFSET(n) ((n) * 8 + 0x000010)
/* Register definitions *****************************************************/
#define RP23XX_BUSCTRL_BUS_PRIORITY (RP23XX_BUSCTRL_BASE + RP23XX_BUSCTRL_BUS_PRIORITY_OFFSET)
#define RP23XX_BUSCTRL_BUS_PRIORITY_ACK (RP23XX_BUSCTRL_BASE + RP23XX_BUSCTRL_BUS_PRIORITY_ACK_OFFSET)
#define RP23XX_BUSCTRL_PERFCTR_EN (RP23XX_BUSCTRL_BASE + RP23XX_BUSCTRL_PERFCTR_EN_OFFSET)
#define RP23XX_BUSCTRL_PERFCTR(n) (RP23XX_BUSCTRL_BASE + RP23XX_BUSCTRL_PERFCTR_OFFSET(n))
#define RP23XX_BUSCTRL_PERFSEL(n) (RP23XX_BUSCTRL_BASE + RP23XX_BUSCTRL_PERFSEL_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_BUSCTRL_BUS_PRIORITY_MASK 0x00001111
#define RP23XX_BUSCTRL_BUS_PRIORITY_DMA_W (1 << 12)
#define RP23XX_BUSCTRL_BUS_PRIORITY_DMA_R (1 << 8)
#define RP23XX_BUSCTRL_BUS_PRIORITY_PROC1 (1 << 4)
#define RP23XX_BUSCTRL_BUS_PRIORITY_PROC0 (1 << 0)
#define RP23XX_BUSCTRL_BUS_PRIORITY_ACK (1 << 0)
#define RP23XX_BUSCTRL_PERFCTR_EN (1 << 0)
#define RP23XX_BUSCTRL_PERFCTR_MASK 0x00ffffff
#define RP23XX_BUSCTRL_PERFSEL_MASK 0x0000007f
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_BUSCTRL_H */

618
arch/risc-v/src/rp23xx-rv/hardware/rp23xx_clocks.h Normal file
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54
arch/risc-v/src/rp23xx-rv/hardware/rp23xx_coresight_trace.h Normal file
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@@ -0,0 +1,54 @@
/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_coresight_trace.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_CORESIGHT_TRACE_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_CORESIGHT_TRACE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_CORESIGHT_TRACE_CTRL_STATUS_OFFSET 0x00000000
#define RP23XX_CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET 0x00000004
/* Register definitions *****************************************************/
#define RP23XX_CORESIGHT_TRACE_CTRL_STATUS (RP23XX_CORESIGHT_TRACE_BASE + RP23XX_CORESIGHT_TRACE_CTRL_STATUS_OFFSET)
#define RP23XX_CORESIGHT_TRACE_TRACE_CAPTURE_FIFO (RP23XX_CORESIGHT_TRACE_BASE + RP23XX_CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_CORESIGHT_TRACE_CTRL_STATUS_MASK (0x00000003)
#define RP23XX_CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW (1 << 1)
#define RP23XX_CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH (1 << 0)
#define RP23XX_CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_MASK (0xffffffff)
#define RP23XX_CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_MASK (0xffffffff)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_CORESIGHT_TRACE_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_dma.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_DMA_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_DMA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_DMA_READ_ADDR_OFFSET 0x000000 /* DMA Read Address pointer */
#define RP23XX_DMA_WRITE_ADDR_OFFSET 0x000004 /* DMA Write Address pointer */
#define RP23XX_DMA_TRANS_COUNT_OFFSET 0x000008 /* DMA Transfer Count */
#define RP23XX_DMA_CTRL_TRIG_OFFSET 0x00000c /* DMA Control and Status */
#define RP23XX_DMA_AL1_CTRL_OFFSET 0x000010 /* Alias for CTRL register */
#define RP23XX_DMA_AL1_READ_ADDR_OFFSET 0x000014 /* Alias for READ_ADDR register */
#define RP23XX_DMA_AL1_WRITE_ADDR_OFFSET 0x000018 /* Alias for WRITE_ADDR register */
#define RP23XX_DMA_AL1_TRANS_COUNT_TRIG_OFFSET 0x00001c /* Alias for TRANS_COUNT register */
#define RP23XX_DMA_AL2_CTRL_OFFSET 0x000020 /* Alias for CTRL register */
#define RP23XX_DMA_AL2_TRANS_COUNT_OFFSET 0x000024 /* Alias for TRANS_COUNT register */
#define RP23XX_DMA_AL2_READ_ADDR_OFFSET 0x000028 /* Alias for READ_ADDR register */
#define RP23XX_DMA_AL2_WRITE_ADDR_TRIG_OFFSET 0x00002c /* Alias for WRITE_ADDR register */
#define RP23XX_DMA_AL3_CTRL_OFFSET 0x000030 /* Alias for CTRL register */
#define RP23XX_DMA_AL3_WRITE_ADDR_OFFSET 0x000034 /* Alias for WRITE_ADDR register */
#define RP23XX_DMA_AL3_TRANS_COUNT_OFFSET 0x000038 /* Alias for TRANS_COUNT register */
#define RP23XX_DMA_AL3_READ_ADDR_TRIG_OFFSET 0x00003c /* Alias for READ_ADDR register */
#define RP23XX_DMA_INTR_OFFSET 0x000400 /* Interrupt Status (raw) */
#define RP23XX_DMA_INTE0_OFFSET 0x000404 /* Interrupt Enables for IRQ 0 */
#define RP23XX_DMA_INTF0_OFFSET 0x000408 /* Force Interrupts */
#define RP23XX_DMA_INTS0_OFFSET 0x00040c /* Interrupt Status for IRQ 0 */
#define RP23XX_DMA_INTE1_OFFSET 0x000414 /* Interrupt Enables for IRQ 1 */
#define RP23XX_DMA_INTF1_OFFSET 0x000418 /* Force Interrupts for IRQ 1 */
#define RP23XX_DMA_INTS1_OFFSET 0x00041c /* Interrupt Status (masked) for IRQ 1 */
#define RP23XX_DMA_INTE2_OFFSET 0x000424 /* Interrupt Enables for IRQ 1 */
#define RP23XX_DMA_INTF2_OFFSET 0x000428 /* Force Interrupts for IRQ 1 */
#define RP23XX_DMA_INTS2_OFFSET 0x00042c /* Interrupt Status (masked) for IRQ 1 */
#define RP23XX_DMA_INTE3_OFFSET 0x000434 /* Interrupt Enables for IRQ 1 */
#define RP23XX_DMA_INTF3_OFFSET 0x000438 /* Force Interrupts for IRQ 1 */
#define RP23XX_DMA_INTS3_OFFSET 0x00043c /* Interrupt Status (masked) for IRQ 1 */
#define RP23XX_DMA_TIMER0_OFFSET 0x000440 /* Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. */
#define RP23XX_DMA_TIMER1_OFFSET 0x000444 /* Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. */
#define RP23XX_DMA_TIMER2_OFFSET 0x000448 /* Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. */
#define RP23XX_DMA_TIMER3_OFFSET 0x00044c /* Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. */
#define RP23XX_DMA_MULTI_CHAN_TRIGGER_OFFSET 0x000450 /* Trigger one or more channels simultaneously */
#define RP23XX_DMA_SNIFF_CTRL_OFFSET 0x000454 /* Sniffer Control */
#define RP23XX_DMA_SNIFF_DATA_OFFSET 0x000458 /* Data accumulator for sniff hardware Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. */
#define RP23XX_DMA_FIFO_LEVELS_OFFSET 0x000460 /* Debug RAF, WAF, TDF levels */
#define RP23XX_DMA_CHAN_ABORT_OFFSET 0x000464 /* Abort an in-progress transfer sequence on one or more channels */
#define RP23XX_DMA_N_CHANNELS_OFFSET 0x000468 /* The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. */
#define RP23XX_DMA_SECCFG_OFFSET(n) (0x000480 + (n) * 0x0004)
#define RP23XX_DMA_DBG_SECCFG_IRQ_OFFSET(n) (0x0004c4 + (n) * 0x0004)
#define RP23XX_DMA_SECCFG_MISC_OFFSET 0x0004d0
#define RP23XX_DMA_DBG_CTDREQ_OFFSET(n) (0x000800 + (n) * 0x0040)
#define RP23XX_DMA_DBG_TCR_OFFSET(n) (0x000804 + (n) * 0x0040)
#define RP23XX_DMA_MPU_CTRL_OFFSET 0x000500
#define RP23XX_DMA_MPU_BAR_OFFSET(n) (0x000504 + (n) * 0x0008)
#define RP23XX_DMA_MPU_LAR_OFFSET(n) (0x000508 + (n) * 0x0008)
/* Register definitions *****************************************************/
#define RP23XX_DMA_CH(n) (RP23XX_DMA_BASE + (0x0040 * (n)))
#define RP23XX_DMA_READ_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_READ_ADDR_OFFSET)
#define RP23XX_DMA_WRITE_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_WRITE_ADDR_OFFSET)
#define RP23XX_DMA_TRANS_COUNT(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_TRANS_COUNT_OFFSET)
#define RP23XX_DMA_CTRL_TRIG(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_CTRL_TRIG_OFFSET)
#define RP23XX_DMA_AL1_CTRL(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL1_CTRL_OFFSET)
#define RP23XX_DMA_AL1_READ_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL1_READ_ADDR_OFFSET)
#define RP23XX_DMA_AL1_WRITE_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL1_WRITE_ADDR_OFFSET)
#define RP23XX_DMA_AL1_TRANS_COUNT_TRIG(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL1_TRANS_COUNT_TRIG_OFFSET)
#define RP23XX_DMA_AL2_CTRL(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL2_CTRL_OFFSET)
#define RP23XX_DMA_AL2_TRANS_COUNT(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL2_TRANS_COUNT_OFFSET)
#define RP23XX_DMA_AL2_READ_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL2_READ_ADDR_OFFSET)
#define RP23XX_DMA_AL2_WRITE_ADDR_TRIG(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL2_WRITE_ADDR_TRIG_OFFSET)
#define RP23XX_DMA_AL3_CTRL(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL3_CTRL_OFFSET)
#define RP23XX_DMA_AL3_WRITE_ADDR(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL3_WRITE_ADDR_OFFSET)
#define RP23XX_DMA_AL3_TRANS_COUNT(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL3_TRANS_COUNT_OFFSET)
#define RP23XX_DMA_AL3_READ_ADDR_TRIG(n) (RP23XX_DMA_CH(n) + RP23XX_DMA_AL3_READ_ADDR_TRIG_OFFSET)
#define RP23XX_DMA_INTR (RP23XX_DMA_BASE + RP23XX_DMA_INTR_OFFSET)
#define RP23XX_DMA_INTE0 (RP23XX_DMA_BASE + RP23XX_DMA_INTE0_OFFSET)
#define RP23XX_DMA_INTF0 (RP23XX_DMA_BASE + RP23XX_DMA_INTF0_OFFSET)
#define RP23XX_DMA_INTS0 (RP23XX_DMA_BASE + RP23XX_DMA_INTS0_OFFSET)
#define RP23XX_DMA_INTE1 (RP23XX_DMA_BASE + RP23XX_DMA_INTE1_OFFSET)
#define RP23XX_DMA_INTF1 (RP23XX_DMA_BASE + RP23XX_DMA_INTF1_OFFSET)
#define RP23XX_DMA_INTS1 (RP23XX_DMA_BASE + RP23XX_DMA_INTS1_OFFSET)
#define RP23XX_DMA_INTE2 (RP23XX_DMA_BASE + RP23XX_DMA_INTE2_OFFSET)
#define RP23XX_DMA_INTF2 (RP23XX_DMA_BASE + RP23XX_DMA_INTF2_OFFSET)
#define RP23XX_DMA_INTS2 (RP23XX_DMA_BASE + RP23XX_DMA_INTS2_OFFSET)
#define RP23XX_DMA_INTE3 (RP23XX_DMA_BASE + RP23XX_DMA_INTE3_OFFSET)
#define RP23XX_DMA_INTF3 (RP23XX_DMA_BASE + RP23XX_DMA_INTF3_OFFSET)
#define RP23XX_DMA_INTS3 (RP23XX_DMA_BASE + RP23XX_DMA_INTS3_OFFSET)
#define RP23XX_DMA_TIMER0 (RP23XX_DMA_BASE + RP23XX_DMA_TIMER0_OFFSET)
#define RP23XX_DMA_TIMER1 (RP23XX_DMA_BASE + RP23XX_DMA_TIMER1_OFFSET)
#define RP23XX_DMA_TIMER2 (RP23XX_DMA_BASE + RP23XX_DMA_TIMER2_OFFSET)
#define RP23XX_DMA_TIMER3 (RP23XX_DMA_BASE + RP23XX_DMA_TIMER3_OFFSET)
#define RP23XX_DMA_MULTI_CHAN_TRIGGER (RP23XX_DMA_BASE + RP23XX_DMA_MULTI_CHAN_TRIGGER_OFFSET)
#define RP23XX_DMA_SNIFF_CTRL (RP23XX_DMA_BASE + RP23XX_DMA_SNIFF_CTRL_OFFSET)
#define RP23XX_DMA_SNIFF_DATA (RP23XX_DMA_BASE + RP23XX_DMA_SNIFF_DATA_OFFSET)
#define RP23XX_DMA_FIFO_LEVELS (RP23XX_DMA_BASE + RP23XX_DMA_FIFO_LEVELS_OFFSET)
#define RP23XX_DMA_CHAN_ABORT (RP23XX_DMA_BASE + RP23XX_DMA_CHAN_ABORT_OFFSET)
#define RP23XX_DMA_N_CHANNELS (RP23XX_DMA_BASE + RP23XX_DMA_N_CHANNELS_OFFSET)
#define RP23XX_DMA_SECCFG(n) (RP23XX_DMA_BASE + RP23XX_DMA_SECCFG_OFFSET(n))
#define RP23XX_DMA_SECCFG_IRQ(n) (RP23XX_DMA_BASE + RP23XX_DMA_SECCFG_IRQ_OFFSET(n))
#define RP23XX_DMA_SECCFG_MISC (RP23XX_DMA_BASE + RP23XX_DMA_SECCFG_MISC_OFFSET)
#define RP23XX_DMA_DBG_CTDREQ(n) (RP23XX_DMA_BASE + RP23XX_DMA_DBG_CTDREQ_OFFSET(n))
#define RP23XX_DMA_DBG_TCR(n) (RP23XX_DMA_BASE + RP23XX_DMA_DBG_TCR_OFFSET(n))
#define RP23XX_DMA_MPU_CTRL (RP23XX_DMA_BASE + RP23XX_DMA_MPU_CTRL_OFFSET)
#define RP23XX_DMA_MPU_BAR(n) (RP23XX_DMA_BASE + RP23XX_DMA_MPU_BAR_OFFSET(n))
#define RP23XX_DMA_MPU_LAR(n) (RP23XX_DMA_BASE + RP23XX_DMA_MPU_LAR_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_DMA_CTRL_TRIG_AHB_ERROR (1 << 31) /* Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. */
#define RP23XX_DMA_CTRL_TRIG_READ_ERROR (1 << 30) /* If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later) */
#define RP23XX_DMA_CTRL_TRIG_WRITE_ERROR (1 << 29) /* If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later) */
#define RP23XX_DMA_CTRL_TRIG_BUSY (1 << 26) /* This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. */
#define RP23XX_DMA_CTRL_TRIG_SNIFF_EN (1 << 25) /* If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. */
#define RP23XX_DMA_CTRL_TRIG_BSWAP (1 << 24) /* Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. */
#define RP23XX_DMA_CTRL_TRIG_IRQ_QUIET (1 << 23) /* In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT (17) /* Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_MASK (0x3f << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_TIMER0 (0x3b << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) /* Select Timer 0 as TREQ */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_TIMER1 (0x3c << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) /* Select Timer 1 as TREQ */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_TIMER2 (0x3d << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) /* Select Timer 2 as TREQ (Optional) */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_TIMER3 (0x3e << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) /* Select Timer 3 as TREQ (Optional) */
#define RP23XX_DMA_CTRL_TRIG_TREQ_SEL_PERMANENT (0x3f << RP23XX_DMA_CTRL_TRIG_TREQ_SEL_SHIFT) /* Permanent request, for unpaced transfers. */
#define RP23XX_DMA_CTRL_TRIG_CHAIN_TO_SHIFT (13) /* When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is equal to channel number (0). */
#define RP23XX_DMA_CTRL_TRIG_CHAIN_TO_MASK (0x0f << RP23XX_DMA_CTRL_TRIG_CHAIN_TO_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_RING_SEL (1 << 12) /* Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. */
#define RP23XX_DMA_CTRL_TRIG_RING_SIZE_SHIFT (8) /* Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. */
#define RP23XX_DMA_CTRL_TRIG_RING_SIZE_MASK (0x0f << RP23XX_DMA_CTRL_TRIG_RING_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_RING_SIZE_RING_NONE (0x0 << RP23XX_DMA_CTRL_TRIG_RING_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_INCR_WRITE_REV (1 << 7) /* If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.*/
#define RP23XX_DMA_CTRL_TRIG_INCR_WRITE (1 << 6) /* If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. */
#define RP23XX_DMA_CTRL_TRIG_INCR_READ_REV (1 << 5) /* If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. */
#define RP23XX_DMA_CTRL_TRIG_INCR_READ (1 << 4) /* If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. */
#define RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT (2) /* Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. */
#define RP23XX_DMA_CTRL_TRIG_DATA_SIZE_MASK (0x03 << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SIZE_BYTE (0x0 << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SIZE_HALFWORD (0x1 << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SIZE_WORD (0x2 << RP23XX_DMA_CTRL_TRIG_DATA_SIZE_SHIFT)
#define RP23XX_DMA_CTRL_TRIG_HIGH_PRIORITY (1 << 1) /* HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. */
#define RP23XX_DMA_CTRL_TRIG_EN (1 << 0) /* DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) */
#define RP23XX_DMA_INTR_MASK (0xffff) /* Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. */
#define RP23XX_DMA_INTE0_MASK (0xffff) /* Set bit n to pass interrupts from channel n to DMA IRQ 0. */
#define RP23XX_DMA_INTF0_MASK (0xffff) /* Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. */
#define RP23XX_DMA_INTS0_MASK (0xffff) /* Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here. */
#define RP23XX_DMA_INTE1_MASK (0xffff) /* Set bit n to pass interrupts from channel n to DMA IRQ 1. */
#define RP23XX_DMA_INTF1_MASK (0xffff) /* Write 1s to force the corresponding bits in INTE1. The interrupt remains asserted until INTF0 is cleared. */
#define RP23XX_DMA_INTS1_MASK (0xffff) /* Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here. */
#define RP23XX_DMA_INTE2_MASK (0xffff) /* Set bit n to pass interrupts from channel n to DMA IRQ 2. */
#define RP23XX_DMA_INTF2_MASK (0xffff) /* Write 1s to force the corresponding bits in INTE2. The interrupt remains asserted until INTF0 is cleared. */
#define RP23XX_DMA_INTS2_MASK (0xffff) /* Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. Channel interrupts can be cleared by writing a bit mask here. */
#define RP23XX_DMA_INTE3_MASK (0xffff) /* Set bit n to pass interrupts from channel n to DMA IRQ 3. */
#define RP23XX_DMA_INTF3_MASK (0xffff) /* Write 1s to force the corresponding bits in INTE3. The interrupt remains asserted until INTF0 is cleared. */
#define RP23XX_DMA_INTS3_MASK (0xffff) /* Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. Channel interrupts can be cleared by writing a bit mask here. */
#define RP23XX_DMA_TIMER0_X_SHIFT (16) /* Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER0_X_MASK (0xffff << RP23XX_DMA_TIMER0_X_SHIFT)
#define RP23XX_DMA_TIMER0_Y_MASK (0xffff) /* Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER1_X_SHIFT (16) /* Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER1_X_MASK (0xffff << RP23XX_DMA_TIMER1_X_SHIFT)
#define RP23XX_DMA_TIMER1_Y_MASK (0xffff) /* Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER2_X_SHIFT (16) /* Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER2_X_MASK (0xffff << RP23XX_DMA_TIMER2_X_SHIFT)
#define RP23XX_DMA_TIMER2_Y_MASK (0xffff) /* Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER3_X_SHIFT (16) /* Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. */
#define RP23XX_DMA_TIMER3_X_MASK (0xffff << RP23XX_DMA_TIMER3_X_SHIFT)
#define RP23XX_DMA_TIMER3_Y_MASK (0xffff) /* Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. */
#define RP23XX_DMA_MULTI_CHAN_TRIGGER_MASK (0xffff) /* Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. */
#define RP23XX_DMA_SNIFF_CTRL_OUT_INV (1 << 11) /* If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. */
#define RP23XX_DMA_SNIFF_CTRL_OUT_REV (1 << 10) /* If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. */
#define RP23XX_DMA_SNIFF_CTRL_BSWAP (1 << 9) /* Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. */
#define RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT (5)
#define RP23XX_DMA_SNIFF_CTRL_CALC_MASK (0x0f << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT)
#define RP23XX_DMA_SNIFF_CTRL_CALC_CRC32 (0x0 << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* Calculate a CRC-32 (IEEE802.3 polynomial) */
#define RP23XX_DMA_SNIFF_CTRL_CALC_CRC32R (0x1 << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data */
#define RP23XX_DMA_SNIFF_CTRL_CALC_CRC16 (0x2 << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* Calculate a CRC-16-CCITT */
#define RP23XX_DMA_SNIFF_CTRL_CALC_CRC16R (0x3 << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* Calculate a CRC-16-CCITT with bit reversed data */
#define RP23XX_DMA_SNIFF_CTRL_CALC_EVEN (0xe << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* XOR reduction over all data. == 1 if the total 1 population count is odd. */
#define RP23XX_DMA_SNIFF_CTRL_CALC_SUM (0xf << RP23XX_DMA_SNIFF_CTRL_CALC_SHIFT) /* Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) */
#define RP23XX_DMA_SNIFF_CTRL_DMACH_SHIFT (1) /* DMA channel for Sniffer to observe */
#define RP23XX_DMA_SNIFF_CTRL_DMACH_MASK (0x0f << RP23XX_DMA_SNIFF_CTRL_DMACH_SHIFT)
#define RP23XX_DMA_SNIFF_CTRL_EN (1 << 0) /* Enable sniffer */
#define RP23XX_DMA_FIFO_LEVELS_RAF_LVL_SHIFT (16) /* Current Read-Address-FIFO fill level */
#define RP23XX_DMA_FIFO_LEVELS_RAF_LVL_MASK (0xff << RP23XX_DMA_FIFO_LEVELS_RAF_LVL_SHIFT)
#define RP23XX_DMA_FIFO_LEVELS_WAF_LVL_SHIFT (8) /* Current Write-Address-FIFO fill level */
#define RP23XX_DMA_FIFO_LEVELS_WAF_LVL_MASK (0xff << RP23XX_DMA_FIFO_LEVELS_WAF_LVL_SHIFT)
#define RP23XX_DMA_FIFO_LEVELS_TDF_LVL_MASK (0xff) /* Current Transfer-Data-FIFO fill level */
#define RP23XX_DMA_CHAN_ABORT_MASK (0xffff) /* Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. */
#define RP23XX_DMA_N_CHANNELS_MASK (0x1f)
#define RP23XX_DMA_SECCFG_MASK (0x00000007)
#define RP23XX_DMA_SECCFG_LOCK (1 << 2) /* LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel’s control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. */
#define RP23XX_DMA_SECCFG_S (1 << 1) /* Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. */
#define RP23XX_DMA_SECCFG_P (1 << 0) /* Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. */
#define RP23XX_DMA_SECCFG_IRQ_MASK (0x00000003)
#define RP23XX_DMA_SECCFG_IRQ_S (1 << 1) /* Secure IRQ. If 1, this IRQ’s control registers can only be accessed from a Secure context. If 0, this IRQ’s control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ’s registers can not be used to acknowledge the channel interrupts of Secure channels. */
#define RP23XX_DMA_SECCFG_IRQ_P (1 << 0) /* Privileged IRQ. If 1, this IRQ’s control registers can only be accessed from a Privileged context. If 0, this IRQ’s control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ’s registers can not be used to acknowledge the channel interrupts of Privileged channels. */
#define RP23XX_DMA_SECCFG_MISC_MASK (0x000003ff)
#define RP23XX_DMA_SECCFG_MISC_TIMER3_S (1 << 9) /* If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels. */
#define RP23XX_DMA_SECCFG_MISC_TIMER3_S (1 << 9)
#define RP23XX_DMA_DBG_CTDREQ_MASK (0x3f)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_DMA_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_dreq.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_dreq.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_DREQ_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_DREQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define RP23XX_DMA_DREQ_PIO0_TX0 0
#define RP23XX_DMA_DREQ_PIO0_TX1 1
#define RP23XX_DMA_DREQ_PIO0_TX2 2
#define RP23XX_DMA_DREQ_PIO0_TX3 3
#define RP23XX_DMA_DREQ_PIO0_RX0 4
#define RP23XX_DMA_DREQ_PIO0_RX1 5
#define RP23XX_DMA_DREQ_PIO0_RX2 6
#define RP23XX_DMA_DREQ_PIO0_RX3 7
#define RP23XX_DMA_DREQ_PIO1_TX0 8
#define RP23XX_DMA_DREQ_PIO1_TX1 9
#define RP23XX_DMA_DREQ_PIO1_TX2 10
#define RP23XX_DMA_DREQ_PIO1_TX3 11
#define RP23XX_DMA_DREQ_PIO1_RX0 12
#define RP23XX_DMA_DREQ_PIO1_RX1 13
#define RP23XX_DMA_DREQ_PIO1_RX2 14
#define RP23XX_DMA_DREQ_PIO1_RX3 15
#define RP23XX_DMA_DREQ_PIO2_TX0 16
#define RP23XX_DMA_DREQ_PIO2_TX1 17
#define RP23XX_DMA_DREQ_PIO2_TX2 18
#define RP23XX_DMA_DREQ_PIO2_TX3 19
#define RP23XX_DMA_DREQ_PIO2_RX0 20
#define RP23XX_DMA_DREQ_PIO2_RX1 21
#define RP23XX_DMA_DREQ_PIO2_RX2 22
#define RP23XX_DMA_DREQ_PIO2_RX3 23
#define RP23XX_DMA_DREQ_SPI0_TX 24
#define RP23XX_DMA_DREQ_SPI0_RX 25
#define RP23XX_DMA_DREQ_SPI1_TX 26
#define RP23XX_DMA_DREQ_SPI1_RX 27
#define RP23XX_DMA_DREQ_UART0_TX 28
#define RP23XX_DMA_DREQ_UART0_RX 29
#define RP23XX_DMA_DREQ_UART1_TX 30
#define RP23XX_DMA_DREQ_UART1_RX 31
#define RP23XX_DMA_DREQ_PWM_WRAP0 32
#define RP23XX_DMA_DREQ_PWM_WRAP1 33
#define RP23XX_DMA_DREQ_PWM_WRAP2 34
#define RP23XX_DMA_DREQ_PWM_WRAP3 35
#define RP23XX_DMA_DREQ_PWM_WRAP4 36
#define RP23XX_DMA_DREQ_PWM_WRAP5 37
#define RP23XX_DMA_DREQ_PWM_WRAP6 38
#define RP23XX_DMA_DREQ_PWM_WRAP7 39
#define RP23XX_DMA_DREQ_PWM_WRAP8 40
#define RP23XX_DMA_DREQ_PWM_WRAP9 41
#define RP23XX_DMA_DREQ_PWM_WRAP10 42
#define RP23XX_DMA_DREQ_PWM_WRAP11 43
#define RP23XX_DMA_DREQ_I2C0_TX 44
#define RP23XX_DMA_DREQ_I2C0_RX 45
#define RP23XX_DMA_DREQ_I2C1_TX 46
#define RP23XX_DMA_DREQ_I2C1_RX 47
#define RP23XX_DMA_DREQ_ADC 48
#define RP23XX_DMA_DREQ_XIP_STREAM 49
#define RP23XX_DMA_DREQ_XIP_QMITX 50
#define RP23XX_DMA_DREQ_XIP_QMIRX 51
#define RP23XX_DMA_DREQ_HSTX 52
#define RP23XX_DMA_DREQ_CORESIGHT 53
#define RP23XX_DMA_DREQ_SHA256 54
#define RP23XX_DMA_DREQ_DMA_TIMER0 59
#define RP23XX_DMA_DREQ_DMA_TIMER1 60
#define RP23XX_DMA_DREQ_DMA_TIMER2 61
#define RP23XX_DMA_DREQ_DMA_TIMER3 62
#define RP23XX_DMA_DREQ_FORCE 63
#define RP23XX_DMA_DREQ_COUNT 64
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_DREQ_H */

76
arch/risc-v/src/rp23xx-rv/hardware/rp23xx_glitch_detector.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_glitch_detector.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_GLITCH_DETECTOR_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_GLITCH_DETECTOR_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_GLITCH_DETECTOR_ARM_OFFSET 0x00000000
#define RP23XX_GLITCH_DETECTOR_DISARM_OFFSET 0x00000004
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_OFFSET 0x00000008
#define RP23XX_GLITCH_DETECTOR_LOCK_OFFSET 0x0000000c
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_OFFSET 0x00000010
#define RP23XX_GLITCH_DETECTOR_TRIG_FORCE_OFFSET 0x00000014
/* Register definitions *****************************************************/
#define RP23XX_GLITCH_DETECTOR_ARM (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_ARM_OFFSET)
#define RP23XX_GLITCH_DETECTOR_DISARM (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_DISARM_OFFSET)
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_SENSITIVITY_OFFSET)
#define RP23XX_GLITCH_DETECTOR_LOCK (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_LOCK_OFFSET)
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_TRIG_STATUS_OFFSET)
#define RP23XX_GLITCH_DETECTOR_TRIG_FORCE (RP23XX_GLITCH_DETECTOR_BASE + RP23XX_GLITCH_DETECTOR_TRIG_FORCE_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_GLITCH_DETECTOR_ARM_MASK 0x0000ffff
#define RP23XX_GLITCH_DETECTOR_DISARM_MASK 0x0000ffff
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_MASK 0xff00ffff
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DEFAULT_MASK 0xff000000
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET3_INV_MASK 0x0000c000
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET2_INV_MASK 0x00003000
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET1_INV_MASK 0x00000c00
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET0_INV_MASK 0x00000300
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET3_MASK 0x000000c0
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET2_MASK 0x00000030
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET1_MASK 0x0000000c
#define RP23XX_GLITCH_DETECTOR_SENSITIVITY_DET0_MASK 0x00000003
#define RP23XX_GLITCH_DETECTOR_LOCK_MASK 0x000000ff
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_MASK 0x0000000f
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_DET3_MASK 0x00000008
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_DET2_MASK 0x00000004
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_DET1_MASK 0x00000002
#define RP23XX_GLITCH_DETECTOR_TRIG_STATUS_DET0_MASK 0x00000001
#define RP23XX_GLITCH_DETECTOR_TRIG_FORCE_MASK 0x0000000f
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_GLITCH_DETECTOR_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hazard3.h Normal file
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79
arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hstx_ctrl.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hstx_ctrl.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_HSTX_CTRL_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_HSTX_CTRL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_HSTX_CTRL_CSR_OFFSET 0x00000000
#define RP23XX_HSTX_CTRL_BIT_OFFSET(n) ((n) * 4 + 0x000004)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_OFFSET 0x00000024
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_OFFSET 0x00000028
/* Register definitions *****************************************************/
#define RP23XX_HSTX_CTRL_CSR (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_CSR_OFFSET)
#define RP23XX_HSTX_CTRL_BIT(n) (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_BIT_OFFSET(n))
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_EXPAND_SHIFT_OFFSET)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS (RP23XX_HSTX_CTRL_BASE + RP23XX_HSTX_CTRL_EXPAND_TMDS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_HSTX_CTRL_CSR_MASK (0xff1f1f73)
#define RP23XX_HSTX_CTRL_CSR_CLKDIV_MASK (0xf0000000)
#define RP23XX_HSTX_CTRL_CSR_CLKPHASE_MASK (0x0f000000)
#define RP23XX_HSTX_CTRL_CSR_N_SHIFTS_MASK (0x001f0000)
#define RP23XX_HSTX_CTRL_CSR_SHIFT_MASK (0x00001f00)
#define RP23XX_HSTX_CTRL_CSR_COUPLED_SEL_MASK (0x00000060)
#define RP23XX_HSTX_CTRL_CSR_COUPLED_MODE (1 << 4)
#define RP23XX_HSTX_CTRL_CSR_EXPAND_EN (1 << 1)
#define RP23XX_HSTX_CTRL_CSR_EN (1 << 0)
#define RP23XX_HSTX_CTRL_BIT_MASK (0x00031f1f)
#define RP23XX_HSTX_CTRL_BIT_CLK_MASK (1 << 25)
#define RP23XX_HSTX_CTRL_BIT_INV_MASK (1 << 24)
#define RP23XX_HSTX_CTRL_BIT_SEL_N_MASK (0x00001f00)
#define RP23XX_HSTX_CTRL_BIT_SEL_P_MASK (0x0000001f)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_MASK (0x1f1f1f1f)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_MASK (0x1f000000)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_MASK (0x001f0000)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_MASK (0x00001f00)
#define RP23XX_HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_MASK (0x0000001f)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_MASK (0x00ffffff)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L2_NBITS_MASK (0x00e00000)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L2_ROT_MASK (0x001f0000)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L1_NBITS_MASK (0x0000e000)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L1_ROT_MASK (0x00001f00)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L0_NBITS_MASK (0x000000e0)
#define RP23XX_HSTX_CTRL_EXPAND_TMDS_L0_ROT_MASK (0x0000001f)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_HSTX_CTRL_H */

55
arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hstx_fifo.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hstx_fifo.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_HSTX_FIFO_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_HSTX_FIFO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_HSTX_FIFO_STAT_OFFSET 0x00000000
#define RP23XX_HSTX_FIFO_FIFO_OFFSET 0x00000004
/* Register definitions *****************************************************/
#define RP23XX_HSTX_FIFO_STAT (RP23XX_HSTX_FIFO_BASE + RP23XX_HSTX_FIFO_STAT_OFFSET)
#define RP23XX_HSTX_FIFO_FIFO (RP23XX_HSTX_FIFO_BASE + RP23XX_HSTX_FIFO_FIFO_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_HSTX_FIFO_STAT_MASK (0x000007ff)
#define RP23XX_HSTX_FIFO_STAT_WOF (1 << 10)
#define RP23XX_HSTX_FIFO_STAT_EMPTY (1 << 9)
#define RP23XX_HSTX_FIFO_STAT_FULL (1 << 8)
#define RP23XX_HSTX_FIFO_STAT_LEVEL_MASK (0x000000ff)
#define RP23XX_HSTX_FIFO_FIFO_MASK (0xffffffff)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_HSTX_FIFO_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_i2c.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_i2c.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_I2C_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_I2C_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_RV_I2C_IC_CON_OFFSET 0x000000 /* I2C Control Register */
#define RP23XX_RV_I2C_IC_TAR_OFFSET 0x000004 /* I2C Target Address Register */
#define RP23XX_RV_I2C_IC_SAR_OFFSET 0x000008 /* I2C Slave Address Register */
#define RP23XX_RV_I2C_IC_DATA_CMD_OFFSET 0x000010 /* I2C Rx/Tx Data Buffer and Command Register */
#define RP23XX_RV_I2C_IC_SS_SCL_HCNT_OFFSET 0x000014 /* Standard Speed I2C Clock SCL High Count Register */
#define RP23XX_RV_I2C_IC_SS_SCL_LCNT_OFFSET 0x000018 /* Standard Speed I2C Clock SCL Low Count Register */
#define RP23XX_RV_I2C_IC_FS_SCL_HCNT_OFFSET 0x00001c /* Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register */
#define RP23XX_RV_I2C_IC_FS_SCL_LCNT_OFFSET 0x000020 /* Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register */
#define RP23XX_RV_I2C_IC_INTR_STAT_OFFSET 0x00002c /* I2C Interrupt Status Register */
#define RP23XX_RV_I2C_IC_INTR_MASK_OFFSET 0x000030 /* I2C Interrupt Mask Register */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_OFFSET 0x000034 /* I2C Raw Interrupt Status Register */
#define RP23XX_RV_I2C_IC_RX_TL_OFFSET 0x000038 /* I2C Receive FIFO Threshold Register */
#define RP23XX_RV_I2C_IC_TX_TL_OFFSET 0x00003c /* I2C Transmit FIFO Threshold Register */
#define RP23XX_RV_I2C_IC_CLR_INTR_OFFSET 0x000040 /* Clear Combined and Individual Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_RX_UNDER_OFFSET 0x000044 /* Clear RX_UNDER Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_RX_OVER_OFFSET 0x000048 /* Clear RX_OVER Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_TX_OVER_OFFSET 0x00004c /* Clear TX_OVER Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_RD_REQ_OFFSET 0x000050 /* Clear RD_REQ Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_TX_ABRT_OFFSET 0x000054 /* Clear TX_ABRT Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_RX_DONE_OFFSET 0x000058 /* Clear RX_DONE Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_ACTIVITY_OFFSET 0x00005c /* Clear ACTIVITY Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_STOP_DET_OFFSET 0x000060 /* Clear STOP_DET Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_START_DET_OFFSET 0x000064 /* Clear START_DET Interrupt Register */
#define RP23XX_RV_I2C_IC_CLR_GEN_CALL_OFFSET 0x000068 /* Clear GEN_CALL Interrupt Register */
#define RP23XX_RV_I2C_IC_ENABLE_OFFSET 0x00006c /* I2C Enable Register */
#define RP23XX_RV_I2C_IC_STATUS_OFFSET 0x000070 /* I2C Status Register */
#define RP23XX_RV_I2C_IC_TXFLR_OFFSET 0x000074 /* I2C Transmit FIFO Level Register */
#define RP23XX_RV_I2C_IC_RXFLR_OFFSET 0x000078 /* I2C Receive FIFO Level Register */
#define RP23XX_RV_I2C_IC_SDA_HOLD_OFFSET 0x00007c /* I2C SDA Hold Time Length Register */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_OFFSET 0x000080 /* I2C Transmit Abort Source Register */
#define RP23XX_RV_I2C_IC_SLV_DATA_NACK_ONLY_OFFSET 0x000084 /* Generate Slave Data NACK Register */
#define RP23XX_RV_I2C_IC_DMA_CR_OFFSET 0x000088 /* DMA Control Register */
#define RP23XX_RV_I2C_IC_DMA_TDLR_OFFSET 0x00008c /* DMA Transmit Data Level Register */
#define RP23XX_RV_I2C_IC_DMA_RDLR_OFFSET 0x000090 /* I2C Receive Data Level Register */
#define RP23XX_RV_I2C_IC_SDA_SETUP_OFFSET 0x000094 /* I2C SDA Setup Register */
#define RP23XX_RV_I2C_IC_ACK_GENERAL_CALL_OFFSET 0x000098 /* I2C ACK General Call Register */
#define RP23XX_RV_I2C_IC_ENABLE_STATUS_OFFSET 0x00009c /* I2C Enable Status Register */
#define RP23XX_RV_I2C_IC_FS_SPKLEN_OFFSET 0x0000a0 /* I2C SS, FS or FM+ spike suppression limit */
#define RP23XX_RV_I2C_IC_CLR_RESTART_DET_OFFSET 0x0000a8 /* Clear RESTART_DET Interrupt Register */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_OFFSET 0x0000f4 /* Component Parameter Register 1 */
#define RP23XX_RV_I2C_IC_COMP_VERSION_OFFSET 0x0000f8 /* I2C Component Version Register */
#define RP23XX_RV_I2C_IC_COMP_TYPE_OFFSET 0x0000fc /* I2C Component Type Register */
/* Register definitions *****************************************************/
#define RP23XX_RV_I2C_IC_CON(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CON_OFFSET)
#define RP23XX_RV_I2C_IC_TAR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_TAR_OFFSET)
#define RP23XX_RV_I2C_IC_SAR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_SAR_OFFSET)
#define RP23XX_RV_I2C_IC_DATA_CMD(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_DATA_CMD_OFFSET)
#define RP23XX_RV_I2C_IC_SS_SCL_HCNT(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_SS_SCL_HCNT_OFFSET)
#define RP23XX_RV_I2C_IC_SS_SCL_LCNT(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_SS_SCL_LCNT_OFFSET)
#define RP23XX_RV_I2C_IC_FS_SCL_HCNT(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_FS_SCL_HCNT_OFFSET)
#define RP23XX_RV_I2C_IC_FS_SCL_LCNT(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_FS_SCL_LCNT_OFFSET)
#define RP23XX_RV_I2C_IC_INTR_STAT(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_INTR_STAT_OFFSET)
#define RP23XX_RV_I2C_IC_INTR_MASK(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_INTR_MASK_OFFSET)
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_RAW_INTR_STAT_OFFSET)
#define RP23XX_RV_I2C_IC_RX_TL(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_RX_TL_OFFSET)
#define RP23XX_RV_I2C_IC_TX_TL(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_TX_TL_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_INTR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_INTR_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_RX_UNDER(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_RX_UNDER_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_RX_OVER(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_RX_OVER_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_TX_OVER(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_TX_OVER_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_RD_REQ(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_RD_REQ_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_TX_ABRT(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_TX_ABRT_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_RX_DONE(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_RX_DONE_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_ACTIVITY(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_ACTIVITY_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_STOP_DET(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_STOP_DET_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_START_DET(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_START_DET_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_GEN_CALL(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_GEN_CALL_OFFSET)
#define RP23XX_RV_I2C_IC_ENABLE(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_ENABLE_OFFSET)
#define RP23XX_RV_I2C_IC_STATUS(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_STATUS_OFFSET)
#define RP23XX_RV_I2C_IC_TXFLR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_TXFLR_OFFSET)
#define RP23XX_RV_I2C_IC_RXFLR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_RXFLR_OFFSET)
#define RP23XX_RV_I2C_IC_SDA_HOLD(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_SDA_HOLD_OFFSET)
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_OFFSET)
#define RP23XX_RV_I2C_IC_SLV_DATA_NACK_ONLY(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_SLV_DATA_NACK_ONLY_OFFSET)
#define RP23XX_RV_I2C_IC_DMA_CR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_DMA_CR_OFFSET)
#define RP23XX_RV_I2C_IC_DMA_TDLR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_DMA_TDLR_OFFSET)
#define RP23XX_RV_I2C_IC_DMA_RDLR(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_DMA_RDLR_OFFSET)
#define RP23XX_RV_I2C_IC_SDA_SETUP(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_SDA_SETUP_OFFSET)
#define RP23XX_RV_I2C_IC_ACK_GENERAL_CALL(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_ACK_GENERAL_CALL_OFFSET)
#define RP23XX_RV_I2C_IC_ENABLE_STATUS(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_ENABLE_STATUS_OFFSET)
#define RP23XX_RV_I2C_IC_FS_SPKLEN(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_FS_SPKLEN_OFFSET)
#define RP23XX_RV_I2C_IC_CLR_RESTART_DET(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_CLR_RESTART_DET_OFFSET)
#define RP23XX_RV_I2C_IC_COMP_PARAM_1(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_COMP_PARAM_1_OFFSET)
#define RP23XX_RV_I2C_IC_COMP_VERSION(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_COMP_VERSION_OFFSET)
#define RP23XX_RV_I2C_IC_COMP_TYPE(n) (RP23XX_RV_I2C_BASE(n) + RP23XX_RV_I2C_IC_COMP_TYPE_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_RV_I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE (1 << 10) /* Master issues the STOP_DET interrupt irrespective of whether master is active or not */
#define RP23XX_RV_I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL (1 << 9) /* Hold bus when RX_FIFO is full */
#define RP23XX_RV_I2C_IC_CON_TX_EMPTY_CTRL (1 << 8) /* Controlled generation of TX_EMPTY interrupt */
#define RP23XX_RV_I2C_IC_CON_STOP_DET_IFADDRESSED (1 << 7) /* slave issues STOP_DET intr only if addressed */
#define RP23XX_RV_I2C_IC_CON_IC_SLAVE_DISABLE (1 << 6) /* Slave mode is disabled */
#define RP23XX_RV_I2C_IC_CON_IC_RESTART_EN (1 << 5) /* Master restart enabled */
#define RP23XX_RV_I2C_IC_CON_IC_10BITADDR_MASTER (1 << 4) /* Master 10Bit addressing mode */
#define RP23XX_RV_I2C_IC_CON_IC_10BITADDR_SLAVE (1 << 3) /* Slave 10Bit addressing */
#define RP23XX_RV_I2C_IC_CON_SPEED_SHIFT (1) /* These bits control at which speed the DW_apb_i2c operates */
#define RP23XX_RV_I2C_IC_CON_SPEED_MASK (0x03 << RP23XX_RV_I2C_IC_CON_SPEED_SHIFT)
#define RP23XX_RV_I2C_IC_CON_SPEED_STANDARD (0x1 << RP23XX_RV_I2C_IC_CON_SPEED_SHIFT)
#define RP23XX_RV_I2C_IC_CON_SPEED_FAST (0x2 << RP23XX_RV_I2C_IC_CON_SPEED_SHIFT)
#define RP23XX_RV_I2C_IC_CON_SPEED_HIGH (0x3 << RP23XX_RV_I2C_IC_CON_SPEED_SHIFT)
#define RP23XX_RV_I2C_IC_CON_MASTER_MODE (1 << 0) /* Master mode is enabled */
#define RP23XX_RV_I2C_IC_TAR_SPECIAL (1 << 11) /* Enables programming of GENERAL_CALL or START_BYTE transmission */
#define RP23XX_RV_I2C_IC_TAR_GC_OR_START (1 << 10) /* START byte transmission */
#define RP23XX_RV_I2C_IC_TAR_MASK (0x3ff) /* This is the target address for any master transaction. */
#define RP23XX_RV_I2C_IC_SAR_MASK (0x3ff) /* The IC_SAR holds the slave address when the I2C is operating as a slave. */
#define RP23XX_RV_I2C_IC_DATA_CMD_FIRST_DATA_BYTE (1 << 11) /* Non sequential data byte received */
#define RP23XX_RV_I2C_IC_DATA_CMD_RESTART (1 << 10) /* Issue RESTART before this command */
#define RP23XX_RV_I2C_IC_DATA_CMD_STOP (1 << 9) /* Issue STOP after this command */
#define RP23XX_RV_I2C_IC_DATA_CMD_CMD (1 << 8) /* Master Read Command */
#define RP23XX_RV_I2C_IC_DATA_CMD_DAT_MASK (0xff) /* This register contains the data to be transmitted or received on the I2C bus. */
#define RP23XX_RV_I2C_IC_SS_SCL_HCNT_MASK (0xffff) /* This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. */
#define RP23XX_RV_I2C_IC_SS_SCL_LCNT_MASK (0xffff) /* This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. */
#define RP23XX_RV_I2C_IC_FS_SCL_HCNT_MASK (0xffff) /* This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. */
#define RP23XX_RV_I2C_IC_FS_SCL_LCNT_MASK (0xffff) /* This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_MASTER_ON_HOLD (1 << 13) /* R_MASTER_ON_HOLD interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_RESTART_DET (1 << 12) /* R_RESTART_DET interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_GEN_CALL (1 << 11) /* R_GEN_CALL interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_START_DET (1 << 10) /* R_START_DET interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_STOP_DET (1 << 9) /* R_STOP_DET interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_ACTIVITY (1 << 8) /* R_ACTIVITY interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_RX_DONE (1 << 7) /* R_RX_DONE interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_TX_ABRT (1 << 6) /* R_TX_ABRT interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_RD_REQ (1 << 5) /* R_RD_REQ interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_TX_EMPTY (1 << 4) /* R_TX_EMPTY interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_TX_OVER (1 << 3) /* R_TX_OVER interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_RX_FULL (1 << 2) /* R_RX_FULL interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_RX_OVER (1 << 1) /* R_RX_OVER interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_STAT_R_RX_UNDER (1 << 0) /* RX_UNDER interrupt is active */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY (1 << 13) /* MASTER_ON_HOLD interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_RESTART_DET (1 << 12) /* RESTART_DET interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_GEN_CALL (1 << 11) /* GEN_CALL interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_START_DET (1 << 10) /* START_DET interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_STOP_DET (1 << 9) /* STOP_DET interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_ACTIVITY (1 << 8) /* ACTIVITY interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_RX_DONE (1 << 7) /* RX_DONE interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_TX_ABRT (1 << 6) /* TX_ABORT interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_RD_REQ (1 << 5) /* RD_REQ interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_TX_EMPTY (1 << 4) /* TX_EMPTY interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_TX_OVER (1 << 3) /* TX_OVER interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_RX_FULL (1 << 2) /* RX_FULL interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_RX_OVER (1 << 1) /* RX_OVER interrupt is unmasked */
#define RP23XX_RV_I2C_IC_INTR_MASK_M_RX_UNDER (1 << 0) /* RX_UNDER interrupt is unmasked */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD (1 << 13) /* MASTER_ON_HOLD interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_RESTART_DET (1 << 12) /* RESTART_DET interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_GEN_CALL (1 << 11) /* GEN_CALL interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_START_DET (1 << 10) /* START_DET interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_STOP_DET (1 << 9) /* STOP_DET interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_ACTIVITY (1 << 8) /* RAW_INTR_ACTIVITY interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_RX_DONE (1 << 7) /* RX_DONE interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_TX_ABRT (1 << 6) /* TX_ABRT interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_RD_REQ (1 << 5) /* RD_REQ interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_TX_EMPTY (1 << 4) /* TX_EMPTY interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_TX_OVER (1 << 3) /* TX_OVER interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_RX_FULL (1 << 2) /* RX_FULL interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_RX_OVER (1 << 1) /* RX_OVER interrupt is active */
#define RP23XX_RV_I2C_IC_RAW_INTR_STAT_RX_UNDER (1 << 0) /* RX_UNDER interrupt is active */
#define RP23XX_RV_I2C_IC_RX_TL_RX_TL_MASK (0xff) /* Receive FIFO Threshold Level. */
#define RP23XX_RV_I2C_IC_TX_TL_TX_TL_MASK (0xff) /* Transmit FIFO Threshold Level. */
#define RP23XX_RV_I2C_IC_CLR_INTR_CLR_INTR (1 << 0) /* Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. */
#define RP23XX_RV_I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER (1 << 0) /* Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_CLR_RX_OVER_CLR_RX_OVER (1 << 0) /* Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_CLR_TX_OVER_CLR_TX_OVER (1 << 0) /* Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_CLR_RD_REQ_CLR_RD_REQ (1 << 0) /* Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT (1 << 0) /* Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. */
#define RP23XX_RV_I2C_IC_CLR_RX_DONE_CLR_RX_DONE (1 << 0) /* Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY (1 << 0) /* Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. */
#define RP23XX_RV_I2C_IC_CLR_STOP_DET_CLR_STOP_DET (1 << 0) /* Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_CLR_START_DET_CLR_START_DET (1 << 0) /* Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL (1 << 0) /* Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_ENABLE_TX_CMD_BLOCK (1 << 2) /* Tx Command execution blocked */
#define RP23XX_RV_I2C_IC_ENABLE_ABORT (1 << 1) /* ABORT operation in progress */
#define RP23XX_RV_I2C_IC_ENABLE_ENABLE (1 << 0) /* I2C is enabled */
#define RP23XX_RV_I2C_IC_STATUS_SLV_ACTIVITY (1 << 6) /* Slave not idle */
#define RP23XX_RV_I2C_IC_STATUS_MST_ACTIVITY (1 << 5) /* Master not idle */
#define RP23XX_RV_I2C_IC_STATUS_RFF (1 << 4) /* Rx FIFO is full */
#define RP23XX_RV_I2C_IC_STATUS_RFNE (1 << 3) /* Rx FIFO not empty */
#define RP23XX_RV_I2C_IC_STATUS_TFE (1 << 2) /* Tx FIFO is empty */
#define RP23XX_RV_I2C_IC_STATUS_TFNF (1 << 1) /* Tx FIFO not full */
#define RP23XX_RV_I2C_IC_STATUS_ACTIVITY (1 << 0) /* I2C is active */
#define RP23XX_RV_I2C_IC_TXFLR_TXFLR_MASK (0x1f) /* Transmit FIFO Level. */
#define RP23XX_RV_I2C_IC_RXFLR_RXFLR_MASK (0x1f) /* Receive FIFO Level. */
#define RP23XX_RV_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_SHIFT (16) /* Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. */
#define RP23XX_RV_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MASK (0xff << RP23XX_RV_I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_SHIFT)
#define RP23XX_RV_I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MASK (0xffff) /* Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_SHIFT (23) /* This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MASK (0x1ff << RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_SHIFT)
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT (1 << 16) /* Transfer abort detected by master */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX (1 << 15) /* Slave trying to transmit to remote master in read mode */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST (1 << 14) /* Slave lost arbitration to remote master */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO (1 << 13) /* Slave flushes existing data in TX-FIFO upon getting read command */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ARB_LOST (1 << 12) /* Master or Slave-Transmitter lost arbitration */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS (1 << 11) /* User initiating master operation when MASTER disabled */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT (1 << 10) /* Master trying to read in 10Bit addressing mode when RESTART disabled */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT (1 << 9) /* User trying to send START byte when RESTART disabled */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT (1 << 8) /* User trying to switch Master to HS mode when RESTART disabled */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET (1 << 7) /* ACK detected for START byte */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET (1 << 6) /* HS Master code ACKed in HS Mode */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ (1 << 5) /* GCALL is followed by read from bus */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK (1 << 4) /* GCALL not ACKed by any slave */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK (1 << 3) /* Transmitted data not ACKed by addressed slave */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK (1 << 2) /* Byte 2 of 10Bit Address not ACKed by any slave */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK (1 << 1) /* Byte 1 of 10Bit Address not ACKed by any slave */
#define RP23XX_RV_I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK (1 << 0) /* This abort is generated because of NOACK for 7-bit address */
#define RP23XX_RV_I2C_IC_SLV_DATA_NACK_ONLY_NACK (1 << 0) /* Slave receiver generates NACK upon data reception only */
#define RP23XX_RV_I2C_IC_DMA_CR_TDMAE (1 << 1) /* Transmit FIFO DMA channel enabled */
#define RP23XX_RV_I2C_IC_DMA_CR_RDMAE (1 << 0) /* Receive FIFO DMA channel enabled */
#define RP23XX_RV_I2C_IC_DMA_TDLR_DMATDL_MASK (0x0f) /* Transmit Data Level. */
#define RP23XX_RV_I2C_IC_DMA_RDLR_DMARDL_MASK (0x0f) /* Receive Data Level. */
#define RP23XX_RV_I2C_IC_SDA_SETUP_SDA_SETUP_MASK (0xff) /* SDA Setup. */
#define RP23XX_RV_I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL (1 << 0) /* Generate ACK for a General Call */
#define RP23XX_RV_I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST (1 << 2) /* Slave RX Data is lost */
#define RP23XX_RV_I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY (1 << 1) /* Slave is disabled when it is active */
#define RP23XX_RV_I2C_IC_ENABLE_STATUS_IC_EN (1 << 0) /* I2C enabled */
#define RP23XX_RV_I2C_IC_FS_SPKLEN_MASK (0xff) /* This register must be set before any I2C bus transaction can take place to ensure stable operation. */
#define RP23XX_RV_I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET (1 << 0) /* Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_SHIFT (16) /* TX Buffer Depth = 16 */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MASK (0xff << RP23XX_RV_I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_SHIFT)
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_SHIFT (8) /* RX Buffer Depth = 16 */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MASK (0xff << RP23XX_RV_I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_SHIFT)
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS (1 << 7) /* Encoded parameters not visible */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_HAS_DMA (1 << 6) /* DMA handshaking signals are enabled */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_INTR_IO (1 << 5) /* COMBINED Interrupt outputs */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES (1 << 4) /* Programmable count values for each mode. */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_SHIFT (2) /* MAX SPEED MODE = FAST MODE */
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MASK (0x03 << RP23XX_RV_I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_SHIFT)
#define RP23XX_RV_I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MASK (0x03) /* APB data bus width is 32 bits */
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_I2C_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_intctrl.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_INTCTRL_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_INTCTRL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define RP23XX_TIMER0_IRQ_0 0
#define RP23XX_TIMER0_IRQ_1 1
#define RP23XX_TIMER0_IRQ_2 2
#define RP23XX_TIMER0_IRQ_3 3
#define RP23XX_TIMER1_IRQ_0 4
#define RP23XX_TIMER1_IRQ_1 5
#define RP23XX_TIMER1_IRQ_2 6
#define RP23XX_TIMER1_IRQ_3 7
#define RP23XX_RV_PWM_IRQ_WRAP_0 8
#define RP23XX_RV_PWM_IRQ_WRAP_1 9
#define RP23XX_DMA_IRQ_0 10
#define RP23XX_DMA_IRQ_1 11
#define RP23XX_DMA_IRQ_2 12
#define RP23XX_DMA_IRQ_3 13
#define RP23XX_USBCTRL_IRQ 14
#define RP23XX_PIO0_IRQ_0 15
#define RP23XX_PIO0_IRQ_1 16
#define RP23XX_PIO1_IRQ_0 17
#define RP23XX_PIO1_IRQ_1 18
#define RP23XX_PIO2_IRQ_0 19
#define RP23XX_PIO2_IRQ_1 20
#define RP23XX_IO_IRQ_BANK0 21
#define RP23XX_IO_IRQ_BANK0_NS 22
#define RP23XX_IO_IRQ_QSPI 23
#define RP23XX_IO_IRQ_QSPI_NS 24
#define RP23XX_SIO_IRQ_FIFO 25
#define RP23XX_SIO_IRQ_BELL 26
#define RP23XX_SIO_IRQ_FIFO_NS 27
#define RP23XX_SIO_IRQ_BELL_NS 28
#define RP23XX_SIO_IRQ_MTIMECMP 29
#define RP23XX_CLOCKS_IRQ 30
#define RP23XX_RV_SPI0_IRQ 31
#define RP23XX_RV_SPI1_IRQ 32
#define RP23XX_RV_UART0_IRQ 33
#define RP23XX_RV_UART1_IRQ 34
#define RP23XX_RV_ADC_IRQ_FIFO 35
#define RP23XX_RV_I2C0_IRQ 36
#define RP23XX_RV_I2C1_IRQ 37
#define RP23XX_OTP_IRQ 38
#define RP23XX_TRNG_IRQ 39
#define RP23XX_PROC0_IRQ_CTI 40
#define RP23XX_PROC1_IRQ_CTI 41
#define RP23XX_PLL_SYS_IRQ 42
#define RP23XX_PLL_USB_IRQ 43
#define RP23XX_POWMAN_IRQ_POW 44
#define RP23XX_POWMAN_IRQ_TIMER 45
#define RP23XX_SPARE_IRQ_0 46
#define RP23XX_SPARE_IRQ_1 47
#define RP23XX_SPARE_IRQ_2 48
#define RP23XX_SPARE_IRQ_3 49
#define RP23XX_SPARE_IRQ_4 50
#define RP23XX_SPARE_IRQ_5 51
#define RP23XX_IRQ_COUNT 52
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_INTCTRL_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_io_bank0.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_io_bank0.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_IO_BANK0_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_IO_BANK0_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_IO_BANK0_GPIO_STATUS_OFFSET(n) ((n) * 8 + 0x000000)
#define RP23XX_IO_BANK0_GPIO_CTRL_OFFSET(n) ((n) * 8 + 0x000004)
#define RP23XX_IO_BANK0_IRQSUMMARY_PROC_SECURE_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x10) + 0x000200)
#define RP23XX_IO_BANK0_IRQSUMMARY_PROC_NONSECURE_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x10) + 0x000208)
#define RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET(n) (((n) >> 3) * 4 + 0x00000220)
#define RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET(n) (((n) >> 3) * 4 + 0x00000228)
#define RP23XX_IO_BANK0_INTR_OFFSET(n) (((n) >> 3) * 4 + 0x000230)
#define RP23XX_IO_BANK0_PROC_INTE_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x48) + 0x000248)
#define RP23XX_IO_BANK0_PROC_INTF_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x48) + 0x000260)
#define RP23XX_IO_BANK0_PROC_INTS_OFFSET(n, p) (((n) >> 3) * 4 + ((p) * 0x48) + 0x000278)
#define RP23XX_IO_BANK0_DORMANT_WAKE_INTE_OFFSET(n) (((n) >> 3) * 4 + 0x0002d8)
#define RP23XX_IO_BANK0_DORMANT_WAKE_INTF_OFFSET(n) (((n) >> 3) * 4 + 0x0002f0)
#define RP23XX_IO_BANK0_DORMANT_WAKE_INTS_OFFSET(n) (((n) >> 3) * 4 + 0x000308)
/* Register definitions *****************************************************/
#define RP23XX_IO_BANK0_GPIO_STATUS(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_GPIO_STATUS_OFFSET(n))
#define RP23XX_IO_BANK0_GPIO_CTRL(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_GPIO_CTRL_OFFSET(n))
#define RP23XX_IO_BANK0_INTR(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_INTR_OFFSET(n))
#define RP23XX_IO_BANK0_PROC_INTE(n, p) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_PROC_INTE_OFFSET(n, p))
#define RP23XX_IO_BANK0_PROC_INTF(n, p) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_PROC_INTF_OFFSET(n, p))
#define RP23XX_IO_BANK0_PROC_INTS(n, p) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_PROC_INTS_OFFSET(n, p))
#define RP23XX_IO_BANK0_DORMANT_WAKE_INTE(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_DORMANT_WAKE_INTE_OFFSET(n))
#define RP23XX_IO_BANK0_DORMANT_WAKE_INTF(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_DORMANT_WAKE_INTF_OFFSET(n))
#define RP23XX_IO_BANK0_DORMANT_WAKE_INTS(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_DORMANT_WAKE_INTS_OFFSET(n))
#define RP23XX_IO_BANK0_IRQSUMMARY_PROC_SECURE(n, p) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_IRQSUMMARY_PROC_SECURE_OFFSET(n, p))
#define RP23XX_IO_BANK0_IRQSUMMARY_PROC_NONSECURE(n, p) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_IRQSUMMARY_PROC_NONSECURE_OFFSET(n, p))
#define RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET(n))
#define RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE(n) (RP23XX_IO_BANK0_BASE + RP23XX_IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_IO_BANK0_GPIO_STATUS_IRQTOPROC (1 << 26) /* interrupt to processors, after override is applied */
#define RP23XX_IO_BANK0_GPIO_STATUS_INFROMPAD (1 << 17) /* input signal from pad, before override is applied */
#define RP23XX_IO_BANK0_GPIO_STATUS_OETOPAD (1 << 13) /* output enable to pad after register override is applied */
#define RP23XX_IO_BANK0_GPIO_STATUS_OUTTOPAD (1 << 9) /* output signal to pad after register override is applied */
#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_SHIFT (28)
#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_MASK (0x03 << RP23XX_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT)
#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_NORMAL (0x0 << RP23XX_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* don't invert the interrupt */
#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_INVERT (0x1 << RP23XX_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* invert the interrupt */
#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_LOW (0x2 << RP23XX_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* drive interrupt low */
#define RP23XX_IO_BANK0_GPIO_CTRL_IRQOVER_HIGH (0x3 << RP23XX_IO_BANK0_GPIO0_CTRL_IRQOVER_SHIFT) /* drive interrupt high */
#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_SHIFT (16)
#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_MASK (0x03 << RP23XX_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT)
#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_NORMAL (0x0 << RP23XX_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* don't invert the peri input */
#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_INVERT (0x1 << RP23XX_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* invert the peri input */
#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_LOW (0x2 << RP23XX_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* drive peri input low */
#define RP23XX_IO_BANK0_GPIO_CTRL_INOVER_HIGH (0x3 << RP23XX_IO_BANK0_GPIO0_CTRL_INOVER_SHIFT) /* drive peri input high */
#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_SHIFT (14)
#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_MASK (0x03 << RP23XX_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT)
#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_NORMAL (0x0 << RP23XX_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* drive output enable from peripheral signal selected by funcsel */
#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_INVERT (0x1 << RP23XX_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* drive output enable from inverse of peripheral signal selected by funcsel */
#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_DISABLE (0x2 << RP23XX_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* disable output */
#define RP23XX_IO_BANK0_GPIO_CTRL_OEOVER_ENABLE (0x3 << RP23XX_IO_BANK0_GPIO0_CTRL_OEOVER_SHIFT) /* enable output */
#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_SHIFT (12)
#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_MASK (0x03 << RP23XX_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT)
#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_NORMAL (0x0 << RP23XX_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output from peripheral signal selected by funcsel */
#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_INVERT (0x1 << RP23XX_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output from inverse of peripheral signal selected by funcsel */
#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_LOW (0x2 << RP23XX_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output low */
#define RP23XX_IO_BANK0_GPIO_CTRL_OUTOVER_HIGH (0x3 << RP23XX_IO_BANK0_GPIO0_CTRL_OUTOVER_SHIFT) /* drive output high */
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_MASK (0x1f)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_HSTX (0x0)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_SPI (0x1)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_UART (0x2)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_I2C (0x3)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PWM (0x4)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_SIO (0x5)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PIO0 (0x6)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PIO1 (0x7)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_PIO2 (0x8)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_GPCK (0x9)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_USB (0xa)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_UART_AUX (0xb)
#define RP23XX_IO_BANK0_GPIO_CTRL_FUNCSEL_NULL (0x1f)
#define RP23XX_IO_BANK0_INTR_GPIO_EDGE_HIGH(n) (1 << (((n) & 0x7) * 4 + 3))
#define RP23XX_IO_BANK0_INTR_GPIO_EDGE_LOW(n) (1 << (((n) & 0x7) * 4 + 2))
#define RP23XX_IO_BANK0_INTR_GPIO_LEVEL_HIGH(n) (1 << (((n) & 0x7) * 4 + 1))
#define RP23XX_IO_BANK0_INTR_GPIO_LEVEL_LOW(n) (1 << (((n) & 0x7) * 4))
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_IO_BANK0_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_io_qspi.h Normal file
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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_memorymap.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_memorymap.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_MEMORYMAP_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "riscv_internal.h"
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define RP23XX_FLASH_BASE 0x10000000 /* -0x001fffff: FLASH memory space (2048KB) */
#define RP23XX_SRAM_BASE 0x20000000 /* -0x20041fff: SRAM memory space (520KB) */
#define RP23XX_SYSINFO_BASE 0x40000000
#define RP23XX_SYSCFG_BASE 0x40008000 /* Register block for various chip control signals */
#define RP23XX_CLOCKS_BASE 0x40010000
#define RP23XX_RESETS_BASE 0x40020000
#define RP23XX_PSM_BASE 0x40018000
#define RP23XX_IO_BANK0_BASE 0x40028000
#define RP23XX_IO_QSPI_BASE 0x40030000
#define RP23XX_PADS_BANK0_BASE 0x40038000
#define RP23XX_PADS_QSPI_BASE 0x40040000
#define RP23XX_XOSC_BASE 0x40048000 /* Controls the crystal oscillator */
#define RP23XX_PLL_SYS_BASE 0x40050000
#define RP23XX_PLL_USB_BASE 0x40058000
#define RP23XX_BUSCTRL_BASE 0x40068000 /* Register block for busfabric control signals and performance counters */
#define RP23XX_RV_UART0_BASE 0x40070000
#define RP23XX_RV_UART1_BASE 0x40078000
#define RP23XX_RV_UART_BASE(n) (0x40070000 + (n) * 0x8000)
#define RP23XX_RV_SPI0_BASE 0x40080000
#define RP23XX_RV_SPI1_BASE 0x40088000
#define RP23XX_RV_SPI_BASE(n) (0x40080000 + (n) * 0x8000)
#define RP23XX_RV_I2C0_BASE 0x40090000 /* DW_apb_i2c address block */
#define RP23XX_RV_I2C1_BASE 0x40098000 /* DW_apb_i2c address block */
#define RP23XX_RV_I2C_BASE(n) (0x40090000 + (n) * 0x8000)
#define RP23XX_RV_ADC_BASE 0x400a0000 /* Control and data interface to SAR ADC */
#define RP23XX_RV_PWM_BASE 0x400a8000 /* Simple PWM */
#define RP23XX_TIMER0_BASE 0x400b0000
#define RP23XX_TIMER1_BASE 0x400b8000
#define RP23XX_TIMER_BASE(n) (0x400b0000 + (n) * 0x8000)
#define RP23XX_HSTX_CTRL_BASE 0x400c0000
#define RP23XX_XIP_CTRL_BASE 0x400c8000 /* QSPI flash execute-in-place block */
#define RP23XX_XIP_QMI_BASE 0x400d0000
#define RP23XX_WATCHDOG_BASE 0x400d8000
#define RP23XX_BOOTRAM_BASE 0x400e0000
#define RP23XX_ROSC_BASE 0x400e8000
#define RP23XX_TRNG_BASE 0x400f0000
#define RP23XX_SHA256_BASE 0x400f8000
#define RP23XX_POWMAN_BASE 0x40100000 /* Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use */
#define RP23XX_TICKS_BASE 0x40108000
#define RP23XX_OTP_BASE 0x40120000
#define RP23XX_OTP_DATA_BASE 0x40130000
#define RP23XX_OTP_DATA_RAW_BASE 0x40134000
#define RP23XX_OTP_DATA_GUARDED_BASE 0x40138000
#define RP23XX_OTP_DATA_RAW_GUARDED_BASE 0x4013c000
#define RP23XX_DFT_BASE 0x40150000
#define RP23XX_GLITCH_DETECTOR_BASE 0x40158000
#define RP23XX_OTP_BASE 0x40120000
#define RP23XX_TBMAN_BASE 0x40160000 /* Testbench manager. Allows the programmer to know what platform their software is running on. */
#define RP23XX_DMA_BASE 0x50000000 /* DMA with separate read and write masters */
#define RP23XX_USBCTRL_DPSRAM_BASE 0x50100000 /* USB Dual Port SRAM */
#define RP23XX_USBCTRL_REGS_BASE 0x50110000 /* USB FS/LS controller device registers */
#define RP23XX_PIO0_BASE 0x50200000 /* Programmable IO block */
#define RP23XX_PIO1_BASE 0x50300000 /* Programmable IO block */
#define RP23XX_PIO2_BASE 0x50400000 /* Programmable IO block */
#define RP23XX_PIO_BASE(n) (0x50200000 + (n) * 0x100000)
#define RP23XX_XIP_AUX_BASE 0x50500000
#define RP23XX_HSTX_FIFO_BASE 0x50600000
#define RP23XX_CORESIGHT_TRACE_BASE 0x50700000
#define RP23XX_SIO_BASE 0xd0000000 /* Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access. */
#define RP23XX_SIO_NONSEC_BASE 0xd0020000
#define RP23XX_PPB_BASE 0xe0000000
#define RP23XX_PPB_NONSEC_BASE 0xe0020000
#define RP23XX_EPPB_BASE 0xe0080000
#define RP23XX_ATOMIC_XOR_REG_OFFSET 0x1000
#define RP23XX_ATOMIC_SET_REG_OFFSET 0x2000
#define RP23XX_ATOMIC_CLR_REG_OFFSET 0x3000
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#define RP23XX_IDLESTACK_BASE (uintptr_t)_ebss
#else
#define RP23XX_IDLESTACK_BASE _ebss
#endif
#define RP23XX_IDLE_STACK (RP23XX_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE)
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
# define xorbits_reg32(v,a) putreg32(v, (a) | RP23XX_ATOMIC_XOR_REG_OFFSET)
# define setbits_reg32(v,a) putreg32(v, (a) | RP23XX_ATOMIC_SET_REG_OFFSET)
# define clrbits_reg32(v,a) putreg32(v, (a) | RP23XX_ATOMIC_CLR_REG_OFFSET)
# define modbits_reg32(v,m,a) xorbits_reg32((getreg32(a) ^ (v)) & (m), a)
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_MEMORYMAP_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_otp.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_OTP_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_OTP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_OTP_SW_LOCK_OFFSET(n) (0x000000 + (n) * 4)
#define RP23XX_OTP_SBPI_INSTR_OFFSET 0x00000100
#define RP23XX_OTP_SBPI_WDATA_0_OFFSET 0x00000104
#define RP23XX_OTP_SBPI_WDATA_1_OFFSET 0x00000108
#define RP23XX_OTP_SBPI_WDATA_2_OFFSET 0x0000010c
#define RP23XX_OTP_SBPI_WDATA_3_OFFSET 0x00000110
#define RP23XX_OTP_SBPI_RDATA_0_OFFSET 0x00000114
#define RP23XX_OTP_SBPI_RDATA_1_OFFSET 0x00000118
#define RP23XX_OTP_SBPI_RDATA_2_OFFSET 0x0000011c
#define RP23XX_OTP_SBPI_RDATA_3_OFFSET 0x00000120
#define RP23XX_OTP_SBPI_STATUS_OFFSET 0x00000124
#define RP23XX_OTP_USR_OFFSET 0x00000128
#define RP23XX_OTP_DBG_OFFSET 0x0000012c
#define RP23XX_OTP_BIST_OFFSET 0x00000134
#define RP23XX_OTP_CRT_KEY_W0_OFFSET 0x00000138
#define RP23XX_OTP_CRT_KEY_W1_OFFSET 0x0000013c
#define RP23XX_OTP_CRT_KEY_W2_OFFSET 0x00000140
#define RP23XX_OTP_CRT_KEY_W3_OFFSET 0x00000144
#define RP23XX_OTP_CRITICAL_OFFSET 0x00000148
#define RP23XX_OTP_KEY_VALID_OFFSET 0x0000014c
#define RP23XX_OTP_DEBUGEN_OFFSET 0x00000150
#define RP23XX_OTP_DEBUGEN_LOCK_OFFSET 0x00000154
#define RP23XX_OTP_ARCHSEL_OFFSET 0x00000158
#define RP23XX_OTP_ARCHSEL_STATUS_OFFSET 0x0000015c
#define RP23XX_OTP_BOOTDIS_OFFSET 0x00000160
#define RP23XX_OTP_INTR_OFFSET 0x00000164
#define RP23XX_OTP_INTE_OFFSET 0x00000168
#define RP23XX_OTP_INTF_OFFSET 0x0000016c
#define RP23XX_OTP_INTS_OFFSET 0x00000170
/* Register definitions *****************************************************/
#define RP23XX_OTP_SW_LOCK(n) (RP23XX_OTP_BASE + RP23XX_OTP_SW_LOCK_OFFSET(n))
#define RP23XX_OTP_SBPI_INSTR (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_INSTR_OFFSET)
#define RP23XX_OTP_SBPI_WDATA_0 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_WDATA_0_OFFSET)
#define RP23XX_OTP_SBPI_WDATA_1 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_WDATA_1_OFFSET)
#define RP23XX_OTP_SBPI_WDATA_2 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_WDATA_2_OFFSET)
#define RP23XX_OTP_SBPI_WDATA_3 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_WDATA_3_OFFSET)
#define RP23XX_OTP_SBPI_RDATA_0 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_RDATA_0_OFFSET)
#define RP23XX_OTP_SBPI_RDATA_1 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_RDATA_1_OFFSET)
#define RP23XX_OTP_SBPI_RDATA_2 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_RDATA_2_OFFSET)
#define RP23XX_OTP_SBPI_RDATA_3 (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_RDATA_3_OFFSET)
#define RP23XX_OTP_SBPI_STATUS (RP23XX_OTP_BASE + RP23XX_OTP_SBPI_STATUS_OFFSET)
#define RP23XX_OTP_USR (RP23XX_OTP_BASE + RP23XX_OTP_USR_OFFSET)
#define RP23XX_OTP_DBG (RP23XX_OTP_BASE + RP23XX_OTP_DBG_OFFSET)
#define RP23XX_OTP_BIST (RP23XX_OTP_BASE + RP23XX_OTP_BIST_OFFSET)
#define RP23XX_OTP_CRT_KEY_W0 (RP23XX_OTP_BASE + RP23XX_OTP_CRT_KEY_W0_OFFSET)
#define RP23XX_OTP_CRT_KEY_W1 (RP23XX_OTP_BASE + RP23XX_OTP_CRT_KEY_W1_OFFSET)
#define RP23XX_OTP_CRT_KEY_W2 (RP23XX_OTP_BASE + RP23XX_OTP_CRT_KEY_W2_OFFSET)
#define RP23XX_OTP_CRT_KEY_W3 (RP23XX_OTP_BASE + RP23XX_OTP_CRT_KEY_W3_OFFSET)
#define RP23XX_OTP_CRITICAL (RP23XX_OTP_BASE + RP23XX_OTP_CRITICAL_OFFSET)
#define RP23XX_OTP_KEY_VALID (RP23XX_OTP_BASE + RP23XX_OTP_KEY_VALID_OFFSET)
#define RP23XX_OTP_DEBUGEN (RP23XX_OTP_BASE + RP23XX_OTP_DEBUGEN_OFFSET)
#define RP23XX_OTP_DEBUGEN_LOCK (RP23XX_OTP_BASE + RP23XX_OTP_DEBUGEN_LOCK_OFFSET)
#define RP23XX_OTP_ARCHSEL (RP23XX_OTP_BASE + RP23XX_OTP_ARCHSEL_OFFSET)
#define RP23XX_OTP_ARCHSEL_STATUS (RP23XX_OTP_BASE + RP23XX_OTP_ARCHSEL_STATUS_OFFSET)
#define RP23XX_OTP_BOOTDIS (RP23XX_OTP_BASE + RP23XX_OTP_BOOTDIS_OFFSET)
#define RP23XX_OTP_INTR (RP23XX_OTP_BASE + RP23XX_OTP_INTR_OFFSET)
#define RP23XX_OTP_INTE (RP23XX_OTP_BASE + RP23XX_OTP_INTE_OFFSET)
#define RP23XX_OTP_INTF (RP23XX_OTP_BASE + RP23XX_OTP_INTF_OFFSET)
#define RP23XX_OTP_INTS (RP23XX_OTP_BASE + RP23XX_OTP_INTS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_OTP_SW_LOCK_MASK 0x0000000f
#define RP23XX_OTP_SW_LOCK_NSEC_MASK 0x0000000c
#define RP23XX_OTP_SW_LOCK_SEC_MASK 0x00000003
#define RP23XX_OTP_SBPI_INSTR_MASK 0x7fffffff
#define RP23XX_OTP_SBPI_INSTR_EXEC (1 << 30)
#define RP23XX_OTP_SBPI_INSTR_IS_WR (1 << 29)
#define RP23XX_OTP_SBPI_INSTR_HAS_PAYLOAD (1 << 28)
#define RP23XX_OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_MASK 0x0f000000
#define RP23XX_OTP_SBPI_INSTR_TARGET_MASK 0x00ff0000
#define RP23XX_OTP_SBPI_INSTR_CMD_MASK 0x0000ff00
#define RP23XX_OTP_SBPI_INSTR_SHORT_WDATA_MASK 0x000000ff
#define RP23XX_OTP_SBPI_STATUS_MASK 0x00ff1111
#define RP23XX_OTP_SBPI_STATUS_MISO_MASK 0x00ff0000
#define RP23XX_OTP_SBPI_STATUS_FLAG (1 << 12)
#define RP23XX_OTP_SBPI_STATUS_INSTR_MISS (1 << 8)
#define RP23XX_OTP_SBPI_STATUS_INSTR_DONE (1 << 4)
#define RP23XX_OTP_SBPI_STATUS_RDATA_VLD (1 << 0)
#define RP23XX_OTP_USR_MASK 0x00000011
#define RP23XX_OTP_USR_PD (1 << 4)
#define RP23XX_OTP_USR_DCTRL (1 << 0)
#define RP23XX_OTP_DBG_MASK 0x000010ff
#define RP23XX_OTP_DBG_CUSTOMER_RMA_FLAG (1 << 12)
#define RP23XX_OTP_DBG_PSM_STATE_MASK 0x000000f0
#define RP23XX_OTP_DBG_ROSC_UP (1 << 3)
#define RP23XX_OTP_DBG_ROSC_UP_SEEN (1 << 2)
#define RP23XX_OTP_DBG_BOOT_DONE (1 << 1)
#define RP23XX_OTP_DBG_PSM_DONE (1 << 0)
#define RP23XX_OTP_BIST_MASK 0x7fff1fff
#define RP23XX_OTP_BIST_CNT_FAIL (1 << 30)
#define RP23XX_OTP_BIST_CNT_CLR (1 << 29)
#define RP23XX_OTP_BIST_CNT_ENA (1 << 28)
#define RP23XX_OTP_BIST_CNT_MAX_MASK 0x0fff0000
#define RP23XX_OTP_BIST_CNT_MASK 0x00001fff
#define RP23XX_OTP_CRITICAL_MASK 0x0003007f
#define RP23XX_OTP_CRITICAL_RISCV_DISABLE (1 << 17)
#define RP23XX_OTP_CRITICAL_ARM_DISABLE (1 << 16)
#define RP23XX_OTP_CRITICAL_GLITCH_DETECTOR_SENS_MASK 0x00000060
#define RP23XX_OTP_CRITICAL_GLITCH_DETECTOR_ENABLE (1 << 4)
#define RP23XX_OTP_CRITICAL_DEFAULT_ARCHSEL (1 << 3)
#define RP23XX_OTP_CRITICAL_DEBUG_DISABLE (1 << 2)
#define RP23XX_OTP_CRITICAL_SECURE_DEBUG_DISABLE (1 << 1)
#define RP23XX_OTP_CRITICAL_SECURE_BOOT_ENABLE (1 << 0)
#define RP23XX_OTP_KEY_VALID_MASK 0x000000ff
#define RP23XX_OTP_DEBUGEN_MASK 0x0000010f
#define RP23XX_OTP_DEBUGEN_MISC (1 << 8)
#define RP23XX_OTP_DEBUGEN_PROC1_SECURE (1 << 3)
#define RP23XX_OTP_DEBUGEN_PROC1 (1 << 2)
#define RP23XX_OTP_DEBUGEN_PROC0_SECURE (1 << 1)
#define RP23XX_OTP_DEBUGEN_PROC0 (1 << 0)
#define RP23XX_OTP_DEBUGEN_LOCK_MASK 0x0000010f
#define RP23XX_OTP_DEBUGEN_LOCK_MISC (1 << 8)
#define RP23XX_OTP_DEBUGEN_LOCK_PROC1_SECURE (1 << 3)
#define RP23XX_OTP_DEBUGEN_LOCK_PROC1 (1 << 2)
#define RP23XX_OTP_DEBUGEN_LOCK_PROC0_SECURE (1 << 1)
#define RP23XX_OTP_DEBUGEN_LOCK_PROC0 (1 << 0)
#define RP23XX_OTP_ARCHSEL_MASK 0x00000003
#define RP23XX_OTP_ARCHSEL_CORE1 (1 << 1)
#define RP23XX_OTP_ARCHSEL_CORE0 (1 << 0)
#define RP23XX_OTP_ARCHSEL_STATUS_MASK 0x00000003
#define RP23XX_OTP_ARCHSEL_STATUS_CORE1 (1 << 1)
#define RP23XX_OTP_ARCHSEL_STATUS_CORE0 (1 << 0)
#define RP23XX_OTP_BOOTDIS_MASK 0x00000003
#define RP23XX_OTP_BOOTDIS_NEXT (1 << 1)
#define RP23XX_OTP_BOOTDIS_NOW (1 << 0)
#define RP23XX_OTP_INTR_MASK 0x0000001f
#define RP23XX_OTP_INTR_APB_RD_NSEC_FAIL (1 << 4)
#define RP23XX_OTP_INTR_APB_RD_SEC_FAIL (1 << 3)
#define RP23XX_OTP_INTR_APB_DCTRL_FAIL (1 << 2)
#define RP23XX_OTP_INTR_SBPI_WR_FAIL (1 << 1)
#define RP23XX_OTP_INTR_SBPI_FLAG_N (1 << 0)
#define RP23XX_OTP_INTE_MASK 0x0000001f
#define RP23XX_OTP_INTE_APB_RD_NSEC_FAIL (1 << 4)
#define RP23XX_OTP_INTE_APB_RD_SEC_FAIL (1 << 3)
#define RP23XX_OTP_INTE_APB_DCTRL_FAIL (1 << 2)
#define RP23XX_OTP_INTE_SBPI_WR_FAIL (1 << 1)
#define RP23XX_OTP_INTE_SBPI_FLAG_N (1 << 0)
#define RP23XX_OTP_INTF_MASK 0x0000001f
#define RP23XX_OTP_INTF_APB_RD_NSEC_FAIL (1 << 4)
#define RP23XX_OTP_INTF_APB_RD_SEC_FAIL (1 << 3)
#define RP23XX_OTP_INTF_APB_DCTRL_FAIL (1 << 2)
#define RP23XX_OTP_INTF_SBPI_WR_FAIL (1 << 1)
#define RP23XX_OTP_INTF_SBPI_FLAG_N (1 << 0)
#define RP23XX_OTP_INTS_MASK 0x0000001f
#define RP23XX_OTP_INTS_APB_RD_NSEC_FAIL (1 << 4)
#define RP23XX_OTP_INTS_APB_RD_SEC_FAIL (1 << 3)
#define RP23XX_OTP_INTS_APB_DCTRL_FAIL (1 << 2)
#define RP23XX_OTP_INTS_SBPI_WR_FAIL (1 << 1)
#define RP23XX_OTP_INTS_SBPI_FLAG_N (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_OTP_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_otp_data.h Normal file
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67
arch/risc-v/src/rp23xx-rv/hardware/rp23xx_pads_bank0.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_pads_bank0.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PADS_BANK0_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PADS_BANK0_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_PADS_BANK0_VOLTAGE_SELECT_OFFSET 0x000000 /* Voltage select. Per bank control */
#define RP23XX_PADS_BANK0_GPIO_OFFSET(n) ((n) * 4 + 0x000004) /* Pad control register */
#define RP23XX_PADS_BANK0_SWCLK_OFFSET 0x0000c4 /* Pad control register */
#define RP23XX_PADS_BANK0_SWD_OFFSET 0x0000c8 /* Pad control register */
/* Register definitions *****************************************************/
#define RP23XX_PADS_BANK0_VOLTAGE_SELECT (RP23XX_PADS_BANK0_BASE + RP23XX_PADS_BANK0_VOLTAGE_SELECT_OFFSET)
#define RP23XX_PADS_BANK0_GPIO(n) (RP23XX_PADS_BANK0_BASE + RP23XX_PADS_BANK0_GPIO_OFFSET(n))
#define RP23XX_PADS_BANK0_SWCLK (RP23XX_PADS_BANK0_BASE + RP23XX_PADS_BANK0_SWCLK_OFFSET)
#define RP23XX_PADS_BANK0_SWD (RP23XX_PADS_BANK0_BASE + RP23XX_PADS_BANK0_SWD_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_PADS_BANK0_VOLTAGE_SELECT_1_8V (1 << 0) /* Set voltage to 1.8V (DVDD <= 1V8) */
#define RP23XX_PADS_BANK0_GPIO_ISO (1 << 8) /* Pad isolation control. Remove this once the pad is configured by software */
#define RP23XX_PADS_BANK0_GPIO_OD (1 << 7) /* Output disable. Has priority over output enable from peripherals */
#define RP23XX_PADS_BANK0_GPIO_IE (1 << 6) /* Input enable */
#define RP23XX_PADS_BANK0_GPIO_DRIVE_SHIFT (4) /* Drive strength */
#define RP23XX_PADS_BANK0_GPIO_DRIVE_MASK (0x03 << RP23XX_PADS_BANK0_GPIO_DRIVE_SHIFT)
#define RP23XX_PADS_BANK0_GPIO_DRIVE_2MA (0x0 << RP23XX_PADS_BANK0_GPIO_DRIVE_SHIFT)
#define RP23XX_PADS_BANK0_GPIO_DRIVE_4MA (0x1 << RP23XX_PADS_BANK0_GPIO_DRIVE_SHIFT)
#define RP23XX_PADS_BANK0_GPIO_DRIVE_8MA (0x2 << RP23XX_PADS_BANK0_GPIO_DRIVE_SHIFT)
#define RP23XX_PADS_BANK0_GPIO_DRIVE_12MA (0x3 << RP23XX_PADS_BANK0_GPIO_DRIVE_SHIFT)
#define RP23XX_PADS_BANK0_GPIO_PUE (1 << 3) /* Pull up enable */
#define RP23XX_PADS_BANK0_GPIO_PDE (1 << 2) /* Pull down enable */
#define RP23XX_PADS_BANK0_GPIO_SCHMITT (1 << 1) /* Enable schmitt trigger */
#define RP23XX_PADS_BANK0_GPIO_SLEWFAST (1 << 0) /* Slew rate control. 1 = Fast, 0 = Slow */
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PADS_BANK0_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_pads_qspi.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_pads_qspi.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PADS_QSPI_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PADS_QSPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_PADS_QSPI_VOLTAGE_SELECT_OFFSET 0x00000000
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_OFFSET 0x00000004
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_OFFSET 0x00000008
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_OFFSET 0x0000000c
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_OFFSET 0x00000010
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_OFFSET 0x00000014
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_OFFSET 0x00000018
/* Register definitions *****************************************************/
#define RP23XX_PADS_QSPI_VOLTAGE_SELECT (RP23XX_PADS_QSPI_BASE + RP23XX_PADS_QSPI_VOLTAGE_SELECT_OFFSET)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK (RP23XX_PADS_QSPI_BASE + RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_OFFSET)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0 (RP23XX_PADS_QSPI_BASE + RP23XX_PADS_QSPI_GPIO_QSPI_SD0_OFFSET)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1 (RP23XX_PADS_QSPI_BASE + RP23XX_PADS_QSPI_GPIO_QSPI_SD1_OFFSET)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2 (RP23XX_PADS_QSPI_BASE + RP23XX_PADS_QSPI_GPIO_QSPI_SD2_OFFSET)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3 (RP23XX_PADS_QSPI_BASE + RP23XX_PADS_QSPI_GPIO_QSPI_SD3_OFFSET)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS (RP23XX_PADS_QSPI_BASE + RP23XX_PADS_QSPI_GPIO_QSPI_SS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_PADS_QSPI_VOLTAGE_SELECT (1 << 0)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_MASK 0x000001ff
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_ISO (1 << 8)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_OD (1 << 7)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_IE (1 << 6)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MASK 0x00000030
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_PUE (1 << 3)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_PDE (1 << 2)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT (1 << 1)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST (1 << 0)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_MASK 0x000001ff
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_ISO (1 << 8)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_OD (1 << 7)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_IE (1 << 6)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MASK 0x00000030
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_PUE (1 << 3)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_PDE (1 << 2)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_SCHMITT (1 << 1)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST (1 << 0)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_MASK 0x000001ff
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_ISO (1 << 8)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_OD (1 << 7)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_IE (1 << 6)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MASK 0x00000030
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_PUE (1 << 3)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_PDE (1 << 2)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_SCHMITT (1 << 1)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST (1 << 0)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_MASK 0x000001ff
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_ISO (1 << 8)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_OD (1 << 7)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_IE (1 << 6)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MASK 0x00000030
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_PUE (1 << 3)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_PDE (1 << 2)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_SCHMITT (1 << 1)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST (1 << 0)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_MASK 0x000001ff
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_ISO (1 << 8)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_OD (1 << 7)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_IE (1 << 6)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MASK 0x00000030
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_PUE (1 << 3)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_PDE (1 << 2)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_SCHMITT (1 << 1)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST (1 << 0)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_MASK 0x000001ff
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_ISO (1 << 8)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_OD (1 << 7)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_IE (1 << 6)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_DRIVE_MASK 0x00000030
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_PUE (1 << 3)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_PDE (1 << 2)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_SCHMITT (1 << 1)
#define RP23XX_PADS_QSPI_GPIO_QSPI_SS_SLEWFAST (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PADS_QSPI_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_pio.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PIO_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_PIO_CTRL_OFFSET 0x000000 /* PIO control register */
#define RP23XX_PIO_FSTAT_OFFSET 0x000004 /* FIFO status register */
#define RP23XX_PIO_FDEBUG_OFFSET 0x000008 /* FIFO debug register */
#define RP23XX_PIO_FLEVEL_OFFSET 0x00000c /* FIFO levels */
#define RP23XX_PIO_TXF_OFFSET(m) (0x000010 + (m) * 4) /* Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. */
#define RP23XX_PIO_RXF_OFFSET(m) (0x000020 + (m) * 4) /* Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. */
#define RP23XX_PIO_IRQ_OFFSET 0x000030 /* Interrupt request register. Write 1 to clear */
#define RP23XX_PIO_IRQ_FORCE_OFFSET 0x000034 /* Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. */
#define RP23XX_PIO_INPUT_SYNC_BYPASS_OFFSET 0x000038 /* There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes. */
#define RP23XX_PIO_DBG_PADOUT_OFFSET 0x00003c /* Read to sample the pad output values PIO is currently driving to the GPIOs. */
#define RP23XX_PIO_DBG_PADOE_OFFSET 0x000040 /* Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. */
#define RP23XX_PIO_DBG_CFGINFO_OFFSET 0x000044 /* The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here. */
#define RP23XX_PIO_INSTR_MEM_OFFSET(m) (0x000048 + (m) * 4) /* Write-only access to instruction memory location m */
#define RP23XX_PIO_SM_CLKDIV_OFFSET(m) (0x0000c8 + (m) * 0x18) /* Clock divider register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */
#define RP23XX_PIO_SM_EXECCTRL_OFFSET(m) (0x0000cc + (m) * 0x18) /* Execution/behavioural settings for state machine 0 */
#define RP23XX_PIO_SM_SHIFTCTRL_OFFSET(m) (0x0000d0 + (m) * 0x18) /* Control behaviour of the input/output shift registers for state machine 0 */
#define RP23XX_PIO_SM_ADDR_OFFSET(m) (0x0000d4 + (m) * 0x18) /* Current instruction address of state machine 0 */
#define RP23XX_PIO_SM_INSTR_OFFSET(m) (0x0000d8 + (m) * 0x18) /* Instruction currently being executed by state machine 0 Write to execute an instruction immediately (including jumps) and then resume execution. */
#define RP23XX_PIO_SM_PINCTRL_OFFSET(m) (0x0000dc + (m) * 0x18) /* State machine pin control */
#define RP23XX_PIO_RXF_PUTGET0_OFFSET(m) (0x000128 + (m) * 0x10) /* Direct read/write access to entry 0 of SM’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. */
#define RP23XX_PIO_RXF_PUTGET1_OFFSET(m) (0x00012c + (m) * 0x10) /* Direct read/write access to entry 0 of SM’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. */
#define RP23XX_PIO_RXF_PUTGET2_OFFSET(m) (0x000130 + (m) * 0x10) /* Direct read/write access to entry 0 of SM’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. */
#define RP23XX_PIO_RXF_PUTGET3_OFFSET(m) (0x000134 + (m) * 0x10) /* Direct read/write access to entry 0 of SM’s RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. */
#define RP23XX_PIO_GPIOBASE_OFFSET 0x000168 /* Relocate GPIO 0 (from PIO’s point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. Only the values 0 and 16 are supported (only bit 4 is writable) */
#define RP23XX_PIO_INTR_OFFSET 0x00016c /* Raw Interrupts */
#define RP23XX_PIO_IRQ0_INTE_OFFSET 0x000170 /* Interrupt Enable for irq0 */
#define RP23XX_PIO_IRQ0_INTF_OFFSET 0x000174 /* Interrupt Force for irq0 */
#define RP23XX_PIO_IRQ0_INTS_OFFSET 0x000178 /* Interrupt status after masking & forcing for irq0 */
#define RP23XX_PIO_IRQ1_INTE_OFFSET 0x00017c /* Interrupt Enable for irq1 */
#define RP23XX_PIO_IRQ1_INTF_OFFSET 0x000180 /* Interrupt Force for irq1 */
#define RP23XX_PIO_IRQ1_INTS_OFFSET 0x000184 /* Interrupt status after masking & forcing for irq1 */
/* Register definitions *****************************************************/
#define RP23XX_PIO_CTRL(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_CTRL_OFFSET)
#define RP23XX_PIO_FSTAT(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_FSTAT_OFFSET)
#define RP23XX_PIO_FDEBUG(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_FDEBUG_OFFSET)
#define RP23XX_PIO_FLEVEL(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_FLEVEL_OFFSET)
#define RP23XX_PIO_TXF(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_TXF_OFFSET(m))
#define RP23XX_PIO_RXF(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_RXF_OFFSET(m))
#define RP23XX_PIO_IRQ(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_IRQ_OFFSET)
#define RP23XX_PIO_IRQ_FORCE(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_IRQ_FORCE_OFFSET)
#define RP23XX_PIO_INPUT_SYNC_BYPASS(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_INPUT_SYNC_BYPASS_OFFSET)
#define RP23XX_PIO_DBG_PADOUT(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_DBG_PADOUT_OFFSET)
#define RP23XX_PIO_DBG_PADOE(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_DBG_PADOE_OFFSET)
#define RP23XX_PIO_DBG_CFGINFO(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_DBG_CFGINFO_OFFSET)
#define RP23XX_PIO_INSTR_MEM(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_INSTR_MEM_OFFSET(m))
#define RP23XX_PIO_SM_CLKDIV(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_SM_CLKDIV_OFFSET(m))
#define RP23XX_PIO_SM_EXECCTRL(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_SM_EXECCTRL_OFFSET(m))
#define RP23XX_PIO_SM_SHIFTCTRL(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_SM_SHIFTCTRL_OFFSET(m))
#define RP23XX_PIO_SM_ADDR(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_SM_ADDR_OFFSET(m))
#define RP23XX_PIO_SM_INSTR(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_SM_INSTR_OFFSET(m))
#define RP23XX_PIO_SM_PINCTRL(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_SM_PINCTRL_OFFSET(m))
#define RP23XX_PIO_RXF_PUTGET0(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_RXF_PUTGET0_OFFSET(m))
#define RP23XX_PIO_RXF_PUTGET1(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_RXF_PUTGET1_OFFSET(m))
#define RP23XX_PIO_RXF_PUTGET2(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_RXF_PUTGET2_OFFSET(m))
#define RP23XX_PIO_RXF_PUTGET3(n, m) (RP23XX_PIO_BASE(n) + RP23XX_PIO_RXF_PUTGET3_OFFSET(m))
#define RP23XX_PIO_GPIOBASE(n) (RP23XX_PIO_BASE(n) + RP23XX_PIO_GPIOBASE_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_PIO_CTRL_NEXTPREV_CLKDIV_RESTART (1 << 26) /* Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers */
#define RP23XX_PIO_CTRL_NEXTPREV_SM_DISABLE (1 << 25) /* Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers */
#define RP23XX_PIO_CTRL_NEXTPREV_SM_ENABLE (1 << 24) /* Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers. If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence */
#define RP23XX_PIO_NEXT_PIO_MASK_SHIFT (20) /* A mask of state machines in the neighbouring highernumbered PIO block in the system (or PIO block 0 if this is the highestnumbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write */
#define RP23XX_PIO_NEXT_PIO_MASK_MASK (0xf)
#define RP23XX_PIO_PREV_PIO_MASK_SHIFT (16) /* A mask of state machines in the neighbouring lowernumbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write */
#define RP23XX_PIO_PREV_PIO_MASK_MASK (0xf)
#define RP23XX_PIO_CTRL_CLKDIV_RESTART_SHIFT (8) /* Force clock dividers to restart their count and clear fractional accumulators. Restart multiple dividers to synchronise them. */
#define RP23XX_PIO_CTRL_CLKDIV_RESTART_MASK (0x0f << RP23XX_PIO_CTRL_CLKDIV_RESTART_SHIFT)
#define RP23XX_PIO_CTRL_SM_RESTART_SHIFT (4) /* Clear internal SM state which is otherwise difficult to access (e.g. shift counters). Self-clearing. */
#define RP23XX_PIO_CTRL_SM_RESTART_MASK (0x0f << RP23XX_PIO_CTRL_SM_RESTART_SHIFT)
#define RP23XX_PIO_CTRL_SM_ENABLE_MASK (0x0f) /* Enable state machine */
#define RP23XX_PIO_FSTAT_TXEMPTY_SHIFT (24) /* State machine TX FIFO is empty */
#define RP23XX_PIO_FSTAT_TXEMPTY_MASK (0x0f << RP23XX_PIO_FSTAT_TXEMPTY_SHIFT)
#define RP23XX_PIO_FSTAT_TXFULL_SHIFT (16) /* State machine TX FIFO is full */
#define RP23XX_PIO_FSTAT_TXFULL_MASK (0x0f << RP23XX_PIO_FSTAT_TXFULL_SHIFT)
#define RP23XX_PIO_FSTAT_RXEMPTY_SHIFT (8) /* State machine RX FIFO is empty */
#define RP23XX_PIO_FSTAT_RXEMPTY_MASK (0x0f << RP23XX_PIO_FSTAT_RXEMPTY_SHIFT)
#define RP23XX_PIO_FSTAT_RXFULL_SHIFT (0) /* State machine RX FIFO is full */
#define RP23XX_PIO_FSTAT_RXFULL_MASK (0x0f) /* State machine RX FIFO is full */
#define RP23XX_PIO_FDEBUG_TXSTALL_SHIFT (24) /* State machine has stalled on empty TX FIFO. Write 1 to clear. */
#define RP23XX_PIO_FDEBUG_TXSTALL_MASK (0x0f << RP23XX_PIO_FDEBUG_TXSTALL_SHIFT)
#define RP23XX_PIO_FDEBUG_TXOVER_SHIFT (16) /* TX FIFO overflow has occurred. Write 1 to clear. */
#define RP23XX_PIO_FDEBUG_TXOVER_MASK (0x0f << RP23XX_PIO_FDEBUG_TXOVER_SHIFT)
#define RP23XX_PIO_FDEBUG_RXUNDER_SHIFT (8) /* RX FIFO underflow has occurred. Write 1 to clear. */
#define RP23XX_PIO_FDEBUG_RXUNDER_MASK (0x0f << RP23XX_PIO_FDEBUG_RXUNDER_SHIFT)
#define RP23XX_PIO_FDEBUG_RXSTALL_SHIFT (0) /* State machine has stalled on full RX FIFO. Write 1 to clear. */
#define RP23XX_PIO_FDEBUG_RXSTALL_MASK (0x0f) /* State machine has stalled on full RX FIFO. Write 1 to clear. */
#define RP23XX_PIO_FLEVEL_RX3_SHIFT (28)
#define RP23XX_PIO_FLEVEL_RX3_MASK (0x0f << RP23XX_PIO_FLEVEL_RX3_SHIFT)
#define RP23XX_PIO_FLEVEL_TX3_SHIFT (24)
#define RP23XX_PIO_FLEVEL_TX3_MASK (0x0f << RP23XX_PIO_FLEVEL_TX3_SHIFT)
#define RP23XX_PIO_FLEVEL_RX2_SHIFT (20)
#define RP23XX_PIO_FLEVEL_RX2_MASK (0x0f << RP23XX_PIO_FLEVEL_RX2_SHIFT)
#define RP23XX_PIO_FLEVEL_TX2_SHIFT (16)
#define RP23XX_PIO_FLEVEL_TX2_MASK (0x0f << RP23XX_PIO_FLEVEL_TX2_SHIFT)
#define RP23XX_PIO_FLEVEL_RX1_SHIFT (12)
#define RP23XX_PIO_FLEVEL_RX1_MASK (0x0f << RP23XX_PIO_FLEVEL_RX1_SHIFT)
#define RP23XX_PIO_FLEVEL_TX1_SHIFT (8)
#define RP23XX_PIO_FLEVEL_TX1_MASK (0x0f << RP23XX_PIO_FLEVEL_TX1_SHIFT)
#define RP23XX_PIO_FLEVEL_RX0_SHIFT (4)
#define RP23XX_PIO_FLEVEL_RX0_MASK (0x0f << RP23XX_PIO_FLEVEL_RX0_SHIFT)
#define RP23XX_PIO_FLEVEL_TX0_SHIFT (0)
#define RP23XX_PIO_FLEVEL_TX0_MASK (0x0f)
#define RP23XX_PIO_FLEVEL_TX_MASK(n) (0x0f << 8*n)
#define RP23XX_PIO_FLEVEL_RX_MASK(n) (0xf0 << 8*n)
#define RP23XX_PIO_IRQ_MASK (0xff)
#define RP23XX_PIO_IRQ_FORCE_MASK (0xff)
#define RP23XX_PIO_DBG_CFGINFO_VERSION_SHIFT (28) /* Version of the core PIO hardware */
#define RP23XX_PIO_DBG_CFGINFO_VERSION_MASK (0xf << RP23XX_PIO_DBG_CFGINFO_VERSION_SHIFT)
#define RP23XX_PIO_DBG_CFGINFO_IMEM_SIZE_SHIFT (16) /* The size of the instruction memory, measured in units of one instruction */
#define RP23XX_PIO_DBG_CFGINFO_IMEM_SIZE_MASK (0x3f << RP23XX_PIO_DBG_CFGINFO_IMEM_SIZE_SHIFT)
#define RP23XX_PIO_DBG_CFGINFO_SM_COUNT_SHIFT (8) /* The number of state machines this PIO instance is equipped with. */
#define RP23XX_PIO_DBG_CFGINFO_SM_COUNT_MASK (0x0f << RP23XX_PIO_DBG_CFGINFO_SM_COUNT_SHIFT)
#define RP23XX_PIO_DBG_CFGINFO_FIFO_DEPTH_MASK (0x3f) /* The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth. */
#define RP23XX_PIO_INSTR_MEM_MASK (0xffff)
#define RP23XX_PIO_SM_CLKDIV_INT_SHIFT (16) /* Effective frequency is sysclk/int. Value of 0 is interpreted as max possible value */
#define RP23XX_PIO_SM_CLKDIV_INT_MASK (0xffff << RP23XX_PIO_SM_CLKDIV_INT_SHIFT)
#define RP23XX_PIO_SM_CLKDIV_FRAC_SHIFT (8) /* Fractional part of clock divider */
#define RP23XX_PIO_SM_CLKDIV_FRAC_MASK (0xff << RP23XX_PIO_SM_CLKDIV_FRAC_SHIFT)
#define RP23XX_PIO_SM_EXECCTRL_EXEC_STALLED (1 << 31) /* An instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear once the instruction completes. */
#define RP23XX_PIO_SM_EXECCTRL_SIDE_EN (1 << 30) /* If 1, the delay MSB is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction. */
#define RP23XX_PIO_SM_EXECCTRL_SIDE_PINDIR (1 << 29) /* Side-set data is asserted to pin OEs instead of pin values */
#define RP23XX_PIO_SM_EXECCTRL_JMP_PIN_SHIFT (24) /* The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. */
#define RP23XX_PIO_SM_EXECCTRL_JMP_PIN_MASK (0x1f << RP23XX_PIO_SM_EXECCTRL_JMP_PIN_SHIFT)
#define RP23XX_PIO_SM_EXECCTRL_OUT_EN_SEL_SHIFT (19) /* Which data bit to use for inline OUT enable */
#define RP23XX_PIO_SM_EXECCTRL_OUT_EN_SEL_MASK (0x1f << RP23XX_PIO_SM_EXECCTRL_OUT_EN_SEL_SHIFT)
#define RP23XX_PIO_SM_EXECCTRL_INLINE_OUT_EN (1 << 18) /* If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) */
#define RP23XX_PIO_SM_EXECCTRL_OUT_STICKY (1 << 17) /* Continuously assert the most recent OUT/SET to the pins */
#define RP23XX_PIO_SM_EXECCTRL_WRAP_TOP_SHIFT (12) /* After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority. */
#define RP23XX_PIO_SM_EXECCTRL_WRAP_TOP_MASK (0x1f << RP23XX_PIO_SM_EXECCTRL_WRAP_TOP_SHIFT)
#define RP23XX_PIO_SM_EXECCTRL_WRAP_BOTTOM_SHIFT (7) /* After reaching wrap_top, execution is wrapped to this address. */
#define RP23XX_PIO_SM_EXECCTRL_WRAP_BOTTOM_MASK (0x1f << RP23XX_PIO_SM_EXECCTRL_WRAP_BOTTOM_SHIFT)
#define RP23XX_PIO_SM_EXECCTRL_STATUS_SEL_SHIFT (5) /* Comparison used for the MOV x, STATUS instruction */
#define RP23XX_PIO_SM_EXECCTRL_STATUS_SEL_MASK (0x3 << RP23XX_PIO_SM_EXECCTRL_STATUS_SEL_SHIFT)
#define RP23XX_PIO_SM_EXECCTRL_STATUS_N_MASK (0x0f) /* : Comparison level or IRQ index for the MOV x, STATUS instruction */
#define RP23XX_PIO_SM_SHIFTCTRL_FJOIN_RX (1 << 31) /* When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. */
#define RP23XX_PIO_SM_SHIFTCTRL_FJOIN_TX (1 << 30) /* When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. */
#define RP23XX_PIO_SM_SHIFTCTRL_PULL_THRESH_SHIFT (25) /* Number of bits shifted out of TXSR before autopull or conditional pull. Write 0 for value of 32. */
#define RP23XX_PIO_SM_SHIFTCTRL_PULL_THRESH_MASK (0x1f << RP23XX_PIO_SM_SHIFTCTRL_PULL_THRESH_SHIFT)
#define RP23XX_PIO_SM_SHIFTCTRL_PUSH_THRESH_SHIFT (20) /* Number of bits shifted into RXSR before autopush or conditional push. Write 0 for value of 32. */
#define RP23XX_PIO_SM_SHIFTCTRL_PUSH_THRESH_MASK (0x1f << RP23XX_PIO_SM_SHIFTCTRL_PUSH_THRESH_SHIFT)
#define RP23XX_PIO_SM_SHIFTCTRL_OUT_SHIFTDIR (1 << 19) /* 1 = shift out of output shift register to right. 0 = to left. */
#define RP23XX_PIO_SM_SHIFTCTRL_IN_SHIFTDIR (1 << 18) /* 1 = shift input shift register to right (data enters from left). 0 = to left. */
#define RP23XX_PIO_SM_SHIFTCTRL_AUTOPULL (1 << 17) /* Pull automatically when the output shift register is emptied */
#define RP23XX_PIO_SM_SHIFTCTRL_AUTOPUSH (1 << 16) /* Push automatically when the input shift register is filled */
#define RP23XX_PIO_SM_SHIFTCTRL_FJOIN_RX_PUT (1 << 15) /* If 1, disable this state machine’s RX FIFO, make its storage available for random write access by the state machine (using the put instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). */
#define RP23XX_PIO_SM_SHIFTCTRL_FJOIN_TX_GET (1 << 14) /* If 1, disable this state machine’s RX FIFO, make its storage available for random read access by the state machine (using the get instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers) */
#define RP23XX_PIO_SM_ADDR_MASK (0x1f)
#define RP23XX_PIO_SM_INSTR_MASK (0xffff)
#define RP23XX_PIO_SM_PINCTRL_SIDESET_COUNT_SHIFT (29) /* The number of delay bits co-opted for side-set. Inclusive of the enable bit, if present. */
#define RP23XX_PIO_SM_PINCTRL_SIDESET_COUNT_MASK (0x07 << RP23XX_PIO_SM_PINCTRL_SIDESET_COUNT_SHIFT)
#define RP23XX_PIO_SM_PINCTRL_SET_COUNT_SHIFT (26) /* The number of pins asserted by a SET. Max of 5 */
#define RP23XX_PIO_SM_PINCTRL_SET_COUNT_MASK (0x07 << RP23XX_PIO_SM_PINCTRL_SET_COUNT_SHIFT)
#define RP23XX_PIO_SM_PINCTRL_OUT_COUNT_SHIFT (20) /* The number of pins asserted by an OUT. Value of 0 -> 32 pins */
#define RP23XX_PIO_SM_PINCTRL_OUT_COUNT_MASK (0x3f << RP23XX_PIO_SM_PINCTRL_OUT_COUNT_SHIFT)
#define RP23XX_PIO_SM_PINCTRL_IN_BASE_SHIFT (15) /* The virtual pin corresponding to IN bit 0 */
#define RP23XX_PIO_SM_PINCTRL_IN_BASE_MASK (0x1f << RP23XX_PIO_SM_PINCTRL_IN_BASE_SHIFT)
#define RP23XX_PIO_SM_PINCTRL_SIDESET_BASE_SHIFT (10) /* The virtual pin corresponding to delay field bit 0 */
#define RP23XX_PIO_SM_PINCTRL_SIDESET_BASE_MASK (0x1f << RP23XX_PIO_SM_PINCTRL_SIDESET_BASE_SHIFT)
#define RP23XX_PIO_SM_PINCTRL_SET_BASE_SHIFT (5) /* The virtual pin corresponding to SET bit 0 */
#define RP23XX_PIO_SM_PINCTRL_SET_BASE_MASK (0x1f << RP23XX_PIO_SM_PINCTRL_SET_BASE_SHIFT)
#define RP23XX_PIO_SM_PINCTRL_OUT_BASE_SHIFT (0) /* The virtual pin corresponding to OUT bit 0 */
#define RP23XX_PIO_SM_PINCTRL_OUT_BASE_MASK (0x1f) /* The virtual pin corresponding to OUT bit 0 */
#define RP23XX_PIO_GPIOBASE_MASK (1 << 4) /* Relocate GPIO 0 (from PIO’s point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO */
#define RP23XX_PIO_INTR_SM7 (1 << 15)
#define RP23XX_PIO_INTR_SM6 (1 << 14)
#define RP23XX_PIO_INTR_SM5 (1 << 13)
#define RP23XX_PIO_INTR_SM4 (1 << 12)
#define RP23XX_PIO_INTR_SM3 (1 << 11)
#define RP23XX_PIO_INTR_SM2 (1 << 10)
#define RP23XX_PIO_INTR_SM1 (1 << 9)
#define RP23XX_PIO_INTR_SM0 (1 << 8)
#define RP23XX_PIO_INTR_SM3_TXNFULL (1 << 7)
#define RP23XX_PIO_INTR_SM2_TXNFULL (1 << 6)
#define RP23XX_PIO_INTR_SM1_TXNFULL (1 << 5)
#define RP23XX_PIO_INTR_SM0_TXNFULL (1 << 4)
#define RP23XX_PIO_INTR_SM3_RXNEMPTY (1 << 3)
#define RP23XX_PIO_INTR_SM2_RXNEMPTY (1 << 2)
#define RP23XX_PIO_INTR_SM1_RXNEMPTY (1 << 1)
#define RP23XX_PIO_INTR_SM0_RXNEMPTY (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PIO_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_pll.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PLL_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PLL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_PLL_CS_OFFSET 0x00000000
#define RP23XX_PLL_PWR_OFFSET 0x00000004
#define RP23XX_PLL_FBDIV_INT_OFFSET 0x00000008
#define RP23XX_PLL_PRIM_OFFSET 0x0000000c
#define RP23XX_PLL_INTR_OFFSET 0x00000010
#define RP23XX_PLL_INTE_OFFSET 0x00000014
#define RP23XX_PLL_INTF_OFFSET 0x00000018
#define RP23XX_PLL_INTS_OFFSET 0x0000001c
/* Register definitions *****************************************************/
#define RP23XX_PLL_CS (RP23XX_PLL_BASE + RP23XX_PLL_CS_OFFSET)
#define RP23XX_PLL_PWR (RP23XX_PLL_BASE + RP23XX_PLL_PWR_OFFSET)
#define RP23XX_PLL_FBDIV_INT (RP23XX_PLL_BASE + RP23XX_PLL_FBDIV_INT_OFFSET)
#define RP23XX_PLL_PRIM (RP23XX_PLL_BASE + RP23XX_PLL_PRIM_OFFSET)
#define RP23XX_PLL_INTR (RP23XX_PLL_BASE + RP23XX_PLL_INTR_OFFSET)
#define RP23XX_PLL_INTE (RP23XX_PLL_BASE + RP23XX_PLL_INTE_OFFSET)
#define RP23XX_PLL_INTF (RP23XX_PLL_BASE + RP23XX_PLL_INTF_OFFSET)
#define RP23XX_PLL_INTS (RP23XX_PLL_BASE + RP23XX_PLL_INTS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_PLL_CS_MASK (0xc000013f)
#define RP23XX_PLL_CS_LOCK (1 << 31)
#define RP23XX_PLL_CS_LOCK_N (1 << 30)
#define RP23XX_PLL_CS_BYPASS (1 << 8)
#define RP23XX_PLL_CS_REFDIV_MASK (0x0000003f)
#define RP23XX_PLL_PWR_MASK (0x0000002d)
#define RP23XX_PLL_PWR_VCOPD (1 << 5)
#define RP23XX_PLL_PWR_POSTDIVPD (1 << 3)
#define RP23XX_PLL_PWR_DSMPD (1 << 2)
#define RP23XX_PLL_PWR_PD (1 << 0)
#define RP23XX_PLL_FBDIV_INT_MASK (0x00000fff)
#define RP23XX_PLL_PRIM_MASK (0x00077000)
#define RP23XX_PLL_PRIM_POSTDIV1_SHIFT (16) /* divide by 1-7 */
#define RP23XX_PLL_PRIM_POSTDIV1_MASK (0x07 << RP23XX_PLL_PRIM_POSTDIV1_SHIFT)
#define RP23XX_PLL_PRIM_POSTDIV2_SHIFT (12) /* divide by 1-7 */
#define RP23XX_PLL_PRIM_POSTDIV2_MASK (0x07 << RP23XX_PLL_PRIM_POSTDIV2_SHIFT)
#define RP23XX_PLL_INTR_LOCK_N_STICKY (1 << 0)
#define RP23XX_PLL_INTE_LOCK_N_STICKY (1 << 0)
#define RP23XX_PLL_INTF_LOCK_N_STICKY (1 << 0)
#define RP23XX_PLL_INTS_LOCK_N_STICKY (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PLL_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_powman.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_POWMAN_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_POWMAN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_POWMAN_BADPASSWD_OFFSET 0x00000000
#define RP23XX_POWMAN_VREG_CTRL_OFFSET 0x00000004
#define RP23XX_POWMAN_VREG_STS_OFFSET 0x00000008
#define RP23XX_POWMAN_VREG_OFFSET 0x0000000c
#define RP23XX_POWMAN_VREG_LP_ENTRY_OFFSET 0x00000010
#define RP23XX_POWMAN_VREG_LP_EXIT_OFFSET 0x00000014
#define RP23XX_POWMAN_BOD_CTRL_OFFSET 0x00000018
#define RP23XX_POWMAN_BOD_OFFSET 0x0000001c
#define RP23XX_POWMAN_BOD_LP_ENTRY_OFFSET 0x00000020
#define RP23XX_POWMAN_BOD_LP_EXIT_OFFSET 0x00000024
#define RP23XX_POWMAN_LPOSC_OFFSET 0x00000028
#define RP23XX_POWMAN_CHIP_RESET_OFFSET 0x0000002c
#define RP23XX_POWMAN_WDSEL_OFFSET 0x00000030
#define RP23XX_POWMAN_SEQ_CFG_OFFSET 0x00000034
#define RP23XX_POWMAN_STATE_OFFSET 0x00000038
#define RP23XX_POWMAN_POW_FASTDIV_OFFSET 0x0000003c
#define RP23XX_POWMAN_POW_DELAY_OFFSET 0x00000040
#define RP23XX_POWMAN_EXT_CTRL0_OFFSET 0x00000044
#define RP23XX_POWMAN_EXT_CTRL1_OFFSET 0x00000048
#define RP23XX_POWMAN_EXT_TIME_REF_OFFSET 0x0000004c
#define RP23XX_POWMAN_LPOSC_FREQ_KHZ_INT_OFFSET 0x00000050
#define RP23XX_POWMAN_LPOSC_FREQ_KHZ_FRAC_OFFSET 0x00000054
#define RP23XX_POWMAN_XOSC_FREQ_KHZ_INT_OFFSET 0x00000058
#define RP23XX_POWMAN_XOSC_FREQ_KHZ_FRAC_OFFSET 0x0000005c
#define RP23XX_POWMAN_SET_TIME_63TO48_OFFSET 0x00000060
#define RP23XX_POWMAN_SET_TIME_47TO32_OFFSET 0x00000064
#define RP23XX_POWMAN_SET_TIME_31TO16_OFFSET 0x00000068
#define RP23XX_POWMAN_SET_TIME_15TO0_OFFSET 0x0000006c
#define RP23XX_POWMAN_READ_TIME_UPPER_OFFSET 0x00000070
#define RP23XX_POWMAN_READ_TIME_LOWER_OFFSET 0x00000074
#define RP23XX_POWMAN_ALARM_TIME_63TO48_OFFSET 0x00000078
#define RP23XX_POWMAN_ALARM_TIME_47TO32_OFFSET 0x0000007c
#define RP23XX_POWMAN_ALARM_TIME_31TO16_OFFSET 0x00000080
#define RP23XX_POWMAN_ALARM_TIME_15TO0_OFFSET 0x00000084
#define RP23XX_POWMAN_TIMER_OFFSET 0x00000088
#define RP23XX_POWMAN_PWRUP0_OFFSET 0x0000008c
#define RP23XX_POWMAN_PWRUP1_OFFSET 0x00000090
#define RP23XX_POWMAN_PWRUP2_OFFSET 0x00000094
#define RP23XX_POWMAN_PWRUP3_OFFSET 0x00000098
#define RP23XX_POWMAN_CURRENT_PWRUP_REQ_OFFSET 0x0000009c
#define RP23XX_POWMAN_LAST_SWCORE_PWRUP_OFFSET 0x000000a0
#define RP23XX_POWMAN_DBG_PWRCFG_OFFSET 0x000000a4
#define RP23XX_POWMAN_BOOTDIS_OFFSET 0x000000a8
#define RP23XX_POWMAN_DBGCONFIG_OFFSET 0x000000ac
#define RP23XX_POWMAN_SCRATCH0_OFFSET 0x000000b0
#define RP23XX_POWMAN_SCRATCH1_OFFSET 0x000000b4
#define RP23XX_POWMAN_SCRATCH2_OFFSET 0x000000b8
#define RP23XX_POWMAN_SCRATCH3_OFFSET 0x000000bc
#define RP23XX_POWMAN_SCRATCH4_OFFSET 0x000000c0
#define RP23XX_POWMAN_SCRATCH5_OFFSET 0x000000c4
#define RP23XX_POWMAN_SCRATCH6_OFFSET 0x000000c8
#define RP23XX_POWMAN_SCRATCH7_OFFSET 0x000000cc
#define RP23XX_POWMAN_BOOT0_OFFSET 0x000000d0
#define RP23XX_POWMAN_BOOT1_OFFSET 0x000000d4
#define RP23XX_POWMAN_BOOT2_OFFSET 0x000000d8
#define RP23XX_POWMAN_BOOT3_OFFSET 0x000000dc
#define RP23XX_POWMAN_INTR_OFFSET 0x000000e0
#define RP23XX_POWMAN_INTE_OFFSET 0x000000e4
#define RP23XX_POWMAN_INTF_OFFSET 0x000000e8
#define RP23XX_POWMAN_INTS_OFFSET 0x000000ec
/* Register definitions *****************************************************/
#define RP23XX_POWMAN_BADPASSWD (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BADPASSWD_OFFSET)
#define RP23XX_POWMAN_VREG_CTRL (RP23XX_POWMAN_BASE + RP23XX_POWMAN_VREG_CTRL_OFFSET)
#define RP23XX_POWMAN_VREG_STS (RP23XX_POWMAN_BASE + RP23XX_POWMAN_VREG_STS_OFFSET)
#define RP23XX_POWMAN_VREG (RP23XX_POWMAN_BASE + RP23XX_POWMAN_VREG_OFFSET)
#define RP23XX_POWMAN_VREG_LP_ENTRY (RP23XX_POWMAN_BASE + RP23XX_POWMAN_VREG_LP_ENTRY_OFFSET)
#define RP23XX_POWMAN_VREG_LP_EXIT (RP23XX_POWMAN_BASE + RP23XX_POWMAN_VREG_LP_EXIT_OFFSET)
#define RP23XX_POWMAN_BOD_CTRL (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOD_CTRL_OFFSET)
#define RP23XX_POWMAN_BOD (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOD_OFFSET)
#define RP23XX_POWMAN_BOD_LP_ENTRY (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOD_LP_ENTRY_OFFSET)
#define RP23XX_POWMAN_BOD_LP_EXIT (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOD_LP_EXIT_OFFSET)
#define RP23XX_POWMAN_LPOSC (RP23XX_POWMAN_BASE + RP23XX_POWMAN_LPOSC_OFFSET)
#define RP23XX_POWMAN_CHIP_RESET (RP23XX_POWMAN_BASE + RP23XX_POWMAN_CHIP_RESET_OFFSET)
#define RP23XX_POWMAN_WDSEL (RP23XX_POWMAN_BASE + RP23XX_POWMAN_WDSEL_OFFSET)
#define RP23XX_POWMAN_SEQ_CFG (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SEQ_CFG_OFFSET)
#define RP23XX_POWMAN_STATE (RP23XX_POWMAN_BASE + RP23XX_POWMAN_STATE_OFFSET)
#define RP23XX_POWMAN_POW_FASTDIV (RP23XX_POWMAN_BASE + RP23XX_POWMAN_POW_FASTDIV_OFFSET)
#define RP23XX_POWMAN_POW_DELAY (RP23XX_POWMAN_BASE + RP23XX_POWMAN_POW_DELAY_OFFSET)
#define RP23XX_POWMAN_EXT_CTRL0 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_EXT_CTRL0_OFFSET)
#define RP23XX_POWMAN_EXT_CTRL1 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_EXT_CTRL1_OFFSET)
#define RP23XX_POWMAN_EXT_TIME_REF (RP23XX_POWMAN_BASE + RP23XX_POWMAN_EXT_TIME_REF_OFFSET)
#define RP23XX_POWMAN_LPOSC_FREQ_KHZ_INT (RP23XX_POWMAN_BASE + RP23XX_POWMAN_LPOSC_FREQ_KHZ_INT_OFFSET)
#define RP23XX_POWMAN_LPOSC_FREQ_KHZ_FRAC (RP23XX_POWMAN_BASE + RP23XX_POWMAN_LPOSC_FREQ_KHZ_FRAC_OFFSET)
#define RP23XX_POWMAN_XOSC_FREQ_KHZ_INT (RP23XX_POWMAN_BASE + RP23XX_POWMAN_XOSC_FREQ_KHZ_INT_OFFSET)
#define RP23XX_POWMAN_XOSC_FREQ_KHZ_FRAC (RP23XX_POWMAN_BASE + RP23XX_POWMAN_XOSC_FREQ_KHZ_FRAC_OFFSET)
#define RP23XX_POWMAN_SET_TIME_63TO48 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SET_TIME_63TO48_OFFSET)
#define RP23XX_POWMAN_SET_TIME_47TO32 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SET_TIME_47TO32_OFFSET)
#define RP23XX_POWMAN_SET_TIME_31TO16 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SET_TIME_31TO16_OFFSET)
#define RP23XX_POWMAN_SET_TIME_15TO0 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SET_TIME_15TO0_OFFSET)
#define RP23XX_POWMAN_READ_TIME_UPPER (RP23XX_POWMAN_BASE + RP23XX_POWMAN_READ_TIME_UPPER_OFFSET)
#define RP23XX_POWMAN_READ_TIME_LOWER (RP23XX_POWMAN_BASE + RP23XX_POWMAN_READ_TIME_LOWER_OFFSET)
#define RP23XX_POWMAN_ALARM_TIME_63TO48 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_ALARM_TIME_63TO48_OFFSET)
#define RP23XX_POWMAN_ALARM_TIME_47TO32 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_ALARM_TIME_47TO32_OFFSET)
#define RP23XX_POWMAN_ALARM_TIME_31TO16 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_ALARM_TIME_31TO16_OFFSET)
#define RP23XX_POWMAN_ALARM_TIME_15TO0 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_ALARM_TIME_15TO0_OFFSET)
#define RP23XX_POWMAN_TIMER (RP23XX_POWMAN_BASE + RP23XX_POWMAN_TIMER_OFFSET)
#define RP23XX_POWMAN_PWRUP0 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_PWRUP0_OFFSET)
#define RP23XX_POWMAN_PWRUP1 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_PWRUP1_OFFSET)
#define RP23XX_POWMAN_PWRUP2 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_PWRUP2_OFFSET)
#define RP23XX_POWMAN_PWRUP3 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_PWRUP3_OFFSET)
#define RP23XX_POWMAN_CURRENT_PWRUP_REQ (RP23XX_POWMAN_BASE + RP23XX_POWMAN_CURRENT_PWRUP_REQ_OFFSET)
#define RP23XX_POWMAN_LAST_SWCORE_PWRUP (RP23XX_POWMAN_BASE + RP23XX_POWMAN_LAST_SWCORE_PWRUP_OFFSET)
#define RP23XX_POWMAN_DBG_PWRCFG (RP23XX_POWMAN_BASE + RP23XX_POWMAN_DBG_PWRCFG_OFFSET)
#define RP23XX_POWMAN_BOOTDIS (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOOTDIS_OFFSET)
#define RP23XX_POWMAN_DBGCONFIG (RP23XX_POWMAN_BASE + RP23XX_POWMAN_DBGCONFIG_OFFSET)
#define RP23XX_POWMAN_SCRATCH0 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH0_OFFSET)
#define RP23XX_POWMAN_SCRATCH1 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH1_OFFSET)
#define RP23XX_POWMAN_SCRATCH2 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH2_OFFSET)
#define RP23XX_POWMAN_SCRATCH3 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH3_OFFSET)
#define RP23XX_POWMAN_SCRATCH4 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH4_OFFSET)
#define RP23XX_POWMAN_SCRATCH5 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH5_OFFSET)
#define RP23XX_POWMAN_SCRATCH6 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH6_OFFSET)
#define RP23XX_POWMAN_SCRATCH7 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_SCRATCH7_OFFSET)
#define RP23XX_POWMAN_BOOT0 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOOT0_OFFSET)
#define RP23XX_POWMAN_BOOT1 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOOT1_OFFSET)
#define RP23XX_POWMAN_BOOT2 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOOT2_OFFSET)
#define RP23XX_POWMAN_BOOT3 (RP23XX_POWMAN_BASE + RP23XX_POWMAN_BOOT3_OFFSET)
#define RP23XX_POWMAN_INTR (RP23XX_POWMAN_BASE + RP23XX_POWMAN_INTR_OFFSET)
#define RP23XX_POWMAN_INTE (RP23XX_POWMAN_BASE + RP23XX_POWMAN_INTE_OFFSET)
#define RP23XX_POWMAN_INTF (RP23XX_POWMAN_BASE + RP23XX_POWMAN_INTF_OFFSET)
#define RP23XX_POWMAN_INTS (RP23XX_POWMAN_BASE + RP23XX_POWMAN_INTS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_POWMAN_BADPASSWD (1 << 0)
#define RP23XX_POWMAN_VREG_CTRL_RST_N (1 << 15)
#define RP23XX_POWMAN_VREG_CTRL_UNLOCK (1 << 13)
#define RP23XX_POWMAN_VREG_CTRL_ISOLATE (1 << 12)
#define RP23XX_POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT (1 << 8)
#define RP23XX_POWMAN_VREG_CTRL_HT_TH_MASK (0x00000070)
#define RP23XX_POWMAN_VREG_STS_VOUT_OK (1 << 4)
#define RP23XX_POWMAN_VREG_STS_STARTUP (1 << 0)
#define RP23XX_POWMAN_VREG_UPDATE_IN_PROGRESS (1 << 15)
#define RP23XX_POWMAN_VREG_VSEL_MASK 0x000001f0
#define RP23XX_POWMAN_VREG_HIZ (1 << 1)
#define RP23XX_POWMAN_VREG_LP_ENTRY_VSEL_MASK 0x000001f0
#define RP23XX_POWMAN_VREG_LP_ENTRY_MODE (1 << 2)
#define RP23XX_POWMAN_VREG_LP_ENTRY_HIZ (1 << 1)
#define RP23XX_POWMAN_VREG_LP_EXIT_VSEL_MASK 0x000001f0
#define RP23XX_POWMAN_VREG_LP_EXIT_MODE (1 << 2)
#define RP23XX_POWMAN_VREG_LP_EXIT_HIZ (1 << 1)
#define RP23XX_POWMAN_BOD_CTRL (1 << 12)
#define RP23XX_POWMAN_BOD_CTRL_ISOLATE (1 << 12)
#define RP23XX_POWMAN_BOD_VSEL_MASK 0x000001f0
#define RP23XX_POWMAN_BOD_EN (1 << 0)
#define RP23XX_POWMAN_BOD_LP_ENTRY_VSEL_MASK 0x000001f0
#define RP23XX_POWMAN_BOD_LP_ENTRY_EN (1 << 0)
#define RP23XX_POWMAN_BOD_LP_EXIT_VSEL_MASK 0x000001f0
#define RP23XX_POWMAN_BOD_LP_EXIT_EN (1 << 0)
#define RP23XX_POWMAN_LPOSC_TRIM_MASK 0x000003f0
#define RP23XX_POWMAN_LPOSC_MODE_MASK 0x00000003
#define RP23XX_POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM (1 << 28)
#define RP23XX_POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ (1 << 27)
#define RP23XX_POWMAN_CHIP_RESET_HAD_GLITCH_DETECT (1 << 26)
#define RP23XX_POWMAN_CHIP_RESET_HAD_SWCORE_PD (1 << 25)
#define RP23XX_POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE (1 << 24)
#define RP23XX_POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN (1 << 23)
#define RP23XX_POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC (1 << 22)
#define RP23XX_POWMAN_CHIP_RESET_HAD_RESCUE (1 << 21)
#define RP23XX_POWMAN_CHIP_RESET_HAD_DP_RESET_REQ (1 << 19)
#define RP23XX_POWMAN_CHIP_RESET_HAD_RUN_LOW (1 << 18)
#define RP23XX_POWMAN_CHIP_RESET_HAD_BOR (1 << 17)
#define RP23XX_POWMAN_CHIP_RESET_HAD_POR (1 << 16)
#define RP23XX_POWMAN_CHIP_RESET_RESCUE_FLAG (1 << 4)
#define RP23XX_POWMAN_CHIP_RESET_DOUBLE_TAP (1 << 0)
#define RP23XX_POWMAN_WDSEL_RESET_RSM (1 << 12)
#define RP23XX_POWMAN_WDSEL_RESET_SWCORE (1 << 8)
#define RP23XX_POWMAN_WDSEL_RESET_POWMAN (1 << 4)
#define RP23XX_POWMAN_WDSEL_RESET_POWMAN_ASYNC (1 << 0)
#define RP23XX_POWMAN_SEQ_CFG_USING_FAST_POWCK (1 << 20)
#define RP23XX_POWMAN_SEQ_CFG_USING_BOD_LP (1 << 17)
#define RP23XX_POWMAN_SEQ_CFG_USING_VREG_LP (1 << 16)
#define RP23XX_POWMAN_SEQ_CFG_USE_FAST_POWCK (1 << 12)
#define RP23XX_POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP (1 << 8)
#define RP23XX_POWMAN_SEQ_CFG_USE_BOD_HP (1 << 7)
#define RP23XX_POWMAN_SEQ_CFG_USE_BOD_LP (1 << 6)
#define RP23XX_POWMAN_SEQ_CFG_USE_VREG_HP (1 << 5)
#define RP23XX_POWMAN_SEQ_CFG_USE_VREG_LP (1 << 4)
#define RP23XX_POWMAN_SEQ_CFG_HW_PWRUP_SRAM0 (1 << 1)
#define RP23XX_POWMAN_SEQ_CFG_HW_PWRUP_SRAM1 (1 << 0)
#define RP23XX_POWMAN_STATE_CHANGING (1 << 13)
#define RP23XX_POWMAN_STATE_WAITING (1 << 12)
#define RP23XX_POWMAN_STATE_BAD_HW_REQ (1 << 11)
#define RP23XX_POWMAN_STATE_BAD_SW_REQ (1 << 10)
#define RP23XX_POWMAN_STATE_PWRUP_WHILE_WAITING (1 << 9)
#define RP23XX_POWMAN_STATE_REQ_IGNORED (1 << 8)
#define RP23XX_POWMAN_STATE_REQ_MASK 0x000000f0
#define RP23XX_POWMAN_STATE_CURRENT_MASK 0x0000000f
#define RP23XX_POWMAN_POW_FASTDIV_MASK 0x000007ff
#define RP23XX_POWMAN_POW_DELAY_SRAM_STEP_MASK 0x0000ff00
#define RP23XX_POWMAN_POW_DELAY_XIP_STEP_MASK 0x000000f0
#define RP23XX_POWMAN_POW_DELAY_SWCORE_STEP_MASK 0x0000000f
#define RP23XX_POWMAN_EXT_CTRL0_LP_EXIT_STATE (1 << 14)
#define RP23XX_POWMAN_EXT_CTRL0_LP_ENTRY_STATE (1 << 13)
#define RP23XX_POWMAN_EXT_CTRL0_INIT_STATE (1 << 12)
#define RP23XX_POWMAN_EXT_CTRL0_INIT (1 << 8)
#define RP23XX_POWMAN_EXT_CTRL0_GPIO_SELECT_MASK 0x0000003f
#define RP23XX_POWMAN_EXT_CTRL1_LP_EXIT_STATE (1 << 14)
#define RP23XX_POWMAN_EXT_CTRL1_LP_ENTRY_STATE (1 << 13)
#define RP23XX_POWMAN_EXT_CTRL1_INIT_STATE (1 << 12)
#define RP23XX_POWMAN_EXT_CTRL1_INIT (1 << 8)
#define RP23XX_POWMAN_EXT_CTRL1_GPIO_SELECT_MASK 0x0000003f
#define RP23XX_POWMAN_EXT_TIME_REF_MASK 0x00000013
#define RP23XX_POWMAN_EXT_TIME_REF_DRIVE_LPCK (1 << 4)
#define RP23XX_POWMAN_EXT_TIME_REF_SOURCE_SEL_MASK 0x00000003
#define RP23XX_POWMAN_LPOSC_FREQ_KHZ_INT_MASK 0x0000003f
#define RP23XX_POWMAN_LPOSC_FREQ_KHZ_FRAC_MASK 0x0000ffff
#define RP23XX_POWMAN_XOSC_FREQ_KHZ_INT_MASK 0x0000ffff
#define RP23XX_POWMAN_XOSC_FREQ_KHZ_FRAC_MASK 0x0000ffff
#define RP23XX_POWMAN_SET_TIME_63TO48_MASK 0x0000ffff
#define RP23XX_POWMAN_SET_TIME_47TO32_MASK 0x0000ffff
#define RP23XX_POWMAN_SET_TIME_31TO16_MASK 0x0000ffff
#define RP23XX_POWMAN_SET_TIME_15TO0_MASK 0x0000ffff
#define RP23XX_POWMAN_READ_TIME_UPPER_MASK 0xffffffff
#define RP23XX_POWMAN_READ_TIME_LOWER_MASK 0xffffffff
#define RP23XX_POWMAN_ALARM_TIME_63TO48_MASK 0x0000ffff
#define RP23XX_POWMAN_ALARM_TIME_47TO32_MASK 0x0000ffff
#define RP23XX_POWMAN_ALARM_TIME_31TO16_MASK 0x0000ffff
#define RP23XX_POWMAN_ALARM_TIME_15TO0_MASK 0x0000ffff
#define RP23XX_POWMAN_TIMER_USING_GPIO_1HZ (1 << 19)
#define RP23XX_POWMAN_TIMER_USING_GPIO_1KHZ (1 << 18)
#define RP23XX_POWMAN_TIMER_USING_LPOSC (1 << 17)
#define RP23XX_POWMAN_TIMER_USING_XOSC (1 << 16)
#define RP23XX_POWMAN_TIMER_USE_GPIO_1HZ (1 << 13)
#define RP23XX_POWMAN_TIMER_USE_GPIO_1KHZ (1 << 10)
#define RP23XX_POWMAN_TIMER_USE_XOSC (1 << 9)
#define RP23XX_POWMAN_TIMER_USE_LPOSC (1 << 8)
#define RP23XX_POWMAN_TIMER_ALARM (1 << 6)
#define RP23XX_POWMAN_TIMER_PWRUP_ON_ALARM (1 << 5)
#define RP23XX_POWMAN_TIMER_ALARM_ENAB (1 << 4)
#define RP23XX_POWMAN_TIMER_CLEAR (1 << 2)
#define RP23XX_POWMAN_TIMER_RUN (1 << 1)
#define RP23XX_POWMAN_TIMER_NONSEC_WRITE (1 << 0)
#define RP23XX_POWMAN_PWRUP0_RAW_STATUS (1 << 10)
#define RP23XX_POWMAN_PWRUP0_STATUS (1 << 9)
#define RP23XX_POWMAN_PWRUP0_MODE (1 << 8)
#define RP23XX_POWMAN_PWRUP0_DIRECTION (1 << 7)
#define RP23XX_POWMAN_PWRUP0_ENABLE (1 << 6)
#define RP23XX_POWMAN_PWRUP0_SOURCE_MASK 0x0000003f
#define RP23XX_POWMAN_PWRUP1_RAW_STATUS (1 << 10)
#define RP23XX_POWMAN_PWRUP1_STATUS (1 << 9)
#define RP23XX_POWMAN_PWRUP1_MODE (1 << 8)
#define RP23XX_POWMAN_PWRUP1_DIRECTION (1 << 7)
#define RP23XX_POWMAN_PWRUP1_ENABLE (1 << 6)
#define RP23XX_POWMAN_PWRUP1_SOURCE_MASK 0x0000003f
#define RP23XX_POWMAN_PWRUP2_RAW_STATUS (1 << 10)
#define RP23XX_POWMAN_PWRUP2_STATUS (1 << 9)
#define RP23XX_POWMAN_PWRUP2_MODE (1 << 8)
#define RP23XX_POWMAN_PWRUP2_DIRECTION (1 << 7)
#define RP23XX_POWMAN_PWRUP2_ENABLE (1 << 6)
#define RP23XX_POWMAN_PWRUP2_SOURCE_MASK 0x0000003f
#define RP23XX_POWMAN_PWRUP3_RAW_STATUS (1 << 10)
#define RP23XX_POWMAN_PWRUP3_STATUS (1 << 9)
#define RP23XX_POWMAN_PWRUP3_MODE (1 << 8)
#define RP23XX_POWMAN_PWRUP3_DIRECTION (1 << 7)
#define RP23XX_POWMAN_PWRUP3_ENABLE (1 << 6)
#define RP23XX_POWMAN_PWRUP3_SOURCE_MASK 0x0000003f
#define RP23XX_POWMAN_CURRENT_PWRUP_REQ_MASK 0x0000007f
#define RP23XX_POWMAN_LAST_SWCORE_PWRUP_MASK 0x0000007f
#define RP23XX_POWMAN_DBG_PWRCFG (1 << 0)
#define RP23XX_POWMAN_DBG_PWRCFG_IGNORE (1 << 0)
#define RP23XX_POWMAN_BOOTDIS_MASK 0x00000003
#define RP23XX_POWMAN_BOOTDIS_NEXT (1 << 1)
#define RP23XX_POWMAN_BOOTDIS_NOW (1 << 0)
#define RP23XX_POWMAN_DBGCONFIG_MASK 0x0000000f
#define RP23XX_POWMAN_DBGCONFIG_DP_INSTID_MASK 0x0000000f
#define RP23XX_POWMAN_INTR_PWRUP_WHILE_WAITING (1 << 3)
#define RP23XX_POWMAN_INTR_STATE_REQ_IGNORED (1 << 2)
#define RP23XX_POWMAN_INTR_TIMER (1 << 1)
#define RP23XX_POWMAN_INTR_VREG_OUTPUT_LOW (1 << 0)
#define RP23XX_POWMAN_INTE_PWRUP_WHILE_WAITING (1 << 3)
#define RP23XX_POWMAN_INTE_STATE_REQ_IGNORED (1 << 2)
#define RP23XX_POWMAN_INTE_TIMER (1 << 1)
#define RP23XX_POWMAN_INTE_VREG_OUTPUT_LOW (1 << 0)
#define RP23XX_POWMAN_INTF_PWRUP_WHILE_WAITING (1 << 3)
#define RP23XX_POWMAN_INTF_STATE_REQ_IGNORED (1 << 2)
#define RP23XX_POWMAN_INTF_TIMER (1 << 1)
#define RP23XX_POWMAN_INTF_VREG_OUTPUT_LOW (1 << 0)
#define RP23XX_POWMAN_INTS_PWRUP_WHILE_WAITING (1 << 3)
#define RP23XX_POWMAN_INTS_STATE_REQ_IGNORED (1 << 2)
#define RP23XX_POWMAN_INTS_TIMER (1 << 1)
#define RP23XX_POWMAN_INTS_VREG_OUTPUT_LOW (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_POWMAN_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_psm.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_psm.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PSM_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PSM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_PSM_FRCE_ON_OFFSET 0x000000 /* Force block out of reset (i.e. power it on) */
#define RP23XX_PSM_FRCE_OFF_OFFSET 0x000004 /* Force into reset (i.e. power it off) */
#define RP23XX_PSM_WDSEL_OFFSET 0x000008 /* Set to 1 if this peripheral should be reset when the watchdog fires. */
#define RP23XX_PSM_DONE_OFFSET 0x00000c /* Indicates the peripheral's registers are ready to access. */
/* Register definitions *****************************************************/
#define RP23XX_PSM_FRCE_ON (RP23XX_PSM_BASE + RP23XX_PSM_FRCE_ON_OFFSET)
#define RP23XX_PSM_FRCE_OFF (RP23XX_PSM_BASE + RP23XX_PSM_FRCE_OFF_OFFSET)
#define RP23XX_PSM_WDSEL (RP23XX_PSM_BASE + RP23XX_PSM_WDSEL_OFFSET)
#define RP23XX_PSM_DONE (RP23XX_PSM_BASE + RP23XX_PSM_DONE_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_PSM_PROC1 (1 << 24)
#define RP23XX_PSM_PROC0 (1 << 23)
#define RP23XX_PSM_ACCESSCTRL (1 << 22)
#define RP23XX_PSM_SIO (1 << 21)
#define RP23XX_PSM_XIP (1 << 20)
#define RP23XX_PSM_SRAM9 (1 << 19)
#define RP23XX_PSM_SRAM8 (1 << 18)
#define RP23XX_PSM_SRAM7 (1 << 17)
#define RP23XX_PSM_SRAM6 (1 << 16)
#define RP23XX_PSM_SRAM5 (1 << 15)
#define RP23XX_PSM_SRAM4 (1 << 14)
#define RP23XX_PSM_SRAM3 (1 << 13)
#define RP23XX_PSM_SRAM2 (1 << 12)
#define RP23XX_PSM_SRAM1 (1 << 11)
#define RP23XX_PSM_SRAM0 (1 << 10)
#define RP23XX_PSM_BOOTRAM (1 << 9)
#define RP23XX_PSM_ROM (1 << 8)
#define RP23XX_PSM_BUSFABRIC (1 << 7)
#define RP23XX_PSM_PSM_READY (1 << 6)
#define RP23XX_PSM_CLOCKS (1 << 5)
#define RP23XX_PSM_RESETS (1 << 4)
#define RP23XX_PSM_XOSC (1 << 3)
#define RP23XX_PSM_ROSC (1 << 2)
#define RP23XX_PSM_OTP (1 << 1)
#define RP23XX_PSM_PROC_COLD (1 << 0)
#define RP23XX_PSM_WDSEL_BITS 0x01ffffff
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_PSM_H */

138
arch/risc-v/src/rp23xx-rv/hardware/rp23xx_pwm.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_pwm.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_PWM_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_PWM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_RV_PWM_CSR_OFFSET(n) (0x000000 + (n) * 20) /* PWM control and status register */
#define RP23XX_RV_PWM_DIV_OFFSET(n) (0x000004 + (n) * 20) /* PWM clock divisor register */
#define RP23XX_RV_PWM_CTR_OFFSET(n) (0x000008 + (n) * 20) /* PWM counter register */
#define RP23XX_RV_PWM_CC_OFFSET(n) (0x00000c + (n) * 20) /* PWM compare register */
#define RP23XX_RV_PWM_TOP_OFFSET(n) (0x000010 + (n) * 20) /* PWM wrap value register */
#define RP23XX_RV_PWM_EN_OFFSET 0x0000f0 /* PWM enable register */
#define RP23XX_RV_PWM_INTR_OFFSET 0x0000f4 /* PWM raw interrupt register */
#define RP23XX_RV_PWM_IRQ0_INTE_OFFSET 0x0000f8 /* PWM interrupt enable register */
#define RP23XX_RV_PWM_IRQ0_INTF_OFFSET 0x0000fC /* PWM interrupt force register */
#define RP23XX_RV_PWM_IRQ0_INTS_OFFSET 0x000100 /* PWM interrupt status register */
#define RP23XX_RV_PWM_IRQ1_INTE_OFFSET 0x000104
#define RP23XX_RV_PWM_IRQ1_INTF_OFFSET 0x000108
#define RP23XX_RV_PWM_IRQ1_INTS_OFFSET 0x00010c
/* Register definitions *****************************************************/
#define RP23XX_RV_PWM_CSR(n) (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_CSR_OFFSET(n))
#define RP23XX_RV_PWM_DIV(n) (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_DIV_OFFSET(n))
#define RP23XX_RV_PWM_CTR(n) (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_CTR_OFFSET(n))
#define RP23XX_RV_PWM_CC(n) (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_CC_OFFSET(n))
#define RP23XX_RV_PWM_TOP(n) (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_TOP_OFFSET(n))
#define RP23XX_RV_PWM_EN (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_EN_OFFSET)
#define RP23XX_RV_PWM_INTR (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_INTR_OFFSET)
#define RP23XX_RV_PWM_IRQ0_INTE (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_IRQ0_INTE_OFFSET)
#define RP23XX_RV_PWM_IRQ0_INTF (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_IRQ0_INTF_OFFSET)
#define RP23XX_RV_PWM_IRQ0_INTS (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_IRQ0_INTS_OFFSET)
#define RP23XX_RV_PWM_IRQ1_INTE (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_IRQ1_INTE_OFFSET)
#define RP23XX_RV_PWM_IRQ1_INTF (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_IRQ1_INTF_OFFSET)
#define RP23XX_RV_PWM_IRQ1_INTS (RP23XX_RV_PWM_BASE + RP23XX_RV_PWM_IRQ1_INTS_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_RV_PWM_CSR_PH_ADV (1 << 7) /* advance phase of counter by one */
#define RP23XX_RV_PWM_CSR_PH_RET (1 << 6) /* retard phase of counter by one */
#define RP23XX_RV_PWM_CSR_DIVMODE_SHIFT (4) /* divisor mode */
#define RP23XX_RV_PWM_CSR_DIVMODE_MASK (0x03 << RP23XX_RV_PWM_CSR_DIVMODE_SHIFT)
#define RP23XX_RV_PWM_CSR_B_INV (1 << 3) /* invert output B */
#define RP23XX_RV_PWM_CSR_A_INV (1 << 2) /* invert output A */
#define RP23XX_RV_PWM_CSR_PH_CORRECT (1 << 1) /* enable phase correct modulation */
#define RP23XX_RV_PWM_CSR_EN (1 << 0) /* enable the PWM channel */
#define RP23XX_PWN_CSR_DIVMODE_DIV 0x00
#define RP23XX_PWN_CSR_DIVMODE_LEVEL 0x01
#define RP23XX_PWN_CSR_DIVMODE_RISE 0x02
#define RP23XX_PWN_CSR_DIVMODE_FALL 0x03
#define RP23XX_RV_PWM_DIV_INT_SHIFT (4) /* divisor integer part */
#define RP23XX_RV_PWM_DIV_INT_MASK (0xff << RP23XX_RV_PWM_DIV_INT_SHIFT)
#define RP23XX_RV_PWM_DIV_FRAC_SHIFT (0) /* divisor fraction part */
#define RP23XX_RV_PWM_DIV_FRAC_MASK (0x0f << RP23XX_RV_PWM_DIV_FRAC_SHIFT)
#define RP23XX_RV_PWM_CC_B_SHIFT (16) /* channel B compare register */
#define RP23XX_RV_PWM_CC_B_MASK (0xffff << RP23XX_RV_PWM_CC_B_SHIFT)
#define RP23XX_RV_PWM_CC_A_SHIFT (0) /* channel A compare register */
#define RP23XX_RV_PWM_CC_A_MASK (0xffff << RP23XX_RV_PWM_CC_A_SHIFT)
#define RP23XX_RV_PWM_TOP_SHIFT (0) /* channel A compare register */
#define RP23XX_RV_PWM_TOP_MASK (0xffff << RP23XX_RV_PWM_TOP_SHIFT)
/* Bit mask for ENA, INTR, INTE, INTF, and INTS registers */
#define RP23XX_RV_PWM_CH11 (1 << 11) /* PWM channel 11 */
#define RP23XX_RV_PWM_CH10 (1 << 10) /* PWM channel 10 */
#define RP23XX_RV_PWM_CH9 (1 << 9) /* PWM channel 9 */
#define RP23XX_RV_PWM_CH8 (1 << 8) /* PWM channel 8 */
#define RP23XX_RV_PWM_CH7 (1 << 7) /* PWM channel 7 */
#define RP23XX_RV_PWM_CH6 (1 << 6) /* PWM channel 6 */
#define RP23XX_RV_PWM_CH5 (1 << 5) /* PWM channel 5 */
#define RP23XX_RV_PWM_CH4 (1 << 4) /* PWM channel 4 */
#define RP23XX_RV_PWM_CH3 (1 << 3) /* PWM channel 3 */
#define RP23XX_RV_PWM_CH2 (1 << 2) /* PWM channel 2 */
#define RP23XX_RV_PWM_CH1 (1 << 1) /* PWM channel 1 */
#define RP23XX_RV_PWM_CH0 (1 << 0) /* PWM channel 0 */
/****************************************************************************
* The following IOCTL values set additional flags in the RP23XX PWM
* device.
****************************************************************************/
/****************************************************************************
* PWMIOC_RP23XX_SETINVERTPULSE sets the pulse invert flag.
*
* The argument is an integer where:
* bit zero is set to invert channel A
* bit one is set to invert channel B
****************************************************************************/
#define PWMIOC_RP23XX_SETINVERTPULSE _PWMIOC(0x80)
#define PWMIOC_RP23XX_GETINVERTPULSE _PWMIOC(0x81)
/****************************************************************************
* PWMIOC_RP23XX_SETPHASECORRECT sets phase correct flags.
*
* The argument is an integer which if non-zero sets the phase correct flag.
****************************************************************************/
#define PWMIOC_RP23XX_SETPHASECORRECT _PWMIOC(0x82)
#define PWMIOC_RP23XX_GETPHASECORRECT _PWMIOC(0x83)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_PWM_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_qmi.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_QMI_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_QMI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_QMI_DIRECT_CSR_OFFSET 0x00000000
#define RP23XX_QMI_DIRECT_TX_OFFSET 0x00000004
#define RP23XX_QMI_DIRECT_RX_OFFSET 0x00000008
#define RP23XX_QMI_M0_TIMING_OFFSET 0x0000000c
#define RP23XX_QMI_M0_RFMT_OFFSET 0x00000010
#define RP23XX_QMI_M0_RCMD_OFFSET 0x00000014
#define RP23XX_QMI_M0_WFMT_OFFSET 0x00000018
#define RP23XX_QMI_M0_WCMD_OFFSET 0x0000001c
#define RP23XX_QMI_M1_TIMING_OFFSET 0x00000020
#define RP23XX_QMI_M1_RFMT_OFFSET 0x00000024
#define RP23XX_QMI_M1_RCMD_OFFSET 0x00000028
#define RP23XX_QMI_M1_WFMT_OFFSET 0x0000002c
#define RP23XX_QMI_M1_WCMD_OFFSET 0x00000030
#define RP23XX_QMI_ATRANS_OFFSET(n) (0x00000034 + (n) * 4)
/* Register definitions *****************************************************/
#define RP23XX_QMI_DIRECT_CSR (RP23XX_QMI_BASE + RP23XX_QMI_DIRECT_CSR_OFFSET)
#define RP23XX_QMI_DIRECT_TX (RP23XX_QMI_BASE + RP23XX_QMI_DIRECT_TX_OFFSET)
#define RP23XX_QMI_DIRECT_RX (RP23XX_QMI_BASE + RP23XX_QMI_DIRECT_RX_OFFSET)
#define RP23XX_QMI_M0_TIMING (RP23XX_QMI_BASE + RP23XX_QMI_M0_TIMING_OFFSET)
#define RP23XX_QMI_M0_RFMT (RP23XX_QMI_BASE + RP23XX_QMI_M0_RFMT_OFFSET)
#define RP23XX_QMI_M0_RCMD (RP23XX_QMI_BASE + RP23XX_QMI_M0_RCMD_OFFSET)
#define RP23XX_QMI_M0_WFMT (RP23XX_QMI_BASE + RP23XX_QMI_M0_WFMT_OFFSET)
#define RP23XX_QMI_M0_WCMD (RP23XX_QMI_BASE + RP23XX_QMI_M0_WCMD_OFFSET)
#define RP23XX_QMI_M1_TIMING (RP23XX_QMI_BASE + RP23XX_QMI_M1_TIMING_OFFSET)
#define RP23XX_QMI_M1_RFMT (RP23XX_QMI_BASE + RP23XX_QMI_M1_RFMT_OFFSET)
#define RP23XX_QMI_M1_RCMD (RP23XX_QMI_BASE + RP23XX_QMI_M1_RCMD_OFFSET)
#define RP23XX_QMI_M1_WFMT (RP23XX_QMI_BASE + RP23XX_QMI_M1_WFMT_OFFSET)
#define RP23XX_QMI_M1_WCMD (RP23XX_QMI_BASE + RP23XX_QMI_M1_WCMD_OFFSET)
#define RP23XX_QMI_ATRANS(n) (RP23XX_QMI_BASE + RP23XX_QMI_ATRANS_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_QMI_DIRECT_CSR_RXDELAY_SHIFT (30) /* Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) */
#define RP23XX_QMI_DIRECT_CSR_RXDELAY_MASK (0x3 << RP23XX_QMI_DIRECT_CSR_RXDELAY_SHIFT)
#define RP23XX_QMI_DIRECT_CSR_CLKDIV_SHIFT (22) /* Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0 */
#define RP23XX_QMI_DIRECT_CSR_CLKDIV_MASK (0xff << RP23XX_QMI_DIRECT_CSR_CLKDIV_SHIFT)
#define RP23XX_QMI_DIRECT_CSR_RXLEVEL_SHIFT (18) /* Current level of DIRECT_RX FIFO */
#define RP23XX_QMI_DIRECT_CSR_RXLEVEL_MASK (0x7 << RP23XX_QMI_DIRECT_CSR_RXLEVEL_SHIFT)
#define RP23XX_QMI_DIRECT_CSR_RXFULL (1 << 17) /* When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full */
#define RP23XX_QMI_DIRECT_CSR_RXEMPTY (1 << 16) /* When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined */
#define RP23XX_QMI_DIRECT_CSR_TXLEVEL_SHIFT (12) /* Current level of DIRECT_TX FIFO */
#define RP23XX_QMI_DIRECT_CSR_TXLEVEL_MASK (0x7 << RP23XX_QMI_DIRECT_CSR_TXLEVEL_SHIFT)
#define RP23XX_QMI_DIRECT_CSR_TXEMPTY (1 << 11) /* When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes */
#define RP23XX_QMI_DIRECT_CSR_TXFULL (1 << 10) /* When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored */
#define RP23XX_QMI_DIRECT_CSR_AUTO_CS1N (1 << 7) /* When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set */
#define RP23XX_QMI_DIRECT_CSR_AUTO_CS0N (1 << 6) /* When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set */
#define RP23XX_QMI_DIRECT_CSR_ASSERT_CS1N (1 << 3) /* When 1, assert (i.e. drive low) the CS1n chip select line */
#define RP23XX_QMI_DIRECT_CSR_ASSERT_CS0N (1 << 2) /* When 1, assert (i.e. drive low) the CS0n chip select line */
#define RP23XX_QMI_DIRECT_CSR_BUSY (1 << 1) /* Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted */
#define RP23XX_QMI_DIRECT_CSR_EN (1 << 0) /* Enable direct mode */
#define RP23XX_QMI_DIRECT_TX_NOPUSH (1 << 20) /* Inhibit the RX FIFO push that would correspond to this TX FIFO entry */
#define RP23XX_QMI_DIRECT_TX_OE (1 << 19) /* Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input */
#define RP23XX_QMI_DIRECT_TX_DWIDTH (1 << 18) /* Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely */
#define RP23XX_QMI_DIRECT_TX_IWIDTH_SHIFT (16) /* Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely */
#define RP23XX_QMI_DIRECT_TX_IWIDTH_MASK (0x3 << RP23XX_QMI_DIRECT_TX_IWIDTH_SHIFT)
#define RP23XX_QMI_DIRECT_TX_DATA_MASK (0xffff) /* Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first. */
#define RP23XX_QMI_DIRECT_RX_MASK (0xffff) /* With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. */
#define RP23XX_QMI_TIMING_COOLDOWN_SHIFT (30) /* Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power */
#define RP23XX_QMI_TIMING_COOLDOWN_MASK (0x3 << RP23XX_QMI_M0_TIMING_COOLDOWN_SHIFT)
#define RP23XX_QMI_TIMING_PAGEBREAK_SHIFT (28) /* When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary */
#define RP23XX_QMI_TIMING_PAGEBREAK_MASK (0x3 << RP23XX_QMI_M0_TIMING_PAGEBREAK_SHIFT)
#define RP23XX_QMI_TIMING_SELECT_SETUP (1 << 25) /* Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK */
#define RP23XX_QMI_TIMING_SELECT_HOLD_SHIFT (23) /* Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window’s chip select */
#define RP23XX_QMI_TIMING_SELECT_HOLD_MASK (0x3 << RP23XX_QMI_M0_TIMING_SELECT_HOLD_SHIFT)
#define RP23XX_QMI_TIMING_MAX_SELECT_SHIFT (17) /* Enforce a maximum assertion duration for this window’s chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN) */
#define RP23XX_QMI_TIMING_MAX_SELECT_MASK (0x3f << RP23XX_QMI_M0_TIMING_MAX_SELECT_SHIFT)
#define RP23XX_QMI_TIMING_MIN_DESELECT_SHIFT (12) /* After this window’s chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin */
#define RP23XX_QMI_TIMING_MIN_DESELECT_MASK (0x1f << RP23XX_QMI_M0_TIMING_MIN_DESELECT_SHIFT)
#define RP23XX_QMI_TIMING_RXDELAY_SHIFT (8) /* Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register */
#define RP23XX_QMI_TIMING_RXDELAY_MASK (0x7 << RP23XX_QMI_M0_TIMING_RXDELAY_SHIFT)
#define RP23XX_QMI_TIMING_CLKDIV_MASK (0x000000ff) /* Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0 */
#define RP23XX_QMI_FMT_DTR (1 << 28) /* Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch */
#define RP23XX_QMI_FMT_DUMMY_LEN_SHIFT (16) /* Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) */
#define RP23XX_QMI_FMT_DUMMY_LEN_MASK (0x7 << RP23XX_QMI_M0_RFMT_DUMMY_LEN_SHIFT)
#define RP23XX_QMI_FMT_SUFFIX_LEN_SHIFT (14) /* Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) */
#define RP23XX_QMI_FMT_SUFFIX_LEN_MASK (0x3 << RP23XX_QMI_M0_RFMT_SUFFIX_LEN_SHIFT)
#define RP23XX_QMI_FMT_PREFIX_LEN (1 << 12) /* Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) */
#define RP23XX_QMI_FMT_DATA_WIDTH_SHIFT (8) /* The width used for the data transfer */
#define RP23XX_QMI_FMT_DATA_WIDTH_MASK (0x3 << RP23XX_QMI_M0_RFMT_DATA_WIDTH_SHIFT)
#define RP23XX_QMI_FMT_DUMMY_WIDTH_SHIFT (6) /* The width used for the dummy phase, if any */
#define RP23XX_QMI_FMT_DUMMY_WIDTH_MASK (0x3 << RP23XX_QMI_M0_RFMT_DUMMY_WIDTH_SHIFT)
#define RP23XX_QMI_FMT_SUFFIX_WIDTH_SHIFT (4) /* The width used for the post-address command suffix, if any */
#define RP23XX_QMI_FMT_SUFFIX_WIDTH_MASK (0x4 << RP23XX_QMI_M0_RFMT_SUFFIX_WIDTH_SHIFT)
#define RP23XX_QMI_FMT_ADDR_WIDTH_SHIFT (2) /* The transfer width used for the address. The address phase always transfers 24 bits in total */
#define RP23XX_QMI_FMT_ADDR_WIDTH_MASK (0x3 << RP23XX_QMI_M0_RFMT_ADDR_WIDTH_SHIFT)
#define RP23XX_QMI_FMT_PREFIX_WIDTH_MASK (0x00000003) /* The transfer width used for the command prefix, if any */
#define RP23XX_QMI_CMD_SUFFIX_SHIFT (8) /* The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero */
#define RP23XX_QMI_CMD_SUFFIX_MASK (0xff << RP23XX_QMI_CMD_SUFFIX_SHIFT)
#define RP23XX_QMI_CMD_PREFIX_MASK (0x000000ff) /* The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero */
#define RP23XX_QMI_ATRANS_SIZE_SHIFT (16) /* Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). */
#define RP23XX_QMI_ATRANS_SIZE_MASK (0x7ff << RP23XX_QMI_ATRANS_SIZE_SHIFT)
#define RP23XX_QMI_ATRANS_BASE_MASK (0xfff) /* Physical address base for this virtual address range, in units of 4 kiB (one flash sector) */
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_QMI_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_resets.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RESETS_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RESETS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_RESETS_RESET_OFFSET 0x000000 /* Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. */
#define RP23XX_RESETS_WDSEL_OFFSET 0x000004 /* Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. */
#define RP23XX_RESETS_RESET_DONE_OFFSET 0x000008 /* Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. */
/* Register definitions *****************************************************/
#define RP23XX_RESETS_RESET (RP23XX_RESETS_BASE + RP23XX_RESETS_RESET_OFFSET)
#define RP23XX_RESETS_WDSEL (RP23XX_RESETS_BASE + RP23XX_RESETS_WDSEL_OFFSET)
#define RP23XX_RESETS_RESET_DONE (RP23XX_RESETS_BASE + RP23XX_RESETS_RESET_DONE_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_RESETS_RESET_MASK (0x1fffffff)
#define RP23XX_RESETS_RESET_USBCTRL (1 << 28)
#define RP23XX_RESETS_RESET_UART1 (1 << 27)
#define RP23XX_RESETS_RESET_UART0 (1 << 26)
#define RP23XX_RESETS_RESET_TRNG (1 << 25)
#define RP23XX_RESETS_RESET_TIMER1 (1 << 24)
#define RP23XX_RESETS_RESET_TIMER0 (1 << 23)
#define RP23XX_RESETS_RESET_TBMAN (1 << 22)
#define RP23XX_RESETS_RESET_SYSINFO (1 << 21)
#define RP23XX_RESETS_RESET_SYSCFG (1 << 20)
#define RP23XX_RESETS_RESET_SPI1 (1 << 19)
#define RP23XX_RESETS_RESET_SPI0 (1 << 18)
#define RP23XX_RESETS_RESET_SHA256 (1 << 17)
#define RP23XX_RESETS_RESET_PWM (1 << 16)
#define RP23XX_RESETS_RESET_PLL_USB (1 << 15)
#define RP23XX_RESETS_RESET_PLL_SYS (1 << 14)
#define RP23XX_RESETS_RESET_PIO2 (1 << 13)
#define RP23XX_RESETS_RESET_PIO1 (1 << 12)
#define RP23XX_RESETS_RESET_PIO0 (1 << 11)
#define RP23XX_RESETS_RESET_PADS_QSPI (1 << 10)
#define RP23XX_RESETS_RESET_PADS_BANK0 (1 << 9)
#define RP23XX_RESETS_RESET_JTAG (1 << 8)
#define RP23XX_RESETS_RESET_IO_QSPI (1 << 7)
#define RP23XX_RESETS_RESET_IO_BANK0 (1 << 6)
#define RP23XX_RESETS_RESET_I2C1 (1 << 5)
#define RP23XX_RESETS_RESET_I2C0 (1 << 4)
#define RP23XX_RESETS_RESET_HSTX (1 << 3)
#define RP23XX_RESETS_RESET_DMA (1 << 2)
#define RP23XX_RESETS_RESET_BUSCTRL (1 << 1)
#define RP23XX_RESETS_RESET_ADC (1 << 0)
#define RP23XX_RESETS_WDSEL_USBCTRL (1 << 28)
#define RP23XX_RESETS_WDSEL_UART1 (1 << 27)
#define RP23XX_RESETS_WDSEL_UART0 (1 << 26)
#define RP23XX_RESETS_WDSEL_TRNG (1 << 25)
#define RP23XX_RESETS_WDSEL_TIMER1 (1 << 24)
#define RP23XX_RESETS_WDSEL_TIMER0 (1 << 23)
#define RP23XX_RESETS_WDSEL_TBMAN (1 << 22)
#define RP23XX_RESETS_WDSEL_SYSINFO (1 << 21)
#define RP23XX_RESETS_WDSEL_SYSCFG (1 << 20)
#define RP23XX_RESETS_WDSEL_SPI1 (1 << 19)
#define RP23XX_RESETS_WDSEL_SPI0 (1 << 18)
#define RP23XX_RESETS_WDSEL_SHA256 (1 << 17)
#define RP23XX_RESETS_WDSEL_PWM (1 << 16)
#define RP23XX_RESETS_WDSEL_PLL_USB (1 << 15)
#define RP23XX_RESETS_WDSEL_PLL_SYS (1 << 14)
#define RP23XX_RESETS_WDSEL_PIO2 (1 << 13)
#define RP23XX_RESETS_WDSEL_PIO1 (1 << 12)
#define RP23XX_RESETS_WDSEL_PIO0 (1 << 11)
#define RP23XX_RESETS_WDSEL_PADS_QSPI (1 << 10)
#define RP23XX_RESETS_WDSEL_PADS_BANK0 (1 << 9)
#define RP23XX_RESETS_WDSEL_JTAG (1 << 8)
#define RP23XX_RESETS_WDSEL_IO_QSPI (1 << 7)
#define RP23XX_RESETS_WDSEL_IO_BANK0 (1 << 6)
#define RP23XX_RESETS_WDSEL_I2C1 (1 << 5)
#define RP23XX_RESETS_WDSEL_I2C0 (1 << 4)
#define RP23XX_RESETS_WDSEL_HSTX (1 << 3)
#define RP23XX_RESETS_WDSEL_DMA (1 << 2)
#define RP23XX_RESETS_WDSEL_BUSCTRL (1 << 1)
#define RP23XX_RESETS_WDSEL_ADC (1 << 0)
#define RP23XX_RESETS_RESET_DONE_USBCTRL (1 << 28)
#define RP23XX_RESETS_RESET_DONE_UART1 (1 << 27)
#define RP23XX_RESETS_RESET_DONE_UART0 (1 << 26)
#define RP23XX_RESETS_RESET_DONE_TRNG (1 << 25)
#define RP23XX_RESETS_RESET_DONE_TIMER1 (1 << 24)
#define RP23XX_RESETS_RESET_DONE_TIMER0 (1 << 23)
#define RP23XX_RESETS_RESET_DONE_TBMAN (1 << 22)
#define RP23XX_RESETS_RESET_DONE_SYSINFO (1 << 21)
#define RP23XX_RESETS_RESET_DONE_SYSCFG (1 << 20)
#define RP23XX_RESETS_RESET_DONE_SPI1 (1 << 19)
#define RP23XX_RESETS_RESET_DONE_SPI0 (1 << 18)
#define RP23XX_RESETS_RESET_DONE_SHA256 (1 << 17)
#define RP23XX_RESETS_RESET_DONE_PWM (1 << 16)
#define RP23XX_RESETS_RESET_DONE_PLL_USB (1 << 15)
#define RP23XX_RESETS_RESET_DONE_PLL_SYS (1 << 14)
#define RP23XX_RESETS_RESET_DONE_PIO2 (1 << 13)
#define RP23XX_RESETS_RESET_DONE_PIO1 (1 << 12)
#define RP23XX_RESETS_RESET_DONE_PIO0 (1 << 11)
#define RP23XX_RESETS_RESET_DONE_PADS_QSPI (1 << 10)
#define RP23XX_RESETS_RESET_DONE_PADS_BANK0 (1 << 9)
#define RP23XX_RESETS_RESET_DONE_JTAG (1 << 8)
#define RP23XX_RESETS_RESET_DONE_IO_QSPI (1 << 7)
#define RP23XX_RESETS_RESET_DONE_IO_BANK0 (1 << 6)
#define RP23XX_RESETS_RESET_DONE_I2C1 (1 << 5)
#define RP23XX_RESETS_RESET_DONE_I2C0 (1 << 4)
#define RP23XX_RESETS_RESET_DONE_HSTX (1 << 3)
#define RP23XX_RESETS_RESET_DONE_DMA (1 << 2)
#define RP23XX_RESETS_RESET_DONE_BUSCTRL (1 << 1)
#define RP23XX_RESETS_RESET_DONE_ADC (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RESETS_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_rosc.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_ROSC_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_ROSC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_ROSC_CTRL_OFFSET 0x00000000
#define RP23XX_ROSC_FREQA_OFFSET 0x00000004
#define RP23XX_ROSC_FREQB_OFFSET 0x00000008
#define RP23XX_ROSC_RANDOM_OFFSET 0x0000000c
#define RP23XX_ROSC_DORMANT_OFFSET 0x00000010
#define RP23XX_ROSC_DIV_OFFSET 0x00000014
#define RP23XX_ROSC_PHASE_OFFSET 0x00000018
#define RP23XX_ROSC_STATUS_OFFSET 0x0000001c
#define RP23XX_ROSC_RANDOMBIT_OFFSET 0x00000020
#define RP23XX_ROSC_COUNT_OFFSET 0x00000024
/* Register definitions *****************************************************/
#define RP23XX_ROSC_CTRL (RP23XX_ROSC_BASE + RP23XX_ROSC_CTRL_OFFSET)
#define RP23XX_ROSC_FREQA (RP23XX_ROSC_BASE + RP23XX_ROSC_FREQA_OFFSET)
#define RP23XX_ROSC_FREQB (RP23XX_ROSC_BASE + RP23XX_ROSC_FREQB_OFFSET)
#define RP23XX_ROSC_RANDOM (RP23XX_ROSC_BASE + RP23XX_ROSC_RANDOM_OFFSET)
#define RP23XX_ROSC_DORMANT (RP23XX_ROSC_BASE + RP23XX_ROSC_DORMANT_OFFSET)
#define RP23XX_ROSC_DIV (RP23XX_ROSC_BASE + RP23XX_ROSC_DIV_OFFSET)
#define RP23XX_ROSC_PHASE (RP23XX_ROSC_BASE + RP23XX_ROSC_PHASE_OFFSET)
#define RP23XX_ROSC_STATUS (RP23XX_ROSC_BASE + RP23XX_ROSC_STATUS_OFFSET)
#define RP23XX_ROSC_RANDOMBIT (RP23XX_ROSC_BASE + RP23XX_ROSC_RANDOMBIT_OFFSET)
#define RP23XX_ROSC_COUNT (RP23XX_ROSC_BASE + RP23XX_ROSC_COUNT_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_ROSC_CTRL_ENABLE_SHIFT (12) /* On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. */
#define RP23XX_ROSC_CTRL_ENABLE_MASK (0xfff << RP23XX_ROSC_CTRL_ENABLE_SHIFT)
#define RP23XX_ROSC_CTRL_ENABLE_DISABLE (0xd1e << RP23XX_ROSC_CTRL_ENABLE_SHIFT)
#define RP23XX_ROSC_CTRL_ENABLE_ENABLE (0xfab << RP23XX_ROSC_CTRL_ENABLE_SHIFT)
#define RP23XX_ROSC_CTRL_FREQ_RANGE_MASK (0xfff)
#define RP23XX_ROSC_CTRL_FREQ_RANGE_LOW (0xfa4)
#define RP23XX_ROSC_CTRL_FREQ_RANGE_MEDIUM (0xfa5)
#define RP23XX_ROSC_CTRL_FREQ_RANGE_HIGH (0xfa7)
#define RP23XX_ROSC_CTRL_FREQ_RANGE_TOOHIGH (0xfa6)
#define RP23XX_ROSC_FREQA_PASSWD_SHIFT (16) /* Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 */
#define RP23XX_ROSC_FREQA_PASSWD_MASK (0xffff << RP23XX_ROSC_FREQA_PASSWD_SHIFT)
#define RP23XX_ROSC_FREQA_PASSWD_PASS (0x9696 << RP23XX_ROSC_FREQA_PASSWD_SHIFT)
#define RP23XX_ROSC_FREQA_DS3_SHIFT (12) /* Stage 3 drive strength */
#define RP23XX_ROSC_FREQA_DS3_MASK (0x07 << RP23XX_ROSC_FREQA_DS3_SHIFT)
#define RP23XX_ROSC_FREQA_DS2_SHIFT (8) /* Stage 2 drive strength */
#define RP23XX_ROSC_FREQA_DS2_MASK (0x07 << RP23XX_ROSC_FREQA_DS2_SHIFT)
#define RP23XX_ROSC_FREQA_DS1_SHIFT (4) /* Stage 1 drive strength */
#define RP23XX_ROSC_FREQA_DS1_MASK (0x07 << RP23XX_ROSC_FREQA_DS1_SHIFT)
#define RP23XX_ROSC_FREQA_DS0_MASK (0x07) /* Stage 0 drive strength */
#define RP23XX_ROSC_FREQB_PASSWD_SHIFT (16) /* Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 */
#define RP23XX_ROSC_FREQB_PASSWD_MASK (0xffff << RP23XX_ROSC_FREQB_PASSWD_SHIFT)
#define RP23XX_ROSC_FREQB_PASSWD_PASS (0x9696 << RP23XX_ROSC_FREQB_PASSWD_SHIFT)
#define RP23XX_ROSC_FREQB_DS7_SHIFT (12) /* Stage 7 drive strength */
#define RP23XX_ROSC_FREQB_DS7_MASK (0x07 << RP23XX_ROSC_FREQB_DS7_SHIFT)
#define RP23XX_ROSC_FREQB_DS6_SHIFT (8) /* Stage 6 drive strength */
#define RP23XX_ROSC_FREQB_DS6_MASK (0x07 << RP23XX_ROSC_FREQB_DS6_SHIFT)
#define RP23XX_ROSC_FREQB_DS5_SHIFT (4) /* Stage 5 drive strength */
#define RP23XX_ROSC_FREQB_DS5_MASK (0x07 << RP23XX_ROSC_FREQB_DS5_SHIFT)
#define RP23XX_ROSC_FREQB_DS4_MASK (0x07) /* Stage 4 drive strength */
#define RP23XX_ROSC_DORMANT_DORMANT (0x636f6d61)
#define RP23XX_ROSC_DORMANT_WAKE (0x77616b65)
#define RP23XX_ROSC_DIV_MASK (0xffff)
#define RP23XX_ROSC_DIV_PASS (0xaa00)
#define RP23XX_ROSC_PHASE_PASSWD_SHIFT (4) /* set to 0xaa0 any other value enables the output with shift=0 */
#define RP23XX_ROSC_PHASE_PASSWD_MASK (0xff << RP23XX_ROSC_PHASE_PASSWD_SHIFT)
#define RP23XX_ROSC_PHASE_ENABLE (1 << 3) /* enable the phase-shifted output this can be changed on-the-fly */
#define RP23XX_ROSC_PHASE_FLIP (1 << 2) /* invert the phase-shifted output this is ignored when div=1 */
#define RP23XX_ROSC_PHASE_SHIFT_MASK (0x03) /* phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1 */
#define RP23XX_ROSC_STATUS_STABLE (1 << 31) /* Oscillator is running and stable */
#define RP23XX_ROSC_STATUS_BADWRITE (1 << 24) /* An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT */
#define RP23XX_ROSC_STATUS_DIV_RUNNING (1 << 16) /* post-divider is running this resets to 0 but transitions to 1 during chip startup */
#define RP23XX_ROSC_STATUS_ENABLED (1 << 12) /* Oscillator is enabled but not necessarily running and stable this resets to 0 but transitions to 1 during chip startup */
#define RP23XX_ROSC_RANDOMBIT_MASK (1 << 0)
#define RP23XX_ROSC_COUNT_MASK (0xffff)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_ROSC_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_rp_ap.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RP_AP_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RP_AP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define RP23XX_RP_AP_CTRL_OFFSET 0x00000000
#define RP23XX_RP_AP_CTRL_BITS 0xc000007f
#define RP23XX_RP_AP_CTRL_RESET 0x00000000
#define RP23XX_RP_AP_CTRL_RESCUE_RESTART_RESET 0x0
#define RP23XX_RP_AP_CTRL_RESCUE_RESTART_BITS 0x80000000
#define RP23XX_RP_AP_CTRL_RESCUE_RESTART_MSB 31
#define RP23XX_RP_AP_CTRL_RESCUE_RESTART_LSB 31
#define RP23XX_RP_AP_CTRL_RESCUE_RESTART_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_SPARE_RESET 0x0
#define RP23XX_RP_AP_CTRL_SPARE_BITS 0x40000000
#define RP23XX_RP_AP_CTRL_SPARE_MSB 30
#define RP23XX_RP_AP_CTRL_SPARE_LSB 30
#define RP23XX_RP_AP_CTRL_SPARE_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_RESET 0x0
#define RP23XX_RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_BITS 0x00000040
#define RP23XX_RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_MSB 6
#define RP23XX_RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_LSB 6
#define RP23XX_RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_LPOSC_STABLE_FRCE_RESET 0x0
#define RP23XX_RP_AP_CTRL_LPOSC_STABLE_FRCE_BITS 0x00000020
#define RP23XX_RP_AP_CTRL_LPOSC_STABLE_FRCE_MSB 5
#define RP23XX_RP_AP_CTRL_LPOSC_STABLE_FRCE_LSB 5
#define RP23XX_RP_AP_CTRL_LPOSC_STABLE_FRCE_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_ISO_OFF_RESET 0x0
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_ISO_OFF_BITS 0x00000010
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_ISO_OFF_MSB 4
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_ISO_OFF_LSB 4
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_ISO_OFF_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_PWRON_RESET 0x0
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_PWRON_BITS 0x00000008
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_PWRON_MSB 3
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_PWRON_LSB 3
#define RP23XX_RP_AP_CTRL_POWMAN_DFT_PWRON_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_POWMAN_DBGMODE_RESET 0x0
#define RP23XX_RP_AP_CTRL_POWMAN_DBGMODE_BITS 0x00000004
#define RP23XX_RP_AP_CTRL_POWMAN_DBGMODE_MSB 2
#define RP23XX_RP_AP_CTRL_POWMAN_DBGMODE_LSB 2
#define RP23XX_RP_AP_CTRL_POWMAN_DBGMODE_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_JTAG_FUNCSEL_RESET 0x0
#define RP23XX_RP_AP_CTRL_JTAG_FUNCSEL_BITS 0x00000002
#define RP23XX_RP_AP_CTRL_JTAG_FUNCSEL_MSB 1
#define RP23XX_RP_AP_CTRL_JTAG_FUNCSEL_LSB 1
#define RP23XX_RP_AP_CTRL_JTAG_FUNCSEL_ACCESS "RW"
#define RP23XX_RP_AP_CTRL_JTAG_TRSTN_RESET 0x0
#define RP23XX_RP_AP_CTRL_JTAG_TRSTN_BITS 0x00000001
#define RP23XX_RP_AP_CTRL_JTAG_TRSTN_MSB 0
#define RP23XX_RP_AP_CTRL_JTAG_TRSTN_LSB 0
#define RP23XX_RP_AP_CTRL_JTAG_TRSTN_ACCESS "RW"
#define RP23XX_RP_AP_DBGKEY_OFFSET 0x00000004
#define RP23XX_RP_AP_DBGKEY_BITS 0x00000007
#define RP23XX_RP_AP_DBGKEY_RESET 0x00000000
#define RP23XX_RP_AP_DBGKEY_RESET_RESET 0x0
#define RP23XX_RP_AP_DBGKEY_RESET_BITS 0x00000004
#define RP23XX_RP_AP_DBGKEY_RESET_MSB 2
#define RP23XX_RP_AP_DBGKEY_RESET_LSB 2
#define RP23XX_RP_AP_DBGKEY_RESET_ACCESS "RW"
#define RP23XX_RP_AP_DBGKEY_PUSH_RESET 0x0
#define RP23XX_RP_AP_DBGKEY_PUSH_BITS 0x00000002
#define RP23XX_RP_AP_DBGKEY_PUSH_MSB 1
#define RP23XX_RP_AP_DBGKEY_PUSH_LSB 1
#define RP23XX_RP_AP_DBGKEY_PUSH_ACCESS "RW"
#define RP23XX_RP_AP_DBGKEY_DATA_RESET 0x0
#define RP23XX_RP_AP_DBGKEY_DATA_BITS 0x00000001
#define RP23XX_RP_AP_DBGKEY_DATA_MSB 0
#define RP23XX_RP_AP_DBGKEY_DATA_LSB 0
#define RP23XX_RP_AP_DBGKEY_DATA_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_OFFSET 0x00000008
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_BITS 0x00000fff
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_RESET 0x00000000
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_BITS 0x00000800
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_MSB 11
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_LSB 11
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_BITS 0x00000400
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_MSB 10
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_LSB 10
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_BITS 0x00000200
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_MSB 9
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_LSB 9
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PU_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PU_BITS 0x00000100
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PU_MSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PU_LSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PU_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_BITS 0x00000080
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_MSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_LSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_BITS 0x00000040
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_MSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_LSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_BITS 0x00000020
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_MSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_LSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_BITS 0x00000010
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_MSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_LSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_BITS 0x00000008
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_MSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_LSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_BITS 0x00000004
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_MSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_LSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_BITS 0x00000002
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_MSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_LSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PD_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PD_BITS 0x00000001
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PD_MSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PD_LSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_SWCORE_IS_PD_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_OFFSET 0x0000000c
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_BITS 0x000001ff
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_RESET 0x00000000
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PU_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PU_BITS 0x00000100
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PU_MSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PU_LSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PU_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_BITS 0x00000080
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_MSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_LSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_BITS 0x00000040
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_MSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_LSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_BITS 0x00000020
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_MSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_LSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_BITS 0x00000010
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_MSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_LSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_BITS 0x00000008
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_MSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_LSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_BITS 0x00000004
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_MSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_LSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_BITS 0x00000002
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_MSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_LSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PD_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PD_BITS 0x00000001
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PD_MSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PD_LSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_XIP_IS_PD_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_OFFSET 0x00000010
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_BITS 0x000001ff
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_RESET 0x00000000
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PU_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PU_BITS 0x00000100
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PU_MSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PU_LSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PU_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_BITS 0x00000080
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_MSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_LSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_BITS 0x00000040
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_MSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_LSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_BITS 0x00000020
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_MSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_LSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_BITS 0x00000010
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_MSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_LSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_BITS 0x00000008
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_MSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_LSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_BITS 0x00000004
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_MSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_LSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_BITS 0x00000002
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_MSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_LSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PD_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PD_BITS 0x00000001
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PD_MSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PD_LSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM0_IS_PD_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_OFFSET 0x00000014
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_BITS 0x000001ff
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_RESET 0x00000000
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PU_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PU_BITS 0x00000100
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PU_MSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PU_LSB 8
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PU_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_BITS 0x00000080
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_MSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_LSB 7
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_BITS 0x00000040
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_MSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_LSB 6
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_BITS 0x00000020
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_MSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_LSB 5
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_BITS 0x00000010
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_MSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_LSB 4
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_BITS 0x00000008
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_MSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_LSB 3
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_BITS 0x00000004
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_MSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_LSB 2
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_BITS 0x00000002
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_MSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_LSB 1
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PD_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PD_BITS 0x00000001
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PD_MSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PD_LSB 0
#define RP23XX_RP_AP_DBG_POW_STATE_SRAM1_IS_PD_ACCESS "RO"
#define RP23XX_RP_AP_DBG_POW_OVRD_OFFSET 0x00000018
#define RP23XX_RP_AP_DBG_POW_OVRD_BITS 0x0000007f
#define RP23XX_RP_AP_DBG_POW_OVRD_RESET 0x00000000
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_BITS 0x00000040
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_MSB 6
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_LSB 6
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESET_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESET_BITS 0x00000020
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESET_MSB 5
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESET_LSB 5
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_RESET_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_BITS 0x00000010
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_MSB 4
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_LSB 4
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_ISO_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_ISO_BITS 0x00000008
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_ISO_MSB 3
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_ISO_LSB 3
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_ISO_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_BITS 0x00000004
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_MSB 2
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_LSB 2
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_BITS 0x00000002
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_MSB 1
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_LSB 1
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_RESET 0x0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_BITS 0x00000001
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_MSB 0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_LSB 0
#define RP23XX_RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_ACCESS "RW"
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_OFFSET 0x0000001c
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_BITS 0x00000fff
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_RESET 0x00000000
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_RESET 0x000
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_BITS 0x00000fff
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_MSB 11
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_LSB 0
#define RP23XX_RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_ACCESS "RW"
#define RP23XX_RP_AP_IDR_OFFSET 0x00000dfc
#define RP23XX_RP_AP_IDR_BITS 0xffffffff
#define RP23XX_RP_AP_IDR_RESET "-"
#define RP23XX_RP_AP_IDR_MSB 31
#define RP23XX_RP_AP_IDR_LSB 0
#define RP23XX_RP_AP_IDR_ACCESS "RO"
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RP_AP_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_sha256.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_SHA256_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_SHA256_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_SHA256_CSR_OFFSET 0x00000000
#define RP23XX_SHA256_WDATA_OFFSET 0x00000004
#define RP23XX_SHA256_SUM_OFFSET(n) ((n) * 4 + 0x000008)
/* Register definitions *****************************************************/
#define RP23XX_SHA256_CSR (RP23XX_SHA256_BASE + RP23XX_SHA256_CSR_OFFSET)
#define RP23XX_SHA256_WDATA (RP23XX_SHA256_BASE + RP23XX_SHA256_WDATA_OFFSET)
#define RP23XX_SHA256_SUM(n) (RP23XX_SHA256_BASE + RP23XX_SHA256_SUM_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_SHA256_CSR_MASK (0x00001317)
#define RP23XX_SHA256_CSR_BSWAP (1 << 18)
#define RP23XX_SHA256_CSR_DMA_SIZE_MASK (0x00000300)
#define RP23XX_SHA256_CSR_ERR_WDATA_NOT_RDY (1 << 4)
#define RP23XX_SHA256_CSR_SUM_VLD (1 << 2)
#define RP23XX_SHA256_CSR_WDATA_RDY (1 << 1)
#define RP23XX_SHA256_CSR_START (1 << 0)
#define RP23XX_SHA256_WDATA_MASK (0xffffffff)
#define RP23XX_SHA256_SUM_MASK (0xffffffff)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_SHA256_H */

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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_sio.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_SIO_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_SIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_SIO_CPUID_OFFSET 0x00000000
#define RP23XX_SIO_GPIO_IN_OFFSET 0x00000004
#define RP23XX_SIO_GPIO_HI_IN_OFFSET 0x00000008
#define RP23XX_SIO_GPIO_OUT_OFFSET 0x00000010
#define RP23XX_SIO_GPIO_HI_OUT_OFFSET 0x00000014
#define RP23XX_SIO_GPIO_OUT_SET_OFFSET 0x00000018
#define RP23XX_SIO_GPIO_HI_OUT_SET_OFFSET 0x0000001c
#define RP23XX_SIO_GPIO_OUT_CLR_OFFSET 0x00000020
#define RP23XX_SIO_GPIO_HI_OUT_CLR_OFFSET 0x00000024
#define RP23XX_SIO_GPIO_OUT_XOR_OFFSET 0x00000028
#define RP23XX_SIO_GPIO_HI_OUT_XOR_OFFSET 0x0000002c
#define RP23XX_SIO_GPIO_OE_OFFSET 0x00000030
#define RP23XX_SIO_GPIO_HI_OE_OFFSET 0x00000034
#define RP23XX_SIO_GPIO_OE_SET_OFFSET 0x00000038
#define RP23XX_SIO_GPIO_HI_OE_SET_OFFSET 0x0000003c
#define RP23XX_SIO_GPIO_OE_CLR_OFFSET 0x00000040
#define RP23XX_SIO_GPIO_HI_OE_CLR_OFFSET 0x00000044
#define RP23XX_SIO_GPIO_OE_XOR_OFFSET 0x00000048
#define RP23XX_SIO_GPIO_HI_OE_XOR_OFFSET 0x0000004c
#define RP23XX_SIO_FIFO_ST_OFFSET 0x00000050
#define RP23XX_SIO_FIFO_WR_OFFSET 0x00000054
#define RP23XX_SIO_FIFO_RD_OFFSET 0x00000058
#define RP23XX_SIO_SPINLOCK_ST_OFFSET 0x0000005c
#define RP23XX_SIO_INTERP0_ACCUM0_OFFSET 0x00000080
#define RP23XX_SIO_INTERP0_ACCUM1_OFFSET 0x00000084
#define RP23XX_SIO_INTERP0_BASE0_OFFSET 0x00000088
#define RP23XX_SIO_INTERP0_BASE1_OFFSET 0x0000008c
#define RP23XX_SIO_INTERP0_BASE2_OFFSET 0x00000090
#define RP23XX_SIO_INTERP0_POP_LANE0_OFFSET 0x00000094
#define RP23XX_SIO_INTERP0_POP_LANE1_OFFSET 0x00000098
#define RP23XX_SIO_INTERP0_POP_FULL_OFFSET 0x0000009c
#define RP23XX_SIO_INTERP0_PEEK_LANE0_OFFSET 0x000000a0
#define RP23XX_SIO_INTERP0_PEEK_LANE1_OFFSET 0x000000a4
#define RP23XX_SIO_INTERP0_PEEK_FULL_OFFSET 0x000000a8
#define RP23XX_SIO_INTERP0_CTRL_LANE0_OFFSET 0x000000ac
#define RP23XX_SIO_INTERP0_CTRL_LANE1_OFFSET 0x000000b0
#define RP23XX_SIO_INTERP0_ACCUM0_ADD_OFFSET 0x000000b4
#define RP23XX_SIO_INTERP0_ACCUM1_ADD_OFFSET 0x000000b8
#define RP23XX_SIO_INTERP0_BASE_1AND0_OFFSET 0x000000bc
#define RP23XX_SIO_INTERP1_ACCUM0_OFFSET 0x000000c0
#define RP23XX_SIO_INTERP1_ACCUM1_OFFSET 0x000000c4
#define RP23XX_SIO_INTERP1_BASE0_OFFSET 0x000000c8
#define RP23XX_SIO_INTERP1_BASE1_OFFSET 0x000000cc
#define RP23XX_SIO_INTERP1_BASE2_OFFSET 0x000000d0
#define RP23XX_SIO_INTERP1_POP_LANE0_OFFSET 0x000000d4
#define RP23XX_SIO_INTERP1_POP_LANE1_OFFSET 0x000000d8
#define RP23XX_SIO_INTERP1_POP_FULL_OFFSET 0x000000dc
#define RP23XX_SIO_INTERP1_PEEK_LANE0_OFFSET 0x000000e0
#define RP23XX_SIO_INTERP1_PEEK_LANE1_OFFSET 0x000000e4
#define RP23XX_SIO_INTERP1_PEEK_FULL_OFFSET 0x000000e8
#define RP23XX_SIO_INTERP1_CTRL_LANE0_OFFSET 0x000000ec
#define RP23XX_SIO_INTERP1_CTRL_LANE1_OFFSET 0x000000f0
#define RP23XX_SIO_INTERP1_ACCUM0_ADD_OFFSET 0x000000f4
#define RP23XX_SIO_INTERP1_ACCUM1_ADD_OFFSET 0x000000f8
#define RP23XX_SIO_INTERP1_BASE_1AND0_OFFSET 0x000000fc
#define RP23XX_SIO_SPINLOCK_OFFSET(n) ((n) * 4 + 0x000100)
#define RP23XX_SIO_DOORBELL_OUT_SET_OFFSET 0x00000180
#define RP23XX_SIO_DOORBELL_OUT_CLR_OFFSET 0x00000184
#define RP23XX_SIO_DOORBELL_IN_SET_OFFSET 0x00000188
#define RP23XX_SIO_DOORBELL_IN_CLR_OFFSET 0x0000018c
#define RP23XX_SIO_PERI_NONSEC_OFFSET 0x00000190
#define RP23XX_SIO_RISCV_SOFTIRQ_OFFSET 0x000001a0
#define RP23XX_SIO_MTIME_CTRL_OFFSET 0x000001a4
#define RP23XX_SIO_MTIME_OFFSET 0x000001b0
#define RP23XX_SIO_MTIMEH_OFFSET 0x000001b4
#define RP23XX_SIO_MTIMECMP_OFFSET 0x000001b8
#define RP23XX_SIO_MTIMECMPH_OFFSET 0x000001bc
#define RP23XX_SIO_TMDS_CTRL_OFFSET 0x000001c0
#define RP23XX_SIO_TMDS_WDATA_OFFSET 0x000001c4
#define RP23XX_SIO_TMDS_PEEK_SINGLE_OFFSET 0x000001c8
#define RP23XX_SIO_TMDS_POP_SINGLE_OFFSET 0x000001cc
#define RP23XX_SIO_TMDS_PEEK_DOUBLE_L0_OFFSET 0x000001d0
#define RP23XX_SIO_TMDS_POP_DOUBLE_L0_OFFSET 0x000001d4
#define RP23XX_SIO_TMDS_PEEK_DOUBLE_L1_OFFSET 0x000001d8
#define RP23XX_SIO_TMDS_POP_DOUBLE_L1_OFFSET 0x000001dc
#define RP23XX_SIO_TMDS_PEEK_DOUBLE_L2_OFFSET 0x000001e0
#define RP23XX_SIO_TMDS_POP_DOUBLE_L2_OFFSET 0x000001e4
/* Register definitions *****************************************************/
#define RP23XX_SIO_CPUID (RP23XX_SIO_BASE + RP23XX_SIO_CPUID_OFFSET)
#define RP23XX_SIO_GPIO_IN (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_IN_OFFSET)
#define RP23XX_SIO_GPIO_HI_IN (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_IN_OFFSET)
#define RP23XX_SIO_GPIO_OUT (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OUT_OFFSET)
#define RP23XX_SIO_GPIO_OUT_SET (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OUT_SET_OFFSET)
#define RP23XX_SIO_GPIO_OUT_CLR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OUT_CLR_OFFSET)
#define RP23XX_SIO_GPIO_OUT_XOR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OUT_XOR_OFFSET)
#define RP23XX_SIO_GPIO_OE (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OE_OFFSET)
#define RP23XX_SIO_GPIO_OE_SET (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OE_SET_OFFSET)
#define RP23XX_SIO_GPIO_OE_CLR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OE_CLR_OFFSET)
#define RP23XX_SIO_GPIO_OE_XOR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_OE_XOR_OFFSET)
#define RP23XX_SIO_GPIO_HI_OUT (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OUT_OFFSET)
#define RP23XX_SIO_GPIO_HI_OUT_SET (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OUT_SET_OFFSET)
#define RP23XX_SIO_GPIO_HI_OUT_CLR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OUT_CLR_OFFSET)
#define RP23XX_SIO_GPIO_HI_OUT_XOR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OUT_XOR_OFFSET)
#define RP23XX_SIO_GPIO_HI_OE (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OE_OFFSET)
#define RP23XX_SIO_GPIO_HI_OE_SET (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OE_SET_OFFSET)
#define RP23XX_SIO_GPIO_HI_OE_CLR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OE_CLR_OFFSET)
#define RP23XX_SIO_GPIO_HI_OE_XOR (RP23XX_SIO_BASE + RP23XX_SIO_GPIO_HI_OE_XOR_OFFSET)
#define RP23XX_SIO_FIFO_ST (RP23XX_SIO_BASE + RP23XX_SIO_FIFO_ST_OFFSET)
#define RP23XX_SIO_FIFO_WR (RP23XX_SIO_BASE + RP23XX_SIO_FIFO_WR_OFFSET)
#define RP23XX_SIO_FIFO_RD (RP23XX_SIO_BASE + RP23XX_SIO_FIFO_RD_OFFSET)
#define RP23XX_SIO_SPINLOCK_ST (RP23XX_SIO_BASE + RP23XX_SIO_SPINLOCK_ST_OFFSET)
#define RP23XX_SIO_DIV_UDIVIDEND (RP23XX_SIO_BASE + RP23XX_SIO_DIV_UDIVIDEND_OFFSET)
#define RP23XX_SIO_DIV_UDIVISOR (RP23XX_SIO_BASE + RP23XX_SIO_DIV_UDIVISOR_OFFSET)
#define RP23XX_SIO_DIV_SDIVIDEND (RP23XX_SIO_BASE + RP23XX_SIO_DIV_SDIVIDEND_OFFSET)
#define RP23XX_SIO_DIV_SDIVISOR (RP23XX_SIO_BASE + RP23XX_SIO_DIV_SDIVISOR_OFFSET)
#define RP23XX_SIO_DIV_QUOTIENT (RP23XX_SIO_BASE + RP23XX_SIO_DIV_QUOTIENT_OFFSET)
#define RP23XX_SIO_DIV_REMAINDER (RP23XX_SIO_BASE + RP23XX_SIO_DIV_REMAINDER_OFFSET)
#define RP23XX_SIO_DIV_CSR (RP23XX_SIO_BASE + RP23XX_SIO_DIV_CSR_OFFSET)
#define RP23XX_SIO_INTERP0_ACCUM0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_ACCUM0_OFFSET)
#define RP23XX_SIO_INTERP0_ACCUM1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_ACCUM1_OFFSET)
#define RP23XX_SIO_INTERP0_BASE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_BASE0_OFFSET)
#define RP23XX_SIO_INTERP0_BASE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_BASE1_OFFSET)
#define RP23XX_SIO_INTERP0_BASE2 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_BASE2_OFFSET)
#define RP23XX_SIO_INTERP0_POP_LANE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_POP_LANE0_OFFSET)
#define RP23XX_SIO_INTERP0_POP_LANE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_POP_LANE1_OFFSET)
#define RP23XX_SIO_INTERP0_POP_FULL (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_POP_FULL_OFFSET)
#define RP23XX_SIO_INTERP0_PEEK_LANE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_PEEK_LANE0_OFFSET)
#define RP23XX_SIO_INTERP0_PEEK_LANE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_PEEK_LANE1_OFFSET)
#define RP23XX_SIO_INTERP0_PEEK_FULL (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_PEEK_FULL_OFFSET)
#define RP23XX_SIO_INTERP0_CTRL_LANE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_CTRL_LANE0_OFFSET)
#define RP23XX_SIO_INTERP0_CTRL_LANE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_CTRL_LANE1_OFFSET)
#define RP23XX_SIO_INTERP0_ACCUM0_ADD (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_ACCUM0_ADD_OFFSET)
#define RP23XX_SIO_INTERP0_ACCUM1_ADD (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_ACCUM1_ADD_OFFSET)
#define RP23XX_SIO_INTERP0_BASE_1AND0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP0_BASE_1AND0_OFFSET)
#define RP23XX_SIO_INTERP1_ACCUM0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_ACCUM0_OFFSET)
#define RP23XX_SIO_INTERP1_ACCUM1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_ACCUM1_OFFSET)
#define RP23XX_SIO_INTERP1_BASE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_BASE0_OFFSET)
#define RP23XX_SIO_INTERP1_BASE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_BASE1_OFFSET)
#define RP23XX_SIO_INTERP1_BASE2 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_BASE2_OFFSET)
#define RP23XX_SIO_INTERP1_POP_LANE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_POP_LANE0_OFFSET)
#define RP23XX_SIO_INTERP1_POP_LANE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_POP_LANE1_OFFSET)
#define RP23XX_SIO_INTERP1_POP_FULL (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_POP_FULL_OFFSET)
#define RP23XX_SIO_INTERP1_PEEK_LANE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_PEEK_LANE0_OFFSET)
#define RP23XX_SIO_INTERP1_PEEK_LANE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_PEEK_LANE1_OFFSET)
#define RP23XX_SIO_INTERP1_PEEK_FULL (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_PEEK_FULL_OFFSET)
#define RP23XX_SIO_INTERP1_CTRL_LANE0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_CTRL_LANE0_OFFSET)
#define RP23XX_SIO_INTERP1_CTRL_LANE1 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_CTRL_LANE1_OFFSET)
#define RP23XX_SIO_INTERP1_ACCUM0_ADD (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_ACCUM0_ADD_OFFSET)
#define RP23XX_SIO_INTERP1_ACCUM1_ADD (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_ACCUM1_ADD_OFFSET)
#define RP23XX_SIO_INTERP1_BASE_1AND0 (RP23XX_SIO_BASE + RP23XX_SIO_INTERP1_BASE_1AND0_OFFSET)
#define RP23XX_SIO_SPINLOCK(n) (RP23XX_SIO_BASE + RP23XX_SIO_SPINLOCK_OFFSET(n))
/* Register bit definitions *************************************************/
#define RP23XX_SIO_GPIO_IN_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_IN_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_IN_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_IN_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_IN_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_IN_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_IN_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_IN_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OUT_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OUT_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OUT_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OUT_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OUT_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OUT_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OUT_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OUT_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OUT_SET_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OUT_SET_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OUT_SET_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OUT_SET_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OUT_SET_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OUT_SET_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OUT_SET_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OUT_SET_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OUT_CLR_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OUT_CLR_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OUT_CLR_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OUT_CLR_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OUT_CLR_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OUT_CLR_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OUT_CLR_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OUT_CLR_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OUT_XOR_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OUT_XOR_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OUT_XOR_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OUT_XOR_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OUT_XOR_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OUT_XOR_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OUT_XOR_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OUT_XOR_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OE_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OE_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OE_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OE_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OE_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OE_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OE_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OE_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OE_SET_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OE_SET_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OE_SET_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OE_SET_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OE_SET_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OE_SET_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OE_SET_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OE_SET_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OE_CLR_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OE_CLR_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OE_CLR_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OE_CLR_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OE_CLR_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OE_CLR_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OE_CLR_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OE_CLR_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_GPIO_OE_XOR_MASK (0xffffffff)
#define RP23XX_SIO_GPIO_HI_OE_XOR_MASK (0xff00ffff)
#define RP23XX_SIO_GPIO_HI_OE_XOR_QSPI_SD_MASK (0xf0000000)
#define RP23XX_SIO_GPIO_HI_OE_XOR_QSPI_CSN (1 << 27)
#define RP23XX_SIO_GPIO_HI_OE_XOR_QSPI_SCK (1 << 26)
#define RP23XX_SIO_GPIO_HI_OE_XOR_USB_DM (1 << 25)
#define RP23XX_SIO_GPIO_HI_OE_XOR_USB_DP (1 << 24)
#define RP23XX_SIO_GPIO_HI_OE_XOR_GPIO_MASK (0x0000ffff)
#define RP23XX_SIO_FIFO_ST_MASK (0x0000000f)
#define RP23XX_SIO_FIFO_ST_ROE (1 << 3)
#define RP23XX_SIO_FIFO_ST_WOF (1 << 2)
#define RP23XX_SIO_FIFO_ST_RDY (1 << 1)
#define RP23XX_SIO_FIFO_ST_VLD (1 << 0)
#define RP23XX_SIO_FIFO_WR_MASK (0xffffffff)
#define RP23XX_SIO_FIFO_RD_MASK (0xffffffff)
#define RP23XX_SIO_SPINLOCK_ST_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_ACCUM0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_ACCUM1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_BASE0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_BASE1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_BASE2_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_POP_LANE0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_POP_LANE1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_POP_FULL_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_PEEK_LANE0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_PEEK_LANE1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_PEEK_FULL_MASK (0xffffffff)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_MASK (0x03bfffff)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_OVERF (1 << 25)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_OVERF1 (1 << 24)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_OVERF0 (1 << 23)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_BLEND (1 << 21)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MASK (0x00180000)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_ADD_RAW (1 << 18)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_CROSS_RESULT (1 << 17)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_CROSS_INPUT (1 << 16)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_SIGNED (1 << 15)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_MASK_MSB_MASK (0x00007c00)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_MASK_LSB_MASK (0x000003e0)
#define RP23XX_SIO_INTERP0_CTRL_LANE0_SHIFT_MASK (0x0000001f)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_MASK (0x001fffff)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MASK (0x00180000)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_ADD_RAW (1 << 18)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_CROSS_RESULT (1 << 17)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_CROSS_INPUT (1 << 16)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_SIGNED (1 << 15)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_MASK_MSB_MASK (0x00007c00)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_MASK_LSB_MASK (0x000003e0)
#define RP23XX_SIO_INTERP0_CTRL_LANE1_SHIFT_MASK (0x0000001f)
#define RP23XX_SIO_INTERP0_ACCUM0_ADD_MASK (0x00ffffff)
#define RP23XX_SIO_INTERP0_ACCUM1_ADD_MASK (0x00ffffff)
#define RP23XX_SIO_INTERP0_BASE_1AND0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_ACCUM0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_ACCUM1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_BASE0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_BASE1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_BASE2_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_POP_LANE0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_POP_LANE1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_POP_FULL_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_PEEK_LANE0_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_PEEK_LANE1_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_PEEK_FULL_MASK (0xffffffff)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_MASK (0x03dfffff)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_OVERF (1 << 25)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_OVERF1 (1 << 24)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_OVERF0 (1 << 23)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_CLAMP (1 << 22)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MASK (0x00180000)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_ADD_RAW (1 << 18)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_CROSS_RESULT (1 << 17)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_CROSS_INPUT (1 << 16)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_SIGNED (1 << 15)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_MASK_MSB_MASK (0x00007c00)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_MASK_LSB_MASK (0x000003e0)
#define RP23XX_SIO_INTERP1_CTRL_LANE0_SHIFT_MASK (0x0000001f)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_MASK (0x001fffff)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MASK (0x00180000)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_ADD_RAW (1 << 18)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_CROSS_RESULT (1 << 17)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_CROSS_INPUT (1 << 16)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_SIGNED (1 << 15)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_MASK_MSB_MASK (0x00007c00)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_MASK_LSB_MASK (0x000003e0)
#define RP23XX_SIO_INTERP1_CTRL_LANE1_SHIFT_MASK (0x0000001f)
#define RP23XX_SIO_INTERP1_ACCUM0_ADD_MASK (0x00ffffff)
#define RP23XX_SIO_INTERP1_ACCUM1_ADD_MASK (0x00ffffff)
#define RP23XX_SIO_INTERP1_BASE_1AND0_MASK (0xffffffff)
#define RP23XX_SIO_DOORBELL_OUT_SET_MASK (0x000000ff)
#define RP23XX_SIO_DOORBELL_OUT_CLR_MASK (0x000000ff)
#define RP23XX_SIO_DOORBELL_IN_SET_MASK (0x000000ff)
#define RP23XX_SIO_DOORBELL_IN_CLR_MASK (0x000000ff)
#define RP23XX_SIO_PERI_NONSEC_MASK (0x00000023)
#define RP23XX_SIO_PERI_NONSEC_TMDS_MASK (0x00000020)
#define RP23XX_SIO_PERI_NONSEC_INTERP1 (1 << 1)
#define RP23XX_SIO_PERI_NONSEC_INTERP0 (1 << 0)
#define RP23XX_SIO_RISCV_SOFTIRQ_MASK (0x00000303)
#define RP23XX_SIO_RISCV_SOFTIRQ_CORE1_CLR (1 << 9)
#define RP23XX_SIO_RISCV_SOFTIRQ_CORE0_CLR (1 << 8)
#define RP23XX_SIO_RISCV_SOFTIRQ_CORE1_SET (1 << 1)
#define RP23XX_SIO_RISCV_SOFTIRQ_CORE0_SET (1 << 0)
#define RP23XX_SIO_MTIME_CTRL_MASK (0x0000000f)
#define RP23XX_SIO_MTIME_CTRL_DBGPAUSE_CORE1 (1 << 3)
#define RP23XX_SIO_MTIME_CTRL_DBGPAUSE_CORE0 (1 << 2)
#define RP23XX_SIO_MTIME_CTRL_FULLSPEED (1 << 1)
#define RP23XX_SIO_MTIME_CTRL_EN (1 << 0)
#define RP23XX_SIO_MTIME_MASK (0xffffffff)
#define RP23XX_SIO_MTIMEH_MASK (0xffffffff)
#define RP23XX_SIO_MTIMECMP_MASK (0xffffffff)
#define RP23XX_SIO_MTIMECMPH_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_CTRL_MASK (0x1f9fffff)
#define RP23XX_SIO_TMDS_CTRL_CLEAR_BALANCE (1 << 28)
#define RP23XX_SIO_TMDS_CTRL_PIX2_NOSHIFT (1 << 27)
#define RP23XX_SIO_TMDS_CTRL_PIX_SHIFT_MASK (0x07000000)
#define RP23XX_SIO_TMDS_CTRL_INTERLEAVE (1 << 23)
#define RP23XX_SIO_TMDS_CTRL_L2_NMASK_MASK (0x001c0000)
#define RP23XX_SIO_TMDS_CTRL_L1_NMASK_MASK (0x00038000)
#define RP23XX_SIO_TMDS_CTRL_L0_NMASK_MASK (0x00007000)
#define RP23XX_SIO_TMDS_CTRL_L2_ROT_MASK (0x00000f00)
#define RP23XX_SIO_TMDS_CTRL_L1_ROT_MASK (0x000000f0)
#define RP23XX_SIO_TMDS_CTRL_L0_ROT_MASK (0x0000000f)
#define RP23XX_SIO_TMDS_WDATA_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_PEEK_SINGLE_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_POP_SINGLE_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_PEEK_DOUBLE_L0_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_POP_DOUBLE_L0_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_PEEK_DOUBLE_L1_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_POP_DOUBLE_L1_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_PEEK_DOUBLE_L2_MASK (0xffffffff)
#define RP23XX_SIO_TMDS_POP_DOUBLE_L2_MASK (0xffffffff)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_SIO_H */

145
arch/risc-v/src/rp23xx-rv/hardware/rp23xx_spi.h Normal file
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@@ -0,0 +1,145 @@
/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_spi.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_SPI_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_RV_SPI_SSPCR0_OFFSET 0x000000 /* Control register 0 */
#define RP23XX_RV_SPI_SSPCR1_OFFSET 0x000004 /* Control register 1 */
#define RP23XX_RV_SPI_SSPDR_OFFSET 0x000008 /* Data register */
#define RP23XX_RV_SPI_SSPSR_OFFSET 0x00000c /* Status register */
#define RP23XX_RV_SPI_SSPCPSR_OFFSET 0x000010 /* Clock prescale register */
#define RP23XX_RV_SPI_SSPIMSC_OFFSET 0x000014 /* Interrupt mask set or clear register */
#define RP23XX_RV_SPI_SSPRIS_OFFSET 0x000018 /* Raw interrupt status register */
#define RP23XX_RV_SPI_SSPMIS_OFFSET 0x00001c /* Masked interrupt status register */
#define RP23XX_RV_SPI_SSPICR_OFFSET 0x000020 /* Interrupt clear register */
#define RP23XX_RV_SPI_SSPDMACR_OFFSET 0x000024 /* DMA control register */
#define RP23XX_RV_SPI_SSPPERIPHID0_OFFSET 0x000fe0 /* Peripheral identification registers */
#define RP23XX_RV_SPI_SSPPERIPHID1_OFFSET 0x000fe4 /* Peripheral identification registers */
#define RP23XX_RV_SPI_SSPPERIPHID2_OFFSET 0x000fe8 /* Peripheral identification registers */
#define RP23XX_RV_SPI_SSPPERIPHID3_OFFSET 0x000fec /* Peripheral identification registers */
#define RP23XX_RV_SPI_SSPPCELLID0_OFFSET 0x000ff0 /* PrimeCell identification registers */
#define RP23XX_RV_SPI_SSPPCELLID1_OFFSET 0x000ff4 /* PrimeCell identification registers */
#define RP23XX_RV_SPI_SSPPCELLID2_OFFSET 0x000ff8 /* PrimeCell identification registers */
#define RP23XX_RV_SPI_SSPPCELLID3_OFFSET 0x000ffc /* PrimeCell identification registers */
/* Register definitions *****************************************************/
#define RP23XX_RV_SPI_SSPCR0(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPCR0_OFFSET)
#define RP23XX_RV_SPI_SSPCR1(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPCR1_OFFSET)
#define RP23XX_RV_SPI_SSPDR(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPDR_OFFSET)
#define RP23XX_RV_SPI_SSPSR(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPSR_OFFSET)
#define RP23XX_RV_SPI_SSPCPSR(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPCPSR_OFFSET)
#define RP23XX_RV_SPI_SSPIMSC(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPIMSC_OFFSET)
#define RP23XX_RV_SPI_SSPRIS(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPRIS_OFFSET)
#define RP23XX_RV_SPI_SSPMIS(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPMIS_OFFSET)
#define RP23XX_RV_SPI_SSPICR(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPICR_OFFSET)
#define RP23XX_RV_SPI_SSPDMACR(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPDMACR_OFFSET)
#define RP23XX_RV_SPI_SSPPERIPHID0(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPERIPHID0_OFFSET)
#define RP23XX_RV_SPI_SSPPERIPHID1(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPERIPHID1_OFFSET)
#define RP23XX_RV_SPI_SSPPERIPHID2(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPERIPHID2_OFFSET)
#define RP23XX_RV_SPI_SSPPERIPHID3(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPERIPHID3_OFFSET)
#define RP23XX_RV_SPI_SSPPCELLID0(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPCELLID0_OFFSET)
#define RP23XX_RV_SPI_SSPPCELLID1(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPCELLID1_OFFSET)
#define RP23XX_RV_SPI_SSPPCELLID2(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPCELLID2_OFFSET)
#define RP23XX_RV_SPI_SSPPCELLID3(n) (RP23XX_RV_SPI_BASE(n) + RP23XX_RV_SPI_SSPPCELLID3_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_RV_SPI_SSPCR0_SCR_SHIFT (8) /* Serial clock rate */
#define RP23XX_RV_SPI_SSPCR0_SCR_MASK (0xff << RP23XX_RV_SPI_SSPCR0_SCR_SHIFT)
#define RP23XX_RV_SPI_SSPCR0_SPH (1 << 7) /* SSPCLKOUT phase */
#define RP23XX_RV_SPI_SSPCR0_SPO (1 << 6) /* SSPCLKOUT polarity */
#define RP23XX_RV_SPI_SSPCR0_FRF_SHIFT (4) /* Frame format */
#define RP23XX_RV_SPI_SSPCR0_FRF_MASK (0x03 << RP23XX_RV_SPI_SSPCR0_FRF_SHIFT)
#define RP23XX_RV_SPI_SSPCR0_DSS_MASK (0x0f) /* Data Size Select */
#define RP23XX_RV_SPI_SSPCR0_DSS_SHIFT (0)
#define RP23XX_RV_SPI_SSPCR1_SOD (1 << 3) /* Slave-mode output disable */
#define RP23XX_RV_SPI_SSPCR1_MS (1 << 2) /* Master or slave mode select */
#define RP23XX_RV_SPI_SSPCR1_SSE (1 << 1) /* Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. */
#define RP23XX_RV_SPI_SSPCR1_LBM (1 << 0) /* Loop back mode */
#define RP23XX_RV_SPI_SSPDR_DATA_MASK (0xffff) /* Transmit/Receive FIFO */
#define RP23XX_RV_SPI_SSPSR_BSY (1 << 4) /* PrimeCell SSP busy flag */
#define RP23XX_RV_SPI_SSPSR_RFF (1 << 3) /* Receive FIFO full */
#define RP23XX_RV_SPI_SSPSR_RNE (1 << 2) /* Receive FIFO not empty */
#define RP23XX_RV_SPI_SSPSR_TNF (1 << 1) /* Transmit FIFO not full */
#define RP23XX_RV_SPI_SSPSR_TFE (1 << 0) /* Transmit FIFO empty */
#define RP23XX_RV_SPI_SSPCPSR_CPSDVSR_MASK (0xff) /* Clock prescale divisor. Must be an even number from 2-254 */
#define RP23XX_RV_SPI_SSPIMSC_TXIM (1 << 3) /* Transmit FIFO interrupt mask */
#define RP23XX_RV_SPI_SSPIMSC_RXIM (1 << 2) /* Receive FIFO interrupt mask */
#define RP23XX_RV_SPI_SSPIMSC_RTIM (1 << 1) /* Receive timeout interrupt mask */
#define RP23XX_RV_SPI_SSPIMSC_RORIM (1 << 0) /* Receive overrun interrupt mask */
#define RP23XX_RV_SPI_SSPRIS_TXRIS (1 << 3) /* Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt */
#define RP23XX_RV_SPI_SSPRIS_RXRIS (1 << 2) /* Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt */
#define RP23XX_RV_SPI_SSPRIS_RTRIS (1 << 1) /* Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt */
#define RP23XX_RV_SPI_SSPRIS_RORRIS (1 << 0) /* Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt */
#define RP23XX_RV_SPI_SSPMIS_TXMIS (1 << 3) /* Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt */
#define RP23XX_RV_SPI_SSPMIS_RXMIS (1 << 2) /* Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt */
#define RP23XX_RV_SPI_SSPMIS_RTMIS (1 << 1) /* Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt */
#define RP23XX_RV_SPI_SSPMIS_RORMIS (1 << 0) /* Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt */
#define RP23XX_RV_SPI_SSPICR_RTIC (1 << 1) /* Clears the SSPRTINTR interrupt */
#define RP23XX_RV_SPI_SSPICR_RORIC (1 << 0) /* Clears the SSPRORINTR interrupt */
#define RP23XX_RV_SPI_SSPDMACR_TXDMAE (1 << 1) /* Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. */
#define RP23XX_RV_SPI_SSPDMACR_RXDMAE (1 << 0) /* Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. */
#define RP23XX_RV_SPI_SSPPERIPHID0_PARTNUMBER0_MASK (0xff) /* These bits read back as 0x22 */
#define RP23XX_RV_SPI_SSPPERIPHID1_DESIGNER0_SHIFT (4) /* These bits read back as 0x1 */
#define RP23XX_RV_SPI_SSPPERIPHID1_DESIGNER0_MASK (0x0f << RP23XX_RV_SPI_SSPPERIPHID1_DESIGNER0_SHIFT)
#define RP23XX_RV_SPI_SSPPERIPHID1_PARTNUMBER1_MASK (0x0f) /* These bits read back as 0x0 */
#define RP23XX_RV_SPI_SSPPERIPHID2_REVISION_SHIFT (4) /* These bits return the peripheral revision */
#define RP23XX_RV_SPI_SSPPERIPHID2_REVISION_MASK (0x0f << RP23XX_RV_SPI_SSPPERIPHID2_REVISION_SHIFT)
#define RP23XX_RV_SPI_SSPPERIPHID2_DESIGNER1_MASK (0x0f) /* These bits read back as 0x4 */
#define RP23XX_RV_SPI_SSPPERIPHID3_CONFIGURATION_MASK (0xff) /* These bits read back as 0x00 */
#define RP23XX_RV_SPI_SSPPCELLID0_MASK (0xff) /* These bits read back as 0x0D */
#define RP23XX_RV_SPI_SSPPCELLID1_MASK (0xff) /* These bits read back as 0xF0 */
#define RP23XX_RV_SPI_SSPPCELLID2_MASK (0xff) /* These bits read back as 0x05 */
#define RP23XX_RV_SPI_SSPPCELLID3_MASK (0xff) /* These bits read back as 0xB1 */
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_RV_SPI_H */

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arch/risc-v/src/rp23xx-rv/hardware/rp23xx_tbman.h Normal file
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/****************************************************************************
* arch/risc-v/src/rp23xx-rv/hardware/rp23xx_tbman.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_TBMAN_H
#define __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_TBMAN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/rp23xx_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define RP23XX_TBMAN_PLATFORM_OFFSET 0x00000000
/* Register definitions *****************************************************/
#define RP23XX_TBMAN_PLATFORM (RP23XX_TBMAN_BASE + RP23XX_TBMAN_PLATFORM_OFFSET)
/* Register bit definitions *************************************************/
#define RP23XX_TBMAN_PLATFORM_MASK 0x00000007
#define RP23XX_TBMAN_PLATFORM_HDLSIM (1 << 2)
#define RP23XX_TBMAN_PLATFORM_FPGA (1 << 1)
#define RP23XX_TBMAN_PLATFORM_ASIC (1 << 0)
#endif /* __ARCH_RISC_V_SRC_RP23XX_HARDWARE_RP23XX_TBMAN_H */

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