risc-v/esp32c3: Support ESP32-C3 SHA accelerator

arch/risc-v/src/esp32c3/Kconfig

@@ -309,6 +309,11 @@ config ESP32C3_WIRELESS
 config ESP32C3_AES_ACCELERATOR
 	bool "AES Accelerator"
 	default n
+config ESP32C3_SHA_ACCELERATOR
+	bool "SHA Accelerator"
+	default n
+	---help---
+		Enable ESP32-C3 SHA accelerator support.
 
 config ESP32C3_BIGNUM_ACCELERATOR
 	bool "BIGNUM Accelerator"
@@ -840,6 +845,14 @@ config ESP32C3_AES_ACCELERATOR_TEST
 	default n
 
 endmenu # AES accelerator
+menu "SHA accelerator"
+	depends on ESP32C3_SHA_ACCELERATOR
+
+config ESP32C3_SHA_ACCELERATOR_TEST
+	bool "SHA accelerator test"
+	default n
+
+endmenu # ESP32C3_SHA_ACCELERATOR
 
 menu "RSA Accelerate Configuration"
 	depends on ESP32C3_RSA_ACCELERATOR

arch/risc-v/src/esp32c3/Make.defs

@@ -117,6 +117,10 @@ ifeq ($(CONFIG_ESP32C3_RSA_ACCELERATOR),y)
 CHIP_CSRCS += esp32c3_rsa.c
 endif
 
+ifeq ($(CONFIG_ESP32C3_SHA_ACCELERATOR),y)
+CHIP_CSRCS += esp32c3_sha.c
+endif
+
 ifeq ($(CONFIG_ESP32C3_FREERUN),y)
 CHIP_CSRCS += esp32c3_freerun.c
 endif

arch/risc-v/src/esp32c3/esp32c3_sha.h

@@ -0,0 +1,121 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c3/esp32c3_sha.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SHA_H
+#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SHA_H
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+enum esp32c3_sha_type_e
+{
+    ESP32C3_SHA1_1 = 0,
+    ESP32C3_SHA2_224,
+    ESP32C3_SHA2_256,
+    ESP32C3_SHA3_384,
+    ESP32C3_SHA3_512,
+    ESP32C3_SHA_TYPE_MAX
+};
+
+enum esp32c3_sha_state_e
+{
+    ESP32C3_SHA_STATE_INIT,
+    ESP32C3_SHA_STATE_IN_PROCESS
+};
+
+/* SHA-1 context structure */
+
+struct esp32c3_sha1_context_s
+{
+    uint32_t total[2];          /* number of bytes processed  */
+    uint32_t state[5];          /* intermediate digest state  */
+    unsigned char buffer[64];   /* data block being processed */
+    bool first_block;           /* if first then true else false */
+    enum esp32c3_sha_type_e mode;
+    enum esp32c3_sha_state_e sha_state;
+};
+
+/* SHA-256 context structure */
+
+struct esp32c3_sha256_context_s
+{
+    uint32_t total[2];          /* number of bytes processed  */
+    uint32_t state[8];          /* intermediate digest state  */
+    unsigned char buffer[64];   /* data block being processed */
+    bool first_block;           /* if first then true, else false */
+    enum esp32c3_sha_type_e mode;
+    enum esp32c3_sha_state_e sha_state;
+};
+
+/* SHA-512 context structure */
+
+struct esp32c3_sha512_context_s
+{
+    uint64_t        total[2];       /* number of bytes processed  */
+    uint64_t        state[8];       /* intermediate digest state  */
+    uint8_t         buffer[128];    /* data block being processed */
+
+    bool first_block;               /* if first then true, else false */
+    enum esp32c3_sha_type_e mode;
+    enum esp32c3_sha_state_e sha_state;
+};
+
+/****************************************************************************
+ * Name: esp32c3_sha_init
+ *
+ * Description:
+ *   Initialize ESP32-C3 SHA hardware.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   OK is returned on success. Otherwise, a negated errno value is returned.
+ *
+ ****************************************************************************/
+
+int esp32c3_sha_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+#undef EXTERN
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SHA_H */

boards/risc-v/esp32c3/esp32c3-devkit/configs/sha/defconfig

@@ -0,0 +1,48 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_NSH_CMDPARMS is not set
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_BOARD="esp32c3-devkit"
+CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y
+CONFIG_ARCH_CHIP="esp32c3"
+CONFIG_ARCH_CHIP_ESP32C3=y
+CONFIG_ARCH_CHIP_ESP32C3WROOM02=y
+CONFIG_ARCH_INTERRUPTSTACK=1536
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=15000
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_ASSERTIONS=y
+CONFIG_DEBUG_FEATURES=y
+CONFIG_DEV_ZERO=y
+CONFIG_ESP32C3_SHA_ACCELERATOR=y
+CONFIG_ESP32C3_SHA_ACCELERATOR_TEST=y
+CONFIG_FS_PROCFS=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_MAX_TASKS=16
+CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_NSH_STRERROR=y
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_START_DAY=29
+CONFIG_START_MONTH=11
+CONFIG_START_YEAR=2019
+CONFIG_SYSTEM_NSH=y
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_USER_ENTRYPOINT="esp32c3_sha_main"

boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c

@@ -59,6 +59,10 @@
 #  include "esp32c3_efuse.h"
 #endif
 
+#ifdef CONFIG_ESP32C3_SHA_ACCELERATOR
+#  include "esp32c3_sha.h"
+#endif
+
 #ifdef CONFIG_RTC_DRIVER
 #  include "esp32c3_rtc_lowerhalf.h"
 #endif
@@ -137,6 +141,15 @@ int esp32c3_bringup(void)
     }
 #endif
 
+#ifdef CONFIG_ESP32C3_SHA_ACCELERATOR
+  ret = esp32c3_sha_init();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to initialize SHA: %d\n", ret);
+    }
+#endif
+
 #ifdef CONFIG_FS_PROCFS
   /* Mount the procfs file system */