mirror of
https://github.com/apache/nuttx.git
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arm/rp2040: Add RP2040 SPI device support
This commit is contained in:
Yuichi Nakamura
committed by
Masayuki Ishikawa
Masayuki Ishikawa
parent
a8d269df98
commit
2d7aabf13b
@@ -73,6 +73,29 @@ config RP2040_UART1_2STOP
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endif
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config RP2040_SPI
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bool "SPI"
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select SPI
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if RP2040_SPI
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config RP2040_SPI0
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bool "SPI0"
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config RP2040_SPI1
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bool "SPI1"
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config RP2040_SPI_DRIVER
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bool "SPI character driver"
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default y
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select SPI_DRIVER
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---help---
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Build in support for a character driver at /dev/spi[N] that may be
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used to perform SPI bus transfers from applications. The intent of
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this driver is to support SPI testing.
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endif
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config RP2040_I2C
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bool "I2C"
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select I2C
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@@ -96,3 +119,25 @@ config RP2040_I2C_DRIVER
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in any real driver application.
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endif
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menuconfig RP2040_SPISD
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bool "SPI SD Card"
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default n
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select MMCSD_SPI
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if RP2040_SPISD
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config RP2040_SPISD_SLOT_NO
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int "SPI SD Card Slot Number"
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default 0
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---help---
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Select spi sd card slot number.
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config RP2040_SPISD_SPI_CH
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int "SPI channel number"
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default 0
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range 0 1
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---help---
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Select spi channel number to use spi sd card.
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endif # SPISD Configuration
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@@ -67,6 +67,10 @@ CHIP_CSRCS += rp2040_cpuidlestack.c
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CHIP_CSRCS += rp2040_testset.c
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endif
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ifeq ($(CONFIG_RP2040_SPI),y)
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CHIP_CSRCS += rp2040_spi.c
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endif
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ifeq ($(CONFIG_RP2040_I2C),y)
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CHIP_CSRCS += rp2040_i2c.c
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endif
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@@ -0,0 +1,160 @@
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/****************************************************************************
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* arch/arm/src/rp2040/hardware/rp2040_spi.h
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*
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* Generated from rp2040.svd originally provided by
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* Raspberry Pi (Trading) Ltd.
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*
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* Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_SPI_H
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#define __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_SPI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "hardware/rp2040_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define RP2040_SPI_SSPCR0_OFFSET 0x000000 /* Control register 0 */
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#define RP2040_SPI_SSPCR1_OFFSET 0x000004 /* Control register 1 */
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#define RP2040_SPI_SSPDR_OFFSET 0x000008 /* Data register */
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#define RP2040_SPI_SSPSR_OFFSET 0x00000c /* Status register */
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#define RP2040_SPI_SSPCPSR_OFFSET 0x000010 /* Clock prescale register */
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#define RP2040_SPI_SSPIMSC_OFFSET 0x000014 /* Interrupt mask set or clear register */
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#define RP2040_SPI_SSPRIS_OFFSET 0x000018 /* Raw interrupt status register */
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#define RP2040_SPI_SSPMIS_OFFSET 0x00001c /* Masked interrupt status register */
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#define RP2040_SPI_SSPICR_OFFSET 0x000020 /* Interrupt clear register */
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#define RP2040_SPI_SSPDMACR_OFFSET 0x000024 /* DMA control register */
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#define RP2040_SPI_SSPPERIPHID0_OFFSET 0x000fe0 /* Peripheral identification registers */
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#define RP2040_SPI_SSPPERIPHID1_OFFSET 0x000fe4 /* Peripheral identification registers */
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#define RP2040_SPI_SSPPERIPHID2_OFFSET 0x000fe8 /* Peripheral identification registers */
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#define RP2040_SPI_SSPPERIPHID3_OFFSET 0x000fec /* Peripheral identification registers */
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#define RP2040_SPI_SSPPCELLID0_OFFSET 0x000ff0 /* PrimeCell identification registers */
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#define RP2040_SPI_SSPPCELLID1_OFFSET 0x000ff4 /* PrimeCell identification registers */
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#define RP2040_SPI_SSPPCELLID2_OFFSET 0x000ff8 /* PrimeCell identification registers */
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#define RP2040_SPI_SSPPCELLID3_OFFSET 0x000ffc /* PrimeCell identification registers */
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/* Register definitions *****************************************************/
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#define RP2040_SPI_SSPCR0(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPCR0_OFFSET)
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#define RP2040_SPI_SSPCR1(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPCR1_OFFSET)
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#define RP2040_SPI_SSPDR(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPDR_OFFSET)
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#define RP2040_SPI_SSPSR(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPSR_OFFSET)
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#define RP2040_SPI_SSPCPSR(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPCPSR_OFFSET)
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#define RP2040_SPI_SSPIMSC(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPIMSC_OFFSET)
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#define RP2040_SPI_SSPRIS(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPRIS_OFFSET)
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#define RP2040_SPI_SSPMIS(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPMIS_OFFSET)
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#define RP2040_SPI_SSPICR(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPICR_OFFSET)
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#define RP2040_SPI_SSPDMACR(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPDMACR_OFFSET)
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#define RP2040_SPI_SSPPERIPHID0(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPPERIPHID0_OFFSET)
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#define RP2040_SPI_SSPPERIPHID1(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPPERIPHID1_OFFSET)
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#define RP2040_SPI_SSPPERIPHID2(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPPERIPHID2_OFFSET)
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#define RP2040_SPI_SSPPERIPHID3(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPPERIPHID3_OFFSET)
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#define RP2040_SPI_SSPPCELLID0(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPPCELLID0_OFFSET)
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#define RP2040_SPI_SSPPCELLID1(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPPCELLID1_OFFSET)
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#define RP2040_SPI_SSPPCELLID2(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPPCELLID2_OFFSET)
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#define RP2040_SPI_SSPPCELLID3(n) (RP2040_SPI_BASE(n) + RP2040_SPI_SSPPCELLID3_OFFSET)
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/* Register bit definitions *************************************************/
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#define RP2040_SPI_SSPCR0_SCR_SHIFT (8) /* Serial clock rate */
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#define RP2040_SPI_SSPCR0_SCR_MASK (0xff << RP2040_SPI_SSPCR0_SCR_SHIFT)
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#define RP2040_SPI_SSPCR0_SPH (1 << 7) /* SSPCLKOUT phase */
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#define RP2040_SPI_SSPCR0_SPO (1 << 6) /* SSPCLKOUT polarity */
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#define RP2040_SPI_SSPCR0_FRF_SHIFT (4) /* Frame format */
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#define RP2040_SPI_SSPCR0_FRF_MASK (0x03 << RP2040_SPI_SSPCR0_FRF_SHIFT)
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#define RP2040_SPI_SSPCR0_DSS_MASK (0x0f) /* Data Size Select */
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#define RP2040_SPI_SSPCR0_DSS_SHIFT (0)
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#define RP2040_SPI_SSPCR1_SOD (1 << 3) /* Slave-mode output disable */
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#define RP2040_SPI_SSPCR1_MS (1 << 2) /* Master or slave mode select */
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#define RP2040_SPI_SSPCR1_SSE (1 << 1) /* Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. */
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#define RP2040_SPI_SSPCR1_LBM (1 << 0) /* Loop back mode */
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#define RP2040_SPI_SSPDR_DATA_MASK (0xffff) /* Transmit/Receive FIFO */
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#define RP2040_SPI_SSPSR_BSY (1 << 4) /* PrimeCell SSP busy flag */
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#define RP2040_SPI_SSPSR_RFF (1 << 3) /* Receive FIFO full */
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#define RP2040_SPI_SSPSR_RNE (1 << 2) /* Receive FIFO not empty */
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#define RP2040_SPI_SSPSR_TNF (1 << 1) /* Transmit FIFO not full */
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#define RP2040_SPI_SSPSR_TFE (1 << 0) /* Transmit FIFO empty */
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#define RP2040_SPI_SSPCPSR_CPSDVSR_MASK (0xff) /* Clock prescale divisor. Must be an even number from 2-254 */
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#define RP2040_SPI_SSPIMSC_TXIM (1 << 3) /* Transmit FIFO interrupt mask */
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#define RP2040_SPI_SSPIMSC_RXIM (1 << 2) /* Receive FIFO interrupt mask */
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#define RP2040_SPI_SSPIMSC_RTIM (1 << 1) /* Receive timeout interrupt mask */
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#define RP2040_SPI_SSPIMSC_RORIM (1 << 0) /* Receive overrun interrupt mask */
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#define RP2040_SPI_SSPRIS_TXRIS (1 << 3) /* Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt */
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#define RP2040_SPI_SSPRIS_RXRIS (1 << 2) /* Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt */
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#define RP2040_SPI_SSPRIS_RTRIS (1 << 1) /* Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt */
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#define RP2040_SPI_SSPRIS_RORRIS (1 << 0) /* Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt */
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#define RP2040_SPI_SSPMIS_TXMIS (1 << 3) /* Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt */
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#define RP2040_SPI_SSPMIS_RXMIS (1 << 2) /* Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt */
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#define RP2040_SPI_SSPMIS_RTMIS (1 << 1) /* Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt */
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#define RP2040_SPI_SSPMIS_RORMIS (1 << 0) /* Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt */
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#define RP2040_SPI_SSPICR_RTIC (1 << 1) /* Clears the SSPRTINTR interrupt */
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#define RP2040_SPI_SSPICR_RORIC (1 << 0) /* Clears the SSPRORINTR interrupt */
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#define RP2040_SPI_SSPDMACR_TXDMAE (1 << 1) /* Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. */
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#define RP2040_SPI_SSPDMACR_RXDMAE (1 << 0) /* Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. */
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#define RP2040_SPI_SSPPERIPHID0_PARTNUMBER0_MASK (0xff) /* These bits read back as 0x22 */
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#define RP2040_SPI_SSPPERIPHID1_DESIGNER0_SHIFT (4) /* These bits read back as 0x1 */
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#define RP2040_SPI_SSPPERIPHID1_DESIGNER0_MASK (0x0f << RP2040_SPI_SSPPERIPHID1_DESIGNER0_SHIFT)
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#define RP2040_SPI_SSPPERIPHID1_PARTNUMBER1_MASK (0x0f) /* These bits read back as 0x0 */
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#define RP2040_SPI_SSPPERIPHID2_REVISION_SHIFT (4) /* These bits return the peripheral revision */
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#define RP2040_SPI_SSPPERIPHID2_REVISION_MASK (0x0f << RP2040_SPI_SSPPERIPHID2_REVISION_SHIFT)
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#define RP2040_SPI_SSPPERIPHID2_DESIGNER1_MASK (0x0f) /* These bits read back as 0x4 */
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#define RP2040_SPI_SSPPERIPHID3_CONFIGURATION_MASK (0xff) /* These bits read back as 0x00 */
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#define RP2040_SPI_SSPPCELLID0_MASK (0xff) /* These bits read back as 0x0D */
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#define RP2040_SPI_SSPPCELLID1_MASK (0xff) /* These bits read back as 0xF0 */
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#define RP2040_SPI_SSPPCELLID2_MASK (0xff) /* These bits read back as 0x05 */
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#define RP2040_SPI_SSPPCELLID3_MASK (0xff) /* These bits read back as 0xB1 */
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#endif /* __ARCH_ARM_SRC_RP2040_HARDWARE_RP2040_SPI_H */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,224 @@
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/****************************************************************************
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* arch/arm/src/rp2040/rp2040_spi.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_RP2040_RP2040_SPI_H
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#define __ARCH_ARM_SRC_RP2040_RP2040_SPI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/spi/spi.h>
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#include "hardware/rp2040_spi.h"
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#ifdef CONFIG_RP2040_DMAC
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#include "rp2040_dmac.h"
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#endif
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#if defined(CONFIG_RP2040_SPI0) || defined(CONFIG_RP2040_SPI1)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* This header file defines interfaces to common SPI logic.
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* To use this common SPI logic on your board:
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*
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* 1. Provide logic in rp2040_boardinitialize() to configure SPI chip select
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* pins.
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* 2. Provide rp2040_spi0/1select() and rp2040_spi0/1status() functions in
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* your board-specific logic. These functions will perform chip selection
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* and status operations using GPIOs in the way your board is configured.
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* 3. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
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* rp2040_spi0/1cmddata() functions in your board-specific logic. These
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* functions will perform cmd/data selection operations using GPIOs in the
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* way your board is configured.
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* 4. Your low level board initialization logic should call
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* rp2040_spibus_initialize.
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* 5. The handle returned by rp2040_spibus_initialize() may then be used to
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* bind the SPI driver to higher level logic
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* (e.g., calling mmcsd_spislotinitialize(), for example, will bind the
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* SPI driver to the SPI MMC/SD driver).
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*/
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#define RP2040_SPI_DMAC_CHTYPE_TX (0)
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#define RP2040_SPI_DMAC_CHTYPE_RX (1)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: rp2040_spibus_initialize
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*
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* Description:
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* Initialize the selected SPI port
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*
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* Input Parameter:
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* port - Port number
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*
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* Returned Value:
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* Valid SPI device structure reference on success; a NULL on failure
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*
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****************************************************************************/
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FAR struct spi_dev_s *rp2040_spibus_initialize(int port);
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/****************************************************************************
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* Name: rp2040_spi_dmaconfig
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*
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* Description:
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* Enable DMA configuration.
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*
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* Input Parameter:
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* port - Port number
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* chtype - Channel type(TX or RX)
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* handle - DMA channel handle
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* conf - DMA configuration
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_RP2040_DMAC
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void rp2040_spi_dmaconfig(int port, int chtype, DMA_HANDLE handle,
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FAR dma_config_t *conf);
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#endif
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/****************************************************************************
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* Name: rp2040_spiXselect, rp2040_spiXstatus, and rp2040_spiXcmddata
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*
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* Description:
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* These functions must be provided in your board-specific logic.
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* The rp2040_spi0/1select functions will perform chip selection and the
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* rp2040_spi0/1status will perform status operations using GPIOs in
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* the way your board is configured.
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*
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* If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, then
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* rp2040_spi0/1cmddata must also be provided.
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* This functions performs cmd/data selection operations using GPIOs in
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* the way your board is configured.
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*
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****************************************************************************/
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#ifdef CONFIG_RP2040_SPI0
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void rp2040_spi0select(FAR struct spi_dev_s *dev,
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uint32_t devid,
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bool selected);
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uint8_t rp2040_spi0status(FAR struct spi_dev_s *dev,
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uint32_t devid);
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#ifdef CONFIG_SPI_CMDDATA
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||||
int rp2040_spi0cmddata(FAR struct spi_dev_s *dev,
|
||||
uint32_t devid,
|
||||
bool cmd);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RP2040_SPI1
|
||||
void rp2040_spi1select(FAR struct spi_dev_s *dev,
|
||||
uint32_t devid,
|
||||
bool selected);
|
||||
uint8_t rp2040_spi1status(FAR struct spi_dev_s *dev,
|
||||
uint32_t devid);
|
||||
#ifdef CONFIG_SPI_CMDDATA
|
||||
int rp2040_spi1cmddata(FAR struct spi_dev_s *dev,
|
||||
uint32_t devid,
|
||||
bool cmd);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: spi_flush
|
||||
*
|
||||
* Description:
|
||||
* Flush and discard any words left in the RX fifo. This can be called
|
||||
* from spi0/1select after a device is deselected (if you worry about such
|
||||
* things).
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void spi_flush(FAR struct spi_dev_s *dev);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rp2040_spiXregister
|
||||
*
|
||||
* Description:
|
||||
* If the board supports a card detect callback to inform the SPI-based
|
||||
* MMC/SD driver when an SD card is inserted or removed, then
|
||||
* CONFIG_SPI_CALLBACK should be defined and the following function(s) must
|
||||
* must be implemented. These functions implements the registercallback
|
||||
* method of the SPI interface (see include/nuttx/spi/spi.h for details)
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* callback - The function to call on the media change
|
||||
* arg - A caller provided value to return with the callback
|
||||
*
|
||||
* Returned Value:
|
||||
* 0 on success; negated errno on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SPI_CALLBACK
|
||||
#ifdef CONFIG_RP2040_SPI0
|
||||
int rp2040_spi0register(FAR struct spi_dev_s *dev,
|
||||
spi_mediachange_t callback, FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RP2040_SPI1
|
||||
int rp2040_spi1register(FAR struct spi_dev_s *dev,
|
||||
spi_mediachange_t callback, FAR void *arg);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_RP2040_SPI0/1 */
|
||||
#endif /* __ARCH_ARM_SRC_RP2040_RP2040_SPI_H */
|
||||
Reference in New Issue
Block a user