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Merged in ziggurat29/nuttx/stm32l4_qspi_005 (pull request #6)

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QSPI DMA support in STM32L4, and DMA fixes...
This commit is contained in:
Gregory Nutt
2016-04-24 16:53:33 -06:00
parent 533aa4d97d 1baf943dca
commit 2d3529294e
9 changed files with 717 additions and 137 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/stm32l4/Kconfig
+114 -3
View File
@@ -79,7 +79,7 @@ config STM32L4_HAVE_LTDC
default n
# These "hidden" settings are the OR of individual peripheral selections
# indicating that the general capabilitiy is required.
# indicating that the general capability is required.
config STM32L4_ADC
bool
@@ -133,7 +133,6 @@ config STM32L4_DMA2
select STM32L4_DMA
select ARCH_DMA
config STM32L4_CRC
bool "CRC"
default n
@@ -209,7 +208,119 @@ config STM32L4_QSPI_CSHT
---help---
The STM32L4 QSPI peripheral requires that it be specified the minimum number
of AHB cycles that Chip Select be held inactive between transactions.
choice
prompt "Transfer technique"
default STM32L4_QSPI_DMA
---help---
You can choose between using polling, interrupts, or DMA to transfer data
over the QSPI interface.
config STM32L4_QSPI_POLLING
bool "Polling"
---help---
Use conventional register I/O with status polling to transfer data.
config STM32L4_QSPI_INTERRUPTS
bool "Interrupts"
---help---
User interrupt driven I/O transfers.
config STM32L4_QSPI_DMA
bool "DMA"
depends on STM32L4_DMA
---help---
Use DMA to improve QSPI transfer performance.
endchoice
choice
prompt "DMA Channel"
default STM32L4_QSPI_DMA_CHAN_1_5
depends on STM32L4_DMA
---help---
You can choose between two DMA channels for use with QSPI:
either DMA1 channel 5, or DMA2 channel 7.
If you only see one choice here, it is probably because
you have not also enabled the associated DMA controller.
config STM32L4_QSPI_DMA_CHAN_1_5
bool "DMA1 Channel 5"
depends on STM32L4_DMA1
---help---
Use DMA1 channel 5 for QSPI.
config STM32L4_QSPI_DMA_CHAN_2_7
bool "DMA2 Channel 7"
depends on STM32L4_DMA2
---help---
Use DMA2 channel 7 for QSPI.
endchoice
choice
prompt "DMA Priority"
default STM32L4_QSPI_DMAPRIORITY_MEDIUM
depends on STM32L4_DMA
---help---
The DMA controller supports priority levels. You are probably fine
with the default of 'medium' except for special cases. In the event
of contention between to channels at the same priority, the lower
numbered channel has hardware priority over the higher numbered one.
config STM32L4_QSPI_DMAPRIORITY_VERYHIGH
bool "Very High priority"
depends on STM32L4_DMA
---help---
'Highest' priority.
config STM32L4_QSPI_DMAPRIORITY_HIGH
bool "High priority"
depends on STM32L4_DMA
---help---
'High' priority.
config STM32L4_QSPI_DMAPRIORITY_MEDIUM
bool "Medium priority"
depends on STM32L4_DMA
---help---
'Medium' priority.
config STM32L4_QSPI_DMAPRIORITY_LOW
bool "Low priority"
depends on STM32L4_DMA
---help---
'Low' priority.
endchoice
config STM32L4_QSPI_DMATHRESHOLD
int "QSPI DMA threshold"
default 4
depends on STM32L4_QSPI_DMA
---help---
When QSPI DMA is enabled, small DMA transfers will still be performed
by polling logic. This value is the threshold below which transfers
will still be performed by conventional register status polling.
config STM32L4_QSPI_DMADEBUG
bool "QSPI DMA transfer debug"
depends on STM32L4_QSPI_DMA && DEBUG && DEBUG_DMA
default n
---help---
Enable special debug instrumentation to analyze QSPI DMA data transfers.
This logic is as non-invasive as possible: It samples DMA
registers at key points in the data transfer and then dumps all of
the registers at the end of the transfer.
config STM32L4_QSPI_REGDEBUG
bool "QSPI Register level debug"
depends on DEBUG
default n
---help---
Output detailed register-level QSPI device debug information.
Requires also DEBUG.
endif
comment "APB1 Peripherals"
arch/arm/src/stm32l4/README.txt
+2 -2
View File
@@ -23,13 +23,13 @@ LSE : works, but TODO autotrim of MSI, etc
RCC : All registers defined, peripherals enabled, basic clock working
SYSCTL : All registers defined
USART : Working in normal mode (no DMA, to be tested, code is written)
DMA : Ported from STM32, code written, to be tested
DMA : works; at least tested with QSPI
SRAM2 : Should work with enough MM regions
FIREWALL : Code written, to be tested, requires support from ldscript
SPI : Code written, to be tested, including DMA
I2C : Registers defined
RTC : works
QSPI : TODO (port from stm32f7)
QSPI : works in polling, interrupt, DMA, and also memory-mapped modes
CAN : TODO
OTGFS : TODO
Timers : TODO
arch/arm/src/stm32l4/chip/stm32l4x6xx_dma.h
+9 -2
View File
@@ -39,8 +39,7 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* These definitions apply to both the STM32 F1 and F3 families */
/* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */
/* 14 Channels Total: 7 DMA1 Channels(1-7) and 7 DMA2 channels (1-7) */
#define DMA1 0
#define DMA2 1
@@ -158,6 +157,8 @@
#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET)
#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET)
#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET)
#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET)
#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET)
#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n))
#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET)
@@ -165,6 +166,8 @@
#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET)
#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET)
#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET)
#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET)
#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET)
#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n))
#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET)
@@ -172,6 +175,8 @@
#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET)
#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET)
#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET)
#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET)
#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET)
#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n))
#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET)
@@ -179,6 +184,8 @@
#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET)
#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET)
#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET)
#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET)
#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET)
/* Register Bitfield Definitions ****************************************************/
arch/arm/src/stm32l4/stm32l4_dma.h
+16 -17
View File
@@ -3,6 +3,8 @@
*
* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Sebastien Lorquet <sebastien@lorquet.fr>
* dev@ziggurat29.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -57,13 +59,11 @@
* DMA callback function (see dma_callback_t).
*/
# define DMA_STATUS_FEIF 0 /* (Not available in F1) */
# define DMA_STATUS_DMEIF 0 /* (Not available in F1) */
# define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */
# define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */
# define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */
#define DMA_STATUS_ERROR (DMA_STATUS_FEIF|DMA_STATUS_DMEIF|DMA_STATUS_TEIF)
#define DMA_STATUS_ERROR (DMA_STATUS_TEIF)
#define DMA_STATUS_SUCCESS (DMA_STATUS_TCIF|DMA_STATUS_HTIF)
/************************************************************************************
@@ -71,7 +71,7 @@
************************************************************************************/
/* DMA_HANDLE provides an opaque are reference that can be used to represent a DMA
* channel (F1) or a DMA stream (F4).
* channel.
*/
typedef FAR void *DMA_HANDLE;
@@ -81,7 +81,7 @@ typedef FAR void *DMA_HANDLE;
* completion of the DMA.
*
* Input Parameters:
* handle - Refers tot he DMA channel or stream
* handle - Refers tot he DMA channel
* status - A bit encoded value that provides the completion status. See the
* DMASTATUS_* definitions above.
* arg - A user-provided value that was provided when stm32l4_dmastart() was
@@ -93,11 +93,12 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
#ifdef CONFIG_DEBUG_DMA
struct stm32l4_dmaregs_s
{
uint32_t isr;
uint32_t ccr;
uint32_t cndtr;
uint32_t cpar;
uint32_t cmar;
uint32_t isr; /* Interrupt Status Register; each channel gets 4 bits */
uint32_t cselr; /* Channel Selection Register; chooses peripheral bound */
uint32_t ccr; /* Channel Configuration Register; determines functionality */
uint32_t cndtr; /* Channel Count Register; determines number of transfers */
uint32_t cpar; /* Channel Peripheral Address Register; determines start */
uint32_t cmar; /* Channel Memory Address Register; determines start */
};
#endif
@@ -126,7 +127,7 @@ extern "C"
* Description:
* Allocate a DMA channel. This function gives the caller mutually
* exclusive access to the DMA channel specified by the 'chan' argument.
* DMA channels are shared on the STM32: Devices sharing the same DMA
* DMA channels are shared on the STM32L4: Devices sharing the same DMA
* channel cannot do DMA concurrently! See the DMACHAN_* definitions in
* stm32l4_dma.h.
*
@@ -142,10 +143,8 @@ extern "C"
*
* Input parameter:
* chan - Identifies the stream/channel resource
* For the STM32 F1, this is simply the channel number as provided by
* the DMACHAN_* definitions in chip/stm32f10xxx_dma.h.
* For the STM32 F4, this is a bit encoded value as provided by the
* the DMAMAP_* definitions in chip/stm32f40xxx_dma.h
* This is a bit encoded value as provided by the DMACHAN_* definitions
* in chip/stm32l4x6xx_dma.h
*
* Returned Value:
* Provided that 'chan' is valid, this function ALWAYS returns a non-NULL,
@@ -153,8 +152,8 @@ extern "C"
* assert if debug is enabled or do something ignorant otherwise).
*
* Assumptions:
* - The caller does not hold he DMA channel.
* - The caller can wait for the DMA channel to be freed if it is no
* - The caller does not hold the DMA channel.
* - The caller can wait for the DMA channel to be freed if it is not
* available.
*
****************************************************************************/
arch/arm/src/stm32l4/stm32l4_qspi.c
+507 -56
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/stm32l4/stm32l4x6xx_dma.c
+30 -14
View File
@@ -3,6 +3,8 @@
*
* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Sebastien Lorquet <sebastien@lorquet.fr>
* dev@ziggurat29.com
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -306,16 +308,17 @@ static int stm32l4_dmainterrupt(int irq, void *context)
isr = dmabase_getreg(dmach, STM32L4_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmach->chan);
/* Clear the interrupts we are handling */
dmabase_putreg(dmach, STM32L4_DMA_IFCR_OFFSET, isr);
/* Invoke the callback */
if (dmach->callback)
{
dmach->callback(dmach, isr >> DMA_ISR_CHAN_SHIFT(dmach->chan), dmach->arg);
}
/* Clear the interrupts we are handling */
dmabase_putreg(dmach, STM32L4_DMA_IFCR_OFFSET, isr);
return OK;
}
@@ -387,9 +390,9 @@ void weak_function up_dmainitialize(void)
* version. Feel free to do that if that is what you need.
*
* Input parameter:
* chndx - Identifies the stream/channel resource. For the STM32 F1, this
* is simply the channel number as provided by the DMACHAN_* definitions
* in chip/stm32f10xxx_dma.h.
* chan - Identifies the stream/channel resource
* This is a bit encoded value as provided by the DMACHAN_* definitions
* in chip/stm32l4x6xx_dma.h
*
* Returned Value:
* Provided that 'chndx' is valid, this function ALWAYS returns a non-NULL,
@@ -471,6 +474,9 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle;
uint32_t regval;
DEBUGASSERT(handle != NULL);
DEBUGASSERT(ntransfers<65536);
/* Then DMA_CNDTRx register can only be modified if the DMA channel is
* disabled.
*/
@@ -514,7 +520,12 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
regval |= ccr;
dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, regval);
#warning TODO define peripheral by using dmach->function
/* define peripheral indicated in dmach->function */
regval = dmabase_getreg(dmach, STM32L4_DMA_CSELR_OFFSET);
regval &= (0x0f << (dmach->chan << 2));
regval |= (dmach->function << (dmach->chan << 2));
dmabase_putreg(dmach, STM32L4_DMA_CSELR_OFFSET, regval);
}
/****************************************************************************
@@ -641,7 +652,9 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
* Transfers to/from memory performed by the DMA controller are
* required to be aligned to their size.
*
* See ST RM0090 rev4, section 9.3.11
* Datasheet 3.13 claims
* "Access to Flash, SRAM, APB and AHB peripherals as source
* and destination"
*
* Compute mend inline to avoid a possible non-constant integer
* multiply.
@@ -682,13 +695,14 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
switch (maddr & STM32L4_REGION_MASK)
{
#if defined(CONFIG_STM32L4_STM32F10XX)
case STM32L4_PERIPH_BASE:
case STM32L4_FSMC_BASE:
case STM32L4_FSMC_BANK1:
case STM32L4_FSMC_BANK2:
case STM32L4_FSMC_BANK3:
case STM32L4_FSMC_BANK4:
#endif
case STM32L4_SRAM_BASE:
case STM32L4_SRAM2_BASE:
case STM32L4_CODE_BASE:
/* All RAM and flash is supported */
@@ -719,13 +733,14 @@ void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs)
struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle;
irqstate_t flags;
flags = irqsave();
flags = enter_critical_section();
regs->isr = dmabase_getreg(dmach, STM32L4_DMA_ISR_OFFSET);
regs->cselr = dmabase_getreg(dmach, STM32L4_DMA_CSELR_OFFSET);
regs->ccr = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET);
regs->cndtr = dmachan_getreg(dmach, STM32L4_DMACHAN_CNDTR_OFFSET);
regs->cpar = dmachan_getreg(dmach, STM32L4_DMACHAN_CPAR_OFFSET);
regs->cmar = dmachan_getreg(dmach, STM32L4_DMACHAN_CMAR_OFFSET);
irqrestore(flags);
leave_critical_section(flags);
}
#endif
@@ -748,7 +763,8 @@ void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs,
uint32_t dmabase = DMA_BASE(dmach->base);
dmadbg("DMA Registers: %s\n", msg);
dmadbg(" ISRC[%08x]: %08x\n", dmabase + STM32L4_DMA_ISR_OFFSET, regs->isr);
dmadbg(" ISR[%08x]: %08x\n", dmabase + STM32L4_DMA_ISR_OFFSET, regs->isr);
dmadbg(" CSELR[%08x]: %08x\n", dmabase + STM32L4_DMA_CSELR_OFFSET, regs->cselr);
dmadbg(" CCR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CCR_OFFSET, regs->ccr);
dmadbg(" CNDTR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CNDTR_OFFSET, regs->cndtr);
dmadbg(" CPAR[%08x]: %08x\n", dmach->base + STM32L4_DMACHAN_CPAR_OFFSET, regs->cpar);
configs/stm32l476vg-disco/include/board.h
-10
View File
@@ -144,16 +144,6 @@
#define GPIO_QSPI_IO3 (GPIO_QSPI_BK1_IO3_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
#define GPIO_QSPI_SCK (GPIO_QSPI_CLK_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
#if 0
/* XXX hmm, elsewhere */
#define QSPI_USE_INTERRUPTS 1
/* XXX hmm, better? (2^(23+1)); this is the value that goes into FSIZE */
#define QSPI_FLASH_SIZE 23
#endif
/* SPI */
/* XXX is SPI1 used on Disco? */
configs/stm32l476vg-disco/nsh/defconfig
+23 -31
View File
@@ -59,6 +59,7 @@ CONFIG_DEBUG_VERBOSE=y
#
# OS Function Debug Options
#
# CONFIG_DEBUG_DMA is not set
# CONFIG_DEBUG_HEAP is not set
# CONFIG_DEBUG_IRQ is not set
@@ -176,6 +177,7 @@ CONFIG_ARMV7M_HAVE_STACKCHECK=y
# CONFIG_ARMV7M_ITMSYSLOG is not set
# CONFIG_SERIAL_TERMIOS is not set
# CONFIG_USART2_RS485 is not set
# CONFIG_USART2_RXDMA is not set
# CONFIG_SERIAL_DISABLE_REORDERING is not set
#
@@ -197,7 +199,7 @@ CONFIG_STM32L4_FLASH_1024KB=y
# CONFIG_STM32L4_ADC is not set
# CONFIG_STM32L4_CAN is not set
# CONFIG_STM32L4_DAC is not set
# CONFIG_STM32L4_DMA is not set
CONFIG_STM32L4_DMA=y
# CONFIG_STM32L4_I2C is not set
# CONFIG_STM32L4_SAI is not set
# CONFIG_STM32L4_SPI is not set
@@ -207,8 +209,8 @@ CONFIG_STM32L4_USART=y
#
# AHB1 Peripherals
#
# CONFIG_STM32L4_DMA1 is not set
# CONFIG_STM32L4_DMA2 is not set
CONFIG_STM32L4_DMA1=y
CONFIG_STM32L4_DMA2=y
# CONFIG_STM32L4_CRC is not set
# CONFIG_STM32L4_TSC is not set
@@ -230,6 +232,17 @@ CONFIG_STM32L4_QSPI=y
CONFIG_STM32L4_QSPI_FLASH_SIZE=16777216
CONFIG_STM32L4_QSPI_FIFO_THESHOLD=4
CONFIG_STM32L4_QSPI_CSHT=1
# CONFIG_STM32L4_QSPI_POLLING is not set
# CONFIG_STM32L4_QSPI_INTERRUPTS is not set
CONFIG_STM32L4_QSPI_DMA=y
CONFIG_STM32L4_QSPI_DMA_CHAN_1_5=y
# CONFIG_STM32L4_QSPI_DMA_CHAN_2_7 is not set
# CONFIG_STM32L4_QSPI_DMAPRIORITY_VERYHIGH is not set
# CONFIG_STM32L4_QSPI_DMAPRIORITY_HIGH is not set
CONFIG_STM32L4_QSPI_DMAPRIORITY_MEDIUM=y
# CONFIG_STM32L4_QSPI_DMAPRIORITY_LOW is not set
CONFIG_STM32L4_QSPI_DMATHRESHOLD=4
# CONFIG_STM32L4_QSPI_REGDEBUG is not set
#
# APB1 Peripherals
@@ -302,7 +315,7 @@ CONFIG_STM32L4_SAI1PLL=y
#
# CONFIG_ARCH_NOINTC is not set
# CONFIG_ARCH_VECNOTIRQ is not set
# CONFIG_ARCH_DMA is not set
CONFIG_ARCH_DMA=y
CONFIG_ARCH_HAVE_IRQPRIO=y
# CONFIG_ARCH_L2CACHE is not set
# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set
@@ -384,7 +397,7 @@ CONFIG_LIB_BOARDCTL=y
# CONFIG_BOARDCTL_ADCTEST is not set
# CONFIG_BOARDCTL_PWMTEST is not set
# CONFIG_BOARDCTL_GRAPHICS is not set
# CONFIG_BOARDCTL_IOCTL is not set
CONFIG_BOARDCTL_IOCTL=y
#
# RTOS Features
@@ -646,12 +659,7 @@ CONFIG_USART2_2STOP=0
#
# System Logging
#
CONFIG_RAMLOG=y
CONFIG_RAMLOG_SYSLOG=y
# CONFIG_RAMLOG_CONSOLE is not set
CONFIG_RAMLOG_BUFSIZE=8192
# CONFIG_RAMLOG_CRLF is not set
CONFIG_RAMLOG_NONBLOCKING=y
# CONFIG_RAMLOG is not set
# CONFIG_SYSLOG_CONSOLE is not set
#
@@ -708,9 +716,8 @@ CONFIG_FS_PROCFS_REGISTER=y
#
# System Logging
#
CONFIG_SYSLOG=y
# CONFIG_SYSLOG is not set
# CONFIG_SYSLOG_TIMESTAMP is not set
# CONFIG_SYSLOG_CHAR is not set
#
# Graphics Support
@@ -838,14 +845,7 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7"
# CONFIG_EXAMPLES_CXXTEST is not set
# CONFIG_EXAMPLES_DHCPD is not set
# CONFIG_EXAMPLES_ELF is not set
CONFIG_EXAMPLES_FSTEST=y
CONFIG_EXAMPLES_FSTEST_MAXNAME=32
CONFIG_EXAMPLES_FSTEST_MAXFILE=8192
CONFIG_EXAMPLES_FSTEST_MAXIO=347
CONFIG_EXAMPLES_FSTEST_MAXOPEN=512
CONFIG_EXAMPLES_FSTEST_MOUNTPT="/mnt/n25qxxx"
CONFIG_EXAMPLES_FSTEST_NLOOPS=1
CONFIG_EXAMPLES_FSTEST_VERBOSE=y
# CONFIG_EXAMPLES_FSTEST is not set
# CONFIG_EXAMPLES_FTPC is not set
# CONFIG_EXAMPLES_FTPD is not set
# CONFIG_EXAMPLES_HELLO is not set
@@ -871,20 +871,12 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
# CONFIG_EXAMPLES_NXIMAGE is not set
# CONFIG_EXAMPLES_NXLINES is not set
# CONFIG_EXAMPLES_NXTEXT is not set
CONFIG_EXAMPLES_OSTEST=y
CONFIG_EXAMPLES_OSTEST_LOOPS=1
CONFIG_EXAMPLES_OSTEST_STACKSIZE=8192
CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=8
CONFIG_EXAMPLES_OSTEST_RR_RANGE=10000
CONFIG_EXAMPLES_OSTEST_RR_RUNS=10
CONFIG_EXAMPLES_OSTEST_WAITRESULT=y
# CONFIG_EXAMPLES_OSTEST is not set
# CONFIG_EXAMPLES_PCA9635 is not set
# CONFIG_EXAMPLES_PIPE is not set
# CONFIG_EXAMPLES_PPPD is not set
# CONFIG_EXAMPLES_POSIXSPAWN is not set
CONFIG_EXAMPLES_RANDOM=y
CONFIG_EXAMPLES_MAXSAMPLES=64
CONFIG_EXAMPLES_NSAMPLES=8
# CONFIG_EXAMPLES_RANDOM is not set
# CONFIG_EXAMPLES_RGBLED is not set
# CONFIG_EXAMPLES_RGMP is not set
# CONFIG_EXAMPLES_SENDMAIL is not set
configs/stm32l476vg-disco/src/stm32_appinit.c
+16 -2
View File
@@ -45,6 +45,8 @@
#include <syslog.h>
#include <errno.h>
#include <debug.h>
#include <string.h>
#include <stdlib.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
@@ -57,6 +59,7 @@
#include <nuttx/fs/fs.h>
#include <nuttx/fs/ramdisk.h>
#include <nuttx/fs/nxffs.h>
#include <nuttx/fs/mkfatfs.h>
#include <nuttx/binfmt/elf.h>
#include <nuttx/i2c/i2c_master.h>
@@ -193,6 +196,7 @@ int board_app_initialize(void)
#ifdef HAVE_N25QXXX_SMARTFS
/* Configure the device with no partition support */
SYSLOG("doing smart_initialize()\n");
ret = smart_initialize(N25QXXX_SMART_MINOR, mtd, NULL);
if (ret != OK)
{
@@ -202,6 +206,7 @@ int board_app_initialize(void)
#elif defined(HAVE_N25QXXX_NXFFS)
/* Initialize to provide NXFFS on the N25QXXX MTD interface */
SYSLOG("doing nxffs_initialize()\n");
ret = nxffs_initialize(mtd);
if (ret < 0)
{
@@ -237,9 +242,9 @@ int board_app_initialize(void)
/* NOTE: for this to work, you will need to make sure that
* CONFIG_FS_WRITABLE is set in the config. It's not a user-
* visible setting, but you can make it set by selecting an
* arbitrary writeable file system (you don't have to actually
* arbitrary writable file system (you don't have to actually
* use it, just select it so that the block device created via
* ftl_initialize() will be writeable). Personally, I chose FAT,
* ftl_initialize() will be writable). Personally, I chose FAT,
* because SMARTFS and NXFFS will cause the other code branches
* above to become active.
*/
@@ -257,3 +262,12 @@ int board_app_initialize(void)
return OK;
}
#endif /* CONFIG_LIB_BOARDCTL */
#ifdef CONFIG_BOARDCTL_IOCTL
int board_ioctl(unsigned int cmd, uintptr_t arg)
{
return OK;
}
#endif