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mem barrier: use UP_DMP UP_DSP as barriers standard API

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Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
This commit is contained in:
lipengfei28
2024-12-11 14:26:43 +08:00
committed by Xiang Xiao
parent afe90db5c4
commit 2d1af01d44
16 changed files with 66 additions and 66 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/include/spinlock.h
+4 -4
View File
@@ -61,12 +61,12 @@
* all memory accesses are complete
*/
#define SP_DSB() __asm__ __volatile__ ("dsb sy" : : : "memory")
#define SP_DMB() __asm__ __volatile__ ("dmb st" : : : "memory")
#define UP_DSB() __asm__ __volatile__ ("dsb sy" : : : "memory")
#define UP_DMB() __asm__ __volatile__ ("dmb st" : : : "memory")
#ifdef CONFIG_ARM_HAVE_WFE_SEV
#define SP_WFE() __asm__ __volatile__ ("wfe" : : : "memory")
#define SP_SEV() __asm__ __volatile__ ("sev" : : : "memory")
#define UP_WFE() __asm__ __volatile__ ("wfe" : : : "memory")
#define UP_SEV() __asm__ __volatile__ ("sev" : : : "memory")
#endif
/****************************************************************************
arch/arm/src/cxd56xx/cxd56_testset.c
+1 -1
View File
@@ -111,7 +111,7 @@ spinlock_t up_testset(volatile spinlock_t *lock)
if (ret == SP_UNLOCKED)
{
*lock = SP_LOCKED;
SP_DMB();
UP_DMB();
}
/* Unlock hardware semaphore */
arch/arm/src/lc823450/lc823450_testset.c
+2 -2
View File
@@ -81,7 +81,7 @@ spinlock_t up_testset(volatile spinlock_t *lock)
}
while (getreg32(MUTEX_REG_MUTEX0) != val);
SP_DMB();
UP_DMB();
ret = *lock;
@@ -90,7 +90,7 @@ spinlock_t up_testset(volatile spinlock_t *lock)
*lock = SP_LOCKED;
}
SP_DMB();
UP_DMB();
val = (this_cpu() << 16) | 0x0;
putreg32(val, MUTEX_REG_MUTEX0);
arch/arm/src/rp2040/rp2040_testset.c
+1 -1
View File
@@ -75,7 +75,7 @@ spinlock_t up_testset(volatile spinlock_t *lock)
if (ret == SP_UNLOCKED)
{
*lock = SP_LOCKED;
SP_DMB();
UP_DMB();
}
/* Unlock hardware spinlock */
arch/arm64/include/spinlock.h
+4 -4
View File
@@ -61,11 +61,11 @@
* all memory accesses are complete
*/
#define SP_DSB() __asm__ __volatile__ ("dsb sy" : : : "memory")
#define SP_DMB() __asm__ __volatile__ ("dmb st" : : : "memory")
#define UP_DSB() __asm__ __volatile__ ("dsb sy" : : : "memory")
#define UP_DMB() __asm__ __volatile__ ("dmb st" : : : "memory")
#define SP_WFE() __asm__ __volatile__ ("wfe" : : : "memory")
#define SP_SEV() __asm__ __volatile__ ("sev" : : : "memory")
#define UP_WFE() __asm__ __volatile__ ("wfe" : : : "memory")
#define UP_SEV() __asm__ __volatile__ ("sev" : : : "memory")
#ifndef __ASSEMBLY__
arch/arm64/src/common/arm64_cpustart.c
+1 -1
View File
@@ -156,7 +156,7 @@ static void arm64_start_cpu(int cpu_num)
return;
}
#else
SP_SEV();
UP_SEV();
#endif
}
arch/ceva/include/spinlock.h
+2 -2
View File
@@ -63,8 +63,8 @@
*
*/
#define SP_DSB() up_dsb()
#define SP_DMB() up_dmb()
#define UP_DSB() up_dsb()
#define UP_DMB() up_dmb()
/****************************************************************************
* Public Types
arch/risc-v/include/spinlock.h
+2 -2
View File
@@ -61,8 +61,8 @@
*
*/
#define SP_DSB() __asm__ __volatile__ ("fence")
#define SP_DMB() __asm__ __volatile__ ("fence")
#define UP_DSB() __asm__ __volatile__ ("fence")
#define UP_DMB() __asm__ __volatile__ ("fence")
/****************************************************************************
* Public Types
arch/tricore/include/spinlock.h
+2 -2
View File
@@ -47,8 +47,8 @@
* barrier.
*/
#define SP_DSB() __dsync()
#define SP_DMB() __asm("":::"memory")
#define UP_DSB() __dsync()
#define UP_DMB() __asm("":::"memory")
/****************************************************************************
* Public Types
arch/x86_64/include/spinlock.h
+2 -2
View File
@@ -57,8 +57,8 @@
*
*/
#define SP_DSB() __asm__ __volatile__ ("mfence")
#define SP_DMB() __asm__ __volatile__ ("mfence")
#define UP_DSB() __asm__ __volatile__ ("mfence")
#define UP_DMB() __asm__ __volatile__ ("mfence")
/****************************************************************************
* Public Types
arch/x86_64/src/common/x86_64_addrenv.c
+8 -8
View File
@@ -169,7 +169,7 @@ static int create_spgtables(arch_addrenv_t *addrenv)
/* Flush the data cache, so the changes are committed to memory */
SP_DMB();
UP_DMB();
return i;
}
@@ -304,7 +304,7 @@ static int x86_64_create_region(arch_addrenv_t *addrenv, uintptr_t vaddr,
/* Flush the data cache, so the changes are committed to memory */
SP_DMB();
UP_DMB();
return npages;
}
@@ -459,8 +459,8 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
/* When all is set and done, flush the data caches */
SP_DSB();
SP_DMB();
UP_DSB();
UP_DMB();
#ifdef CONFIG_SMP
x86_64_tlb_shootdown();
@@ -505,8 +505,8 @@ int up_addrenv_destroy(arch_addrenv_t *addrenv)
/* Make sure the caches are flushed before doing this */
SP_DSB();
SP_DMB();
UP_DSB();
UP_DMB();
/* Things start from the beginning of the user virtual memory */
@@ -557,8 +557,8 @@ int up_addrenv_destroy(arch_addrenv_t *addrenv)
/* When all is set and done, flush the caches */
SP_DSB();
SP_DMB();
UP_DSB();
UP_DMB();
#ifdef CONFIG_SMP
x86_64_tlb_shootdown();
arch/x86_64/src/intel64/intel64_cpustart.c
+2 -2
View File
@@ -89,7 +89,7 @@ static int x86_64_ap_startup(int cpu)
/* Wait for 10 ms */
up_mdelay(10);
SP_DMB();
UP_DMB();
/* Send an STARTUP IPI to the CPU */
@@ -101,7 +101,7 @@ static int x86_64_ap_startup(int cpu)
do
{
up_udelay(300);
SP_DMB();
UP_DMB();
sinfo("wait for startup cpu=%d...\n", cpu);
}
while (x86_64_cpu_ready_get(cpu) == false);
drivers/net/e1000.c
+1 -1
View File
@@ -596,7 +596,7 @@ static int e1000_transmit(FAR struct netdev_lowerhalf_s *dev,
priv->tx[desc].cso = 0;
priv->tx[desc].status = 0;
SP_DSB();
UP_DSB();
/* Update TX tail */
drivers/net/igc.c
+1 -1
View File
@@ -550,7 +550,7 @@ static int igc_transmit(FAR struct netdev_lowerhalf_s *dev,
priv->tx[desc].cso = 0;
priv->tx[desc].status = 0;
SP_DSB();
UP_DSB();
/* Update TX tail */
include/nuttx/spinlock.h
+31 -31
View File
@@ -63,22 +63,22 @@ extern "C"
*/
#undef __SP_UNLOCK_FUNCTION
#if !defined(SP_DMB)
# define SP_DMB()
#if !defined(UP_DMB)
# define UP_DMB()
#else
# define __SP_UNLOCK_FUNCTION 1
#endif
#if !defined(SP_DSB)
# define SP_DSB()
#if !defined(UP_DSB)
# define UP_DSB()
#endif
#if !defined(SP_WFE)
# define SP_WFE()
#if !defined(UP_WFE)
# define UP_WFE()
#endif
#if !defined(SP_SEV)
# define SP_SEV()
#if !defined(UP_SEV)
# define UP_SEV()
#endif
#if !defined(__SP_UNLOCK_FUNCTION) && (defined(CONFIG_TICKET_SPINLOCK) || \
@@ -199,11 +199,11 @@ static inline_function void spin_lock_wo_note(FAR volatile spinlock_t *lock)
while (up_testset(lock) == SP_LOCKED)
#endif
{
SP_DSB();
SP_WFE();
UP_DSB();
UP_WFE();
}
SP_DMB();
UP_DMB();
}
#endif /* CONFIG_SPINLOCK */
@@ -280,11 +280,11 @@ spin_trylock_wo_note(FAR volatile spinlock_t *lock)
if (up_testset(lock) == SP_LOCKED)
#endif /* CONFIG_TICKET_SPINLOCK */
{
SP_DSB();
UP_DSB();
return false;
}
SP_DMB();
UP_DMB();
return true;
}
#endif /* CONFIG_SPINLOCK */
@@ -361,14 +361,14 @@ static inline_function bool spin_trylock(FAR volatile spinlock_t *lock)
static inline_function void
spin_unlock_wo_note(FAR volatile spinlock_t *lock)
{
SP_DMB();
UP_DMB();
#ifdef CONFIG_TICKET_SPINLOCK
atomic_fetch_add(&lock->owner, 1);
#else
*lock = SP_UNLOCKED;
#endif
SP_DSB();
SP_SEV();
UP_DSB();
UP_SEV();
}
#endif /* CONFIG_SPINLOCK */
@@ -686,8 +686,8 @@ static inline_function void read_lock(FAR volatile rwlock_t *lock)
if (old <= RW_SP_WRITE_LOCKED)
{
DEBUGASSERT(old == RW_SP_WRITE_LOCKED);
SP_DSB();
SP_WFE();
UP_DSB();
UP_WFE();
}
else if(atomic_cmpxchg(lock, &old, old + 1))
{
@@ -695,7 +695,7 @@ static inline_function void read_lock(FAR volatile rwlock_t *lock)
}
}
SP_DMB();
UP_DMB();
}
/****************************************************************************
@@ -738,7 +738,7 @@ static inline_function bool read_trylock(FAR volatile rwlock_t *lock)
}
}
SP_DMB();
UP_DMB();
return true;
}
@@ -763,10 +763,10 @@ static inline_function void read_unlock(FAR volatile rwlock_t *lock)
{
DEBUGASSERT(atomic_read(lock) >= RW_SP_READ_LOCKED);
SP_DMB();
UP_DMB();
atomic_fetch_sub(lock, 1);
SP_DSB();
SP_SEV();
UP_DSB();
UP_SEV();
}
/****************************************************************************
@@ -800,11 +800,11 @@ static inline_function void write_lock(FAR volatile rwlock_t *lock)
while (!atomic_cmpxchg(lock, &zero, RW_SP_WRITE_LOCKED))
{
SP_DSB();
SP_WFE();
UP_DSB();
UP_WFE();
}
SP_DMB();
UP_DMB();
}
/****************************************************************************
@@ -838,11 +838,11 @@ static inline_function bool write_trylock(FAR volatile rwlock_t *lock)
if (atomic_cmpxchg(lock, &zero, RW_SP_WRITE_LOCKED))
{
SP_DMB();
UP_DMB();
return true;
}
SP_DSB();
UP_DSB();
return false;
}
@@ -869,10 +869,10 @@ static inline_function void write_unlock(FAR volatile rwlock_t *lock)
DEBUGASSERT(atomic_read(lock) == RW_SP_WRITE_LOCKED);
SP_DMB();
UP_DMB();
atomic_set(lock, RW_SP_UNLOCKED);
SP_DSB();
SP_SEV();
UP_DSB();
UP_SEV();
}
/****************************************************************************
libs/libc/machine/arch_atomic.c
+2 -2
View File
@@ -788,8 +788,8 @@ SYNC_VAL_CMP_SWAP(__sync_val_compare_and_swap_, 8, uint64_t)
void weak_function __sync_synchronize(void)
{
#ifdef SP_DMB
SP_DMB();
#ifdef UP_DMB
UP_DMB();
#endif
}